Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4988
-gerrit
commit 598bdd76126cfd2414c5ddac55e376feb7104adf
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Dec 4 18:34:11 2013 -0800
baytrail: Fix _CRS to build with new IASL
The new IASL is complaining about the PCI memory region not
having consistent base/end/length values because they are
placeholder that are fixed up in the method before returning.
Put in some more valid placeholder values to make it happy.
BUG=chromium:311294
BRANCH=none
TEST=build and boot with IASL 20130117 on rambi
Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178864
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Commit-Queue: Duncan Laurie <dlaurie(a)google.com>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/acpi/southcluster.asl | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 7760869..49349c4 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -160,8 +160,8 @@ Method (_CRS, 0, Serialized)
// PCI Memory Region (Top of memory-0xfeafffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xfeafffff, 0x00000000,
- 0x00000000,,, PMEM)
+ 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
+ 0x00100000,,, PMEM)
// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4974
-gerrit
commit f78d099ebd918bb0343fc9207ccea93b3f7f5cdf
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 14 13:47:08 2013 -0600
baytrail: ensure init_chromeos() is called in romstage
The TPM needs to have the TPM_Startup command sent to it
on all boot paths. The call init_chromeos() in romstage_common()
fulfills this requirement.
BUG=chrome-os-partner:24057
BRANCH=None
TEST=Built and booted. Was able to suspend to ram multiple times
in a row.
Change-Id: Id0339a9d82897249d20ff5f62d2dcb8b535310fa
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176803
Reviewed-by: Todd Broch <tbroch(a)chromium.org>
Tested-by: Todd Broch <tbroch(a)chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/soc/intel/baytrail/romstage/romstage.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 19a7153..0416a52 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -181,6 +181,16 @@ static int chipset_prev_sleep_state(void)
return prev_sleep_state;
}
+#if CONFIG_CHROMEOS
+static inline void chromeos_init(int prev_sleep_state)
+{
+ /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */
+ init_chromeos(prev_sleep_state == 3 ? 2 : 0);
+}
+#else
+static inline void chromeos_init(int prev_sleep_state) {}
+#endif
+
/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
@@ -208,6 +218,8 @@ void romstage_common(struct romstage_params *params)
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
+ chromeos_init(prev_sleep_state);
+
/* Save timestamp information. */
timestamp_init(ts64_to_tsc(params->ts.times[0]));
timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4972
-gerrit
commit 259dd21dd35ac874c2beea40a2b69a05656db908
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 14 11:06:17 2013 -0600
baytrail: don't allow PCIE wake ups
The PCIe subsystem was constantly waking up boards from
S3 and S5. Completely disable PCIe wake ups. It can be made
mainboard-configurable later if needed.
BUG=chrome-os-partner:24004
BRANCH=None
TEST=Both S3 and EC RW->RW update (trip through S5) don't
cause wakeups.
Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176791
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/soc/intel/baytrail/smm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index c654c85..e10c70b 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -93,8 +93,8 @@ void southcluster_smm_enable_smi(void)
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
- /* Configure events */
- enable_pm1(PWRBTN_EN | GBL_EN);
+ /* Configure events Disable pcie wake. */
+ enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */