Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4997
-gerrit
commit 56bd6dfebcda8863d12f72e339560d62deaa953f
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Dec 10 08:35:51 2013 -0800
baytrail: allow SD card controller capabilities overrides
The SD card controller can have the capabilities it supports
to be overridden. Add two optional fields to the chip structure
to allow the mainboard to override the SD card controller
capabilities.
BUG=chrome-os-partner:24423
BRANCH=None
TEST=Built and booted. Noted capabilities override console output.
Change-Id: Ibfef8f765b35eeec6da969dd05f5484f8672a7b9
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179414
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/Makefile.inc | 1 +
src/soc/intel/baytrail/chip.h | 4 +++
src/soc/intel/baytrail/sd.c | 65 +++++++++++++++++++++++++++++++++++++
3 files changed, 70 insertions(+)
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index f418bed..63e7c61 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -43,6 +43,7 @@ ramstage-y += scc.c
ramstage-y += emmc.c
ramstage-y += lpss.c
ramstage-y += pcie.c
+ramstage-y += sd.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 250f644..43a3efb 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -51,6 +51,10 @@ struct soc_intel_baytrail_config {
/* LPE Audio Clock configuration. */
int lpe_codec_clk_freq; /* 19 or 25 are valid. */
int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
+
+ /* Native SD Card controller - override controller capabilities. */
+ uint32_t sdcard_cap_low;
+ uint32_t sdcard_cap_high;
};
extern struct chip_operations soc_intel_baytrail_ops;
diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c
new file mode 100644
index 0000000..82833c3
--- /dev/null
+++ b/src/soc/intel/baytrail/sd.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <reg_script.h>
+
+#include <baytrail/pci_devs.h>
+#include <baytrail/ramstage.h>
+#include "chip.h"
+
+#define CAP_OVERRIDE_LOW 0xa0
+#define CAP_OVERRIDE_HIGH 0xa4
+# define USE_CAP_OVERRIDES (1 << 31)
+
+static void sd_init(device_t dev)
+{
+ struct soc_intel_baytrail_config *config = dev->chip_info;
+
+ if (config == NULL)
+ return;
+
+ if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) {
+ printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n");
+ pci_write_config32(dev, CAP_OVERRIDE_LOW,
+ config->sdcard_cap_low);
+ pci_write_config32(dev, CAP_OVERRIDE_HIGH,
+ config->sdcard_cap_high | USE_CAP_OVERRIDES);
+ }
+}
+
+static const struct device_operations device_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sd_init,
+ .enable = NULL,
+ .scan_bus = NULL,
+ .ops_pci = &soc_pci_ops,
+};
+
+static const struct pci_driver southcluster __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = SD_DEVID,
+};
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4996
-gerrit
commit a8c19b2b2b3dcc22fc8514ed4213bde96d167def
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Dec 9 15:03:34 2013 -0800
baytrail: fix nvs offsets
The VDAT data was off by 2 bytes when reading it from the
kernel. The reason is that the header did not line up
correctly with actual ACPI code.
BUG=chrome-os-partner:24440
BRANCH=None
TEST=crossystem devsw_cur now returns either 0 or 1 depending
on state.
Change-Id: Ie78599f29cd5daf7da98db5e37fa276d24339f6a
Signed-off-by: Aaron durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179372
---
src/soc/intel/baytrail/baytrail/nvs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h
index 1cd4246..ae1f099 100644
--- a/src/soc/intel/baytrail/baytrail/nvs.h
+++ b/src/soc/intel/baytrail/baytrail/nvs.h
@@ -50,12 +50,12 @@ typedef struct {
u32 cmem; /* 0x30 - CBMEM TOC */
u32 tolm; /* 0x34 - Top of Low Memory */
u32 cbmc; /* 0x38 - coreboot memconsole */
- u8 rsvd5[39];
+ u8 rsvd5[36];
/* Serial IO device BARs */
u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */
u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */
- u8 rsvd6[95];
+ u8 rsvd6[96];
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4998
-gerrit
commit ea92a6c66c571ee11ee02ea70fa2475cbbbe5560
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Dec 10 09:01:41 2013 -0800
rambi: limit SD card controller to 2.0 spec
The rambi board can only meet the SD card 2.0 specification.
Therefore, the controller capabilities need to be overridden
to match.
BUG=chrome-os-partner:24423
BRANCH=None
TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows
high speed as maximum timing as well as 3.3V signal voltage.
Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179415
---
src/mainboard/google/rambi/devicetree.cb | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 1c24d57..96772ac 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -27,6 +27,10 @@ chip soc/intel/baytrail
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+ # SD Card controller
+ register "sdcard_cap_low" = "0x036864b2"
+ register "sdcard_cap_high" = "0x0"
+
device cpu_cluster 0 on
device lapic 0 on end
end