Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5047
-gerrit
commit bca56efcc60ee18133d39f662d703868edfdc856
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Jan 14 17:28:33 2014 -0600
cpu/intel: allow non-packaged scoped turbo setting
In the past the turbo disable setting (bit 38) of the
IA32_MISC_ENABLES msr has been package scoped. That means
knocking the turbo disable bit down enabled turbo for the
entire package. Sadly, that's no longer true on all Intel
processors. Therefore, allow non-packaged scoped turbo
setting by introducing the CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
Kconfig option. It defaults to false which was the original
assumption.
BUG=chrome-os-partner:25014
BRANCH=baytrail
TEST=Built and ran both ways successfully.
Change-Id: I71a31e76ff47878023081fc47da643187517b597
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182405
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/cpu/intel/Kconfig | 1 +
src/cpu/intel/turbo/Kconfig | 6 ++++++
src/cpu/intel/turbo/turbo.c | 27 +++++++++++++++++++++++++--
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 6f4f561..af03619 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -37,3 +37,4 @@ source src/cpu/intel/socket_LGA775/Kconfig
source src/cpu/intel/socket_rPGA989/Kconfig
# Architecture specific features
source src/cpu/intel/fit/Kconfig
+source src/cpu/intel/turbo/Kconfig
diff --git a/src/cpu/intel/turbo/Kconfig b/src/cpu/intel/turbo/Kconfig
new file mode 100644
index 0000000..5432c28
--- /dev/null
+++ b/src/cpu/intel/turbo/Kconfig
@@ -0,0 +1,6 @@
+
+config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+ def_bool n
+ help
+ This option indicates that the turbo mode setting is not package
+ scoped. i.e. enable_turbo() needs to be called on not just the bsp
diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
index 779550e..7599ff1 100644
--- a/src/cpu/intel/turbo/turbo.c
+++ b/src/cpu/intel/turbo/turbo.c
@@ -24,7 +24,28 @@
#include <cpu/x86/msr.h>
#include <arch/cpu.h>
-static int turbo_state = TURBO_UNKNOWN;
+#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+static inline int get_global_turbo_state(void)
+{
+ return TURBO_UNKNOWN;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+}
+#else
+static int g_turbo_state = TURBO_UNKNOWN;
+
+static inline int get_global_turbo_state(void)
+{
+ return g_turbo_state;
+}
+
+static inline void set_global_turbo_state(int state)
+{
+ g_turbo_state = state;
+}
+#endif
static const char *turbo_state_desc[] = {
[TURBO_UNKNOWN] = "unknown",
@@ -43,6 +64,7 @@ int get_turbo_state(void)
struct cpuid_result cpuid_regs;
int turbo_en, turbo_cap;
msr_t msr;
+ int turbo_state = get_global_turbo_state();
/* Return cached state if available */
if (turbo_state != TURBO_UNKNOWN)
@@ -65,6 +87,7 @@ int get_turbo_state(void)
turbo_state = TURBO_ENABLED;
}
+ set_global_turbo_state(turbo_state);
printk(BIOS_INFO, "Turbo is %s\n", turbo_state_desc[turbo_state]);
return turbo_state;
}
@@ -84,7 +107,7 @@ void enable_turbo(void)
wrmsr(MSR_IA32_MISC_ENABLES, msr);
/* Update cached turbo state */
- turbo_state = TURBO_ENABLED;
+ set_global_turbo_state(TURBO_ENABLED);
printk(BIOS_INFO, "Turbo has been enabled\n");
}
}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4895
-gerrit
commit 2de2c1d4142d71c23380fb6ed080aac68d303536
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 24 08:55:51 2013 -0500
x86: add HAVE_REFCODE_BLOB option
In order to incorporate external blobs into
CBFS besides MRC have a notion of a reference code
blob. By selecting HAVE_REFCODE_BLOB and providing
the file name the refcode blob will be added to
cbfs as a stage file.
BUG=chrome-os-partner:22866
BRANCH=None
TEST=Using this option and other patches able to build,
boot, and run blob code.
Change-Id: I472604d77f4cb48f286b5a76b25d8b5bfb0c7780
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174423
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/Kconfig | 17 +++++++++++++++++
src/arch/x86/Makefile.inc | 3 +++
2 files changed, 20 insertions(+)
diff --git a/src/Kconfig b/src/Kconfig
index 0af108f..614b95f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -429,6 +429,23 @@ config RELOCATABLE_RAMSTAGE
wake. When selecting this option the romstage is responsible for
determing a stack location to use for loading the ramstage.
+config HAVE_REFCODE_BLOB
+ depends on ARCH_X86
+ bool "An external reference code blob should be put into cbfs."
+ default n
+ help
+ The reference code blob will be placed into cbfs.
+
+if HAVE_REFCODE_BLOB
+
+config REFCODE_BLOB_FILE
+ string "Path and filename to reference code blob."
+ default "refcode.elf"
+ help
+ The path and filename to the file to be added to cbfs.
+
+endif # HAVE_REFCODE_BLOB
+
config HAVE_ACPI_TABLES
bool
help
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 2ade820..80e731f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -136,6 +136,9 @@ endif
ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y)
$(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB_ELF) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG)
endif
+ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y)
+ $(CBFSTOOL) $@.tmp add-stage -f $(CONFIG_REFCODE_BLOB_FILE) -n $(CONFIG_CBFS_PREFIX)/refcode -c $(CBFS_COMPRESS_FLAG)
+endif
ifeq ($(CONFIG_PXE_ROM),y)
$(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw
endif
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5022
-gerrit
commit ccda0d147f24bcf4ce2817b7252b9bef28824fb2
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Dec 13 13:02:46 2013 -0800
chromeos: add VBOOT_REFCODE_INDEX option
Certain platforms need to have reference code
packaged and verified through vboot. Therefore,
add this option.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built.
Change-Id: Iea4b96bcf334289edbc872a253614bb1bebe196a
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180025
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/vendorcode/google/chromeos/Kconfig | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index a564608..2f17b7e 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -110,6 +110,14 @@ config VBOOT_RAMSTAGE_INDEX
This is the index of the ramstage component in the verified
firmware block.
+config VBOOT_REFCODE_INDEX
+ hex "Reference code firmware index"
+ default 1
+ depends on VBOOT_VERIFY_FIRMWARE
+ help
+ This is the index of the reference code component in the verified
+ firmware block.
+
config NO_TPM_RESUME
bool
default n
the following patch was just integrated into master:
commit 14161a2b7f1194c49ba1b0b0d4fc4473d549eeb7
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 24 10:11:08 2013 -0500
cbmem: add reference code ids
In order to identify the ram used in cbmem for
reference code blobs add common ids to be consumed
by downstream users.
BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted with ref code support. Noted reference
code entries in cbmem.
Change-Id: Iae3f0c2c1ffdb2eb0e82a52ee459d25db44c1904
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174424
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See http://review.coreboot.org/4896 for details.
-gerrit
the following patch was just integrated into master:
commit 47c1725d496c0245abd6534e3d3395bfadc348f9
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 27 16:39:17 2014 -0600
x86/mtrr: don't assume size of ROM cached during CAR mode
Romstage and ramstage can use 2 different values for the
amount of ROM to cache just under 4GiB in the address
space. Don't assume a cpu's romstage caching policy
for the ROM.
Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/4846 for details.
-gerrit
the following patch was just integrated into master:
commit 5f748a2b8fc4c70f7078aa8b1ccc39edf37075f5
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 27 15:52:47 2014 -0600
intel: fix microcode compilation failure in bootblock
When not building with CONFIG_SSE there are not enough
registers for ROMCC to use for spilling. The previous
changes to this file had too many local variables that
needed to be tracked -- thus causing romcc compilation
issues.
Change-Id: I3dd4b48be707f41ce273285e98ebd397c32a6a25
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/4845 for details.
-gerrit