Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5079
-gerrit
commit 1d10759b11a317c8991ba81275988826ae0c18ee
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Wed Jan 29 15:29:44 2014 +1100
mainboard/jetway/nf81-t56n-lf: Serialize ACPI methods to avoid races.
Fix the remark introduced in ACPICA version 20130517 that gives the
following explanation:
If a thread blocks within the method for any reason, and another thread
enters the method, the method will fail because an attempt will be
made to create the same (named) object twice.
In this case, issue a remark that the method should be marked
serialized. ACPICA BZ 909.
Change-Id: I2b3605a31a8647c07be0830e54cd117d53985c81
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
index b3aed9c..4071f85 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
@@ -77,7 +77,7 @@ Method(GTTM, 1) /* get total time*/
Device(PRID)
{
Name (_ADR, Zero)
- Method(_GTM, 0)
+ Method(_GTM, 0, Serialized)
{
NAME(OTBF, Buffer(20) { /* out buffer */
0xFF, 0xFF, 0xFF, 0xFF,
@@ -122,7 +122,7 @@ Device(PRID)
Return(OTBF) /* out buffer */
} /* End Method(_GTM) */
- Method(_STM, 3, NotSerialized)
+ Method(_STM, 3, Serialized)
{
NAME(INBF, Buffer(20) { /* in buffer */
0xFF, 0xFF, 0xFF, 0xFF,
@@ -173,7 +173,7 @@ Device(PRID)
Device(MST)
{
Name(_ADR, 0)
- Method(_GTF) {
+ Method(_GTF, 0, Serialized) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
@@ -209,7 +209,7 @@ Device(PRID)
Device(SLAV)
{
Name(_ADR, 1)
- Method(_GTF) {
+ Method(_GTF, 0, Serialized) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5079
-gerrit
commit e227ae6f9321796623f7bce0a3914794348d18d7
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Wed Jan 29 15:29:44 2014 +1100
mainboard/jetway/nf81-t56n-lf: Serialize ACPI method remarks to avoid races.
Fix the remark introduced in ACPICA version 20130517 that gives the
following explanation:
If a thread blocks within the method for any reason, and another thread
enters the method, the method will fail because an attempt will be
made to create the same (named) object twice.
In this case, issue a remark that the method should be marked
serialized. ACPICA BZ 909.
The toolchain remarks fixed by this are as follows:
Intel ACPI Component Architecture
ASL Optimizing Compiler version 20130626-64 [Jan 26 2014]
Copyright (c) 2000 - 2013 Intel Corporation
dsdt.ramstage.asl 1034: Method(_GTM, 0)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.ramstage.asl 1069: Method(_STM, 3, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.ramstage.asl 1114: Method(_GTF) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.ramstage.asl 1146: Method(_GTF) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
ASL Input: dsdt.ramstage.asl - 1732 lines, 33264 bytes, 941 keywords
AML Output: dsdt.ramstage.aml - 10152 bytes, 406 named objects, 535 executable opcodes
Hex Dump: dsdt.ramstage.hex - 95502 bytes
Change-Id: I2b3605a31a8647c07be0830e54cd117d53985c81
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
index b3aed9c..4071f85 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
@@ -77,7 +77,7 @@ Method(GTTM, 1) /* get total time*/
Device(PRID)
{
Name (_ADR, Zero)
- Method(_GTM, 0)
+ Method(_GTM, 0, Serialized)
{
NAME(OTBF, Buffer(20) { /* out buffer */
0xFF, 0xFF, 0xFF, 0xFF,
@@ -122,7 +122,7 @@ Device(PRID)
Return(OTBF) /* out buffer */
} /* End Method(_GTM) */
- Method(_STM, 3, NotSerialized)
+ Method(_STM, 3, Serialized)
{
NAME(INBF, Buffer(20) { /* in buffer */
0xFF, 0xFF, 0xFF, 0xFF,
@@ -173,7 +173,7 @@ Device(PRID)
Device(MST)
{
Name(_ADR, 0)
- Method(_GTF) {
+ Method(_GTF, 0, Serialized) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
@@ -209,7 +209,7 @@ Device(PRID)
Device(SLAV)
{
Name(_ADR, 1)
- Method(_GTF) {
+ Method(_GTF, 0, Serialized) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4801
-gerrit
commit a419ff66aacf6d6779fd44bfea43dcf8a8af9811
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sat Jan 25 21:46:10 2014 +1100
Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
Step 2: change the Persimmon code to adapt it to the new board's hardware.
The NF81-T56N-LF is a IPC form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) APU
- 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (1.5 or 1.35V)?
- VGA and LVDS (via Analogix ANX3110)
- AMD A55E (Hudson-E1) southbridge
- 6x USB 2.0/1.1 ports
- 5x SATA3 6Gb/s, 1x mSATA socket
- 6-Channel HD Audio (via VIA VT1705)
- PCI and ISA (via ITE IT8888)??
- NEC uPD78F0532 microcontroller on I2C ("SEMA")??
- 2x RJ45 GbE (via Realtek RTL8111E x2)
- Fintek F71869AD Super I/O
- PS/2 KB/MS port
- RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
- GPIO header
- CIR header
- 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)
Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies*
claiming the SPI flash is 16MB. They also use red pen over the chip
so you wont see this deceit.
Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/Kconfig | 3 ++
src/mainboard/jetway/nf81-t56n-lf/Kconfig | 18 ++++---
src/mainboard/jetway/nf81-t56n-lf/board_info.txt | 5 +-
src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 62 ++++++++++++++++--------
src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 3 ++
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 7 +--
6 files changed, 65 insertions(+), 33 deletions(-)
diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig
index 7e6e29d..5b55daa 100644
--- a/src/mainboard/jetway/Kconfig
+++ b/src/mainboard/jetway/Kconfig
@@ -11,6 +11,8 @@ config BOARD_JETWAY_J7F4K1G5D
bool "J7F4K1G5D"
config BOARD_JETWAY_PA78VM5
bool "PA78VM5 (Fam10)"
+config BOARD_JETWAY_NF81_T56N_LF
+ bool "NF81_T56N_LF"
endchoice
@@ -18,6 +20,7 @@ source "src/mainboard/jetway/j7f2/Kconfig"
source "src/mainboard/jetway/j7f4k1g2e/Kconfig"
source "src/mainboard/jetway/j7f4k1g5d/Kconfig"
source "src/mainboard/jetway/pa78vm5/Kconfig"
+source "src/mainboard/jetway/nf81-t56n-lf/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index febd8dd..d602ffa 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -17,7 +18,7 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-if BOARD_AMD_PERSIMMON
+if BOARD_JETWAY_NF81_T56N_LF
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -25,22 +26,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
- select SUPERIO_FINTEK_F81865F
+ select SUPERIO_FINTEK_F71869AD
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select HAVE_ACPI_RESUME
+# FIXME: Disable S3 for now. Enable by default once stabilised.
+# select HAVE_ACPI_RESUME
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_4096
+ select BOARD_ROMSIZE_KB_2048
select GFXUMA
config MAINBOARD_DIR
string
- default amd/persimmon
+ default jetway/nf81-t56n-lf
config APIC_ID_OFFSET
hex
@@ -48,7 +50,7 @@ config APIC_ID_OFFSET
config MAINBOARD_PART_NUMBER
string
- default "Persimmon"
+ default "NF81-T56N-LF"
config HW_MEM_HOLE_SIZEK
hex
@@ -101,7 +103,7 @@ config VGA_BIOS
config VGA_BIOS_ID
string
- default "1002,9802"
+ default "1002,9806" # FUSION_G_T56N
config SB800_AHCI_ROM
bool
@@ -111,4 +113,4 @@ config DRIVERS_PS2_KEYBOARD
bool
default n
-endif # BOARD_AMD_PERSIMMON
+endif # BOARD_JETWAY_NF81_T56N_LF
diff --git a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
index 85cb19a..6748751 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
+++ b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
@@ -1,5 +1,6 @@
-Board name: DBFT1-00-EVAL-KT (Persimmon)
-Category: eval
+Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T5…
+Category: Mini-ITX
+ROM package: SOIC8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 8b1acd5..3624744 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -29,7 +30,8 @@ chip northbridge/amd/agesa/family14/root_complex
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
- device pci 4.0 on end # PCIE P2P bridge on-board NIC
+# device pci 1.1 on end # Internal Audio P2P bridge 0x1314
+ device pci 4.0 off end # PCIE P2P bridge on-board NIC
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge PCIe slot
device pci 7.0 off end # PCIE P2P bridge
@@ -50,43 +52,58 @@ chip northbridge/amd/agesa/family14/root_complex
device i2c 51 on end
end
end # SM
- device pci 14.1 on end # IDE 0x439c
+ device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
- chip superio/fintek/f81865f
- device pnp 4e.0 off # Floppy
+ chip superio/fintek/f71869ad
+# XXX: 4e is the default index port and .xy is the
+# LDN indexing the pnp_info array found in the superio.c
+ device pnp 4e.00 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
- device pnp 4e.3 off end # Parallel Port
- device pnp 4e.4 off end # Hardware Monitor
- device pnp 4e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 4e.6 off end # GPIO
- device pnp 4e.a off end # PME
- device pnp 4e.10 on # COM1
+ device pnp 4e.01 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 4e.11 on # COM2
+ device pnp 4e.02 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
- end # f81865f
+ device pnp 4e.03 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 4e.04 on # Hardware Monitor
+ io 0x60 = 0x295
+ irq 0x70 = 0
+ end
+ device pnp 4e.05 on # KBC
+ io 0x60 = 0x060
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x70 = 12 # Mouse IRQ
+ end
+ device pnp 4e.06 off end # GPIO
+# TODO: Verify BSEL register content with vendor BIOS using
+# $ sudo isadump 0x4e 0x4f 0x7
+# which select logical device (LDN) 7. Then read that we have in 0x27, bit1
+ device pnp 4e.07 on # BSEL
+ io 0x60 = 0x000
+ end
+ device pnp 4e.0a on end # PME
+ end # f71869ad
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
- device pci 14.5 off end # OHCI FS/LS USB
+ device pci 14.5 on end # OHCI FS/LS USB (0x4399)
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
- device pci 15.0 off end # PCIe PortA
+ device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
- device pci 16.0 off end # OHCI USB 10-13
- device pci 16.2 off end # EHCI USB 10-13
+ device pci 16.0 on end # OHCI USB 10-13 (0x4397)
+ device pci 16.2 on end # EHCI USB 10-13 (0x4396)
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
@@ -150,6 +167,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.6 on end
device pci 18.7 on end
+#
+# TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
+# with i2cdump tool.
+# Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
+#
register "spdAddrLookup" = "
{
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
index f084b2f..ce08bee 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -211,6 +212,7 @@
*/
#define GEC_CONFIG 0
+/* FIXME: Verify this for sound to work! */
static const CODECENTRY persimmon_codec_alc269[] =
{
/* NID, PinConfig */
@@ -228,6 +230,7 @@ static const CODECENTRY persimmon_codec_alc269[] =
{0xff, 0xffffffff} /* end of table */
};
+/* FIXME: Verify this for sound to work! */
static const CODECTBLLIST codec_tablelist[] =
{
{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 98c64ed..f8271f7 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,7 +32,7 @@
#include <cpu/x86/mtrr.h>
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include "superio/fintek/f71869ad/f71869ad.h"
#include "cpu/x86/lapic.h"
#include "drivers/pc80/i8254.c"
#include "drivers/pc80/i8259.c"
@@ -45,7 +46,7 @@
void disable_cache_as_ram(void); /* cache_as_ram.inc */
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
+#define SERIAL_DEV PNP_DEV(0x4e, F71869AD_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -70,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init();
post_code(0x31);
- f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5079
-gerrit
commit a17f077d881c1c7d1f90ef3778dcf1dad643a09a
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Wed Jan 29 15:29:44 2014 +1100
mainboard/jetway/nf81-t56n-lf: Serialize ACPI method remarks to avoid races.
Fix the remark introduced in ACPICA version 20130517 that gives the
following explanation:
If a thread blocks within the method for any reason, and another thread
enters the method, the method will fail because an attempt will be
made to create the same (named) object twice.
In this case, issue a remark that the method should be marked
serialized. ACPICA BZ 909.
The toolchain remarks fixed by this are as follows:
Intel ACPI Component Architecture
ASL Optimizing Compiler version 20130626-64 [Jan 26 2014]
Copyright (c) 2000 - 2013 Intel Corporation
dsdt.ramstage.asl 1034: Method(_GTM, 0)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.ramstage.asl 1069: Method(_STM, 3, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.ramstage.asl 1114: Method(_GTF) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.ramstage.asl 1146: Method(_GTF) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
ASL Input: dsdt.ramstage.asl - 1732 lines, 33264 bytes, 941 keywords
AML Output: dsdt.ramstage.aml - 10152 bytes, 406 named objects, 535 executable opcodes
Hex Dump: dsdt.ramstage.hex - 95502 bytes
Change-Id: I2b3605a31a8647c07be0830e54cd117d53985c81
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
index b3aed9c..4071f85 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
@@ -77,7 +77,7 @@ Method(GTTM, 1) /* get total time*/
Device(PRID)
{
Name (_ADR, Zero)
- Method(_GTM, 0)
+ Method(_GTM, 0, Serialized)
{
NAME(OTBF, Buffer(20) { /* out buffer */
0xFF, 0xFF, 0xFF, 0xFF,
@@ -122,7 +122,7 @@ Device(PRID)
Return(OTBF) /* out buffer */
} /* End Method(_GTM) */
- Method(_STM, 3, NotSerialized)
+ Method(_STM, 3, Serialized)
{
NAME(INBF, Buffer(20) { /* in buffer */
0xFF, 0xFF, 0xFF, 0xFF,
@@ -173,7 +173,7 @@ Device(PRID)
Device(MST)
{
Name(_ADR, 0)
- Method(_GTF) {
+ Method(_GTF, 0, Serialized) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
@@ -209,7 +209,7 @@ Device(PRID)
Device(SLAV)
{
Name(_ADR, 1)
- Method(_GTF) {
+ Method(_GTF, 0, Serialized) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4817
-gerrit
commit 88d5fb9060920e9b28bd373b204e0f2a38b96918
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Tue Dec 3 11:13:35 2013 -0800
cbfs: fix issues with word size and endianness.
Add XDR functions and use them to convert the ELF headers
to native headers, using the Elf64 structs to ensure we accomodate
all word sizes. Also, use these XDR functions for output.
This may seem overly complex but it turned out to be much the easiest
way to do this. Note that the basic elf parsing function
in cbfs-mkstage.c now works over all ELF files, for all architectures,
endian, and word size combinations. At the same time, the basic elf
parsing in cbfs-mkstage.c is a loop that has no architecture-specific
conditionals.
Add -g to the LDFLAGS while we're here. It's on the CFLAGS so there is
no harm done.
This code has been tested on all chromebooks that use coreboot to date.
I added most of the extra checks from ChromeOS and they triggered a
lot of warnings, hence the other changes. I had to take -Wshadow back
out due to the many errors it triggers in LZMA.
BUG=None
TEST=Build and boot for Peppy; works fine. Build and boot for nyan,
works fine. Build for qemu targets and armv8 targets.
BRANCH=None
Change-Id: I5a4cee9854799189115ac701e22efc406a8d902f
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/178606
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Ronald Minnich <rminnich(a)chromium.org>
---
util/cbfstool/Makefile | 14 +-
util/cbfstool/Makefile.inc | 1 +
util/cbfstool/cbfs-mkstage.c | 347 +++++++++++++++++++++++++++++++++++--------
util/cbfstool/cbfs_image.c | 26 +---
util/cbfstool/common.c | 51 ++++---
util/cbfstool/common.h | 32 +++-
util/cbfstool/compress.c | 2 -
util/cbfstool/fit.c | 8 +-
util/cbfstool/xdr.c | 140 +++++++++++++++++
9 files changed, 505 insertions(+), 116 deletions(-)
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 3aa5edc..5e4fdcb 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -1,13 +1,19 @@
obj ?= $(shell pwd)
-HOSTCC ?= gcc
-CFLAGS ?= -g -Wall -Werror
-CFLAGS += -D_7ZIP_ST
+HOSTCC ?= gcc
+CFLAGS ?= -g
+CFLAGS += -D_7ZIP_ST
+CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
+CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
+CFLAGS += -Wstrict-aliasing -Werror
+# You're going to have to fix the LzmaEnc.c first -- it's horrible.
+# CFLAGS += -Wshadow
+LDFLAGS += -g
BINARY:=$(obj)/cbfstool
COMMON:=cbfstool.o common.o cbfs_image.o compress.o fit.o
-COMMON+=cbfs-mkstage.o cbfs-mkpayload.o
+COMMON+=cbfs-mkstage.o cbfs-mkpayload.o xdr.o
# LZMA
COMMON+=lzma/lzma.o
COMMON+=lzma/C/LzFind.o lzma/C/LzmaDec.o lzma/C/LzmaEnc.o
diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc
index fc120f3..4270d75 100644
--- a/util/cbfstool/Makefile.inc
+++ b/util/cbfstool/Makefile.inc
@@ -5,6 +5,7 @@ cbfsobj += compress.o
cbfsobj += cbfs_image.o
cbfsobj += cbfs-mkstage.o
cbfsobj += cbfs-mkpayload.o
+cbfsobj += xdr.o
cbfsobj += fit.o
# LZMA
cbfsobj += lzma.o
diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c
index dfc93c2..5c8014f 100644
--- a/util/cbfstool/cbfs-mkstage.c
+++ b/util/cbfstool/cbfs-mkstage.c
@@ -28,46 +28,204 @@
#include "cbfs.h"
#include "elf.h"
-static unsigned int idemp(unsigned int x)
-{
- return x;
-}
+/*
+ * Short form: this is complicated, but we've tried making it simple
+ * and we keep hitting problems with our ELF parsing.
+ *
+ * The ELF parsing situation has always been a bit tricky. In fact,
+ * we (and most others) have been getting it wrong in small ways for
+ * years. Recently this has caused real trouble for the ARM V8 build.
+ * In this file we attempt to finally get it right for all variations
+ * of endian-ness and word size and target architectures and
+ * architectures we might get run on. Phew!. To do this we borrow a
+ * page from the FreeBSD NFS xdr model (see elf_ehdr and elf_phdr),
+ * the Plan 9 endianness functions (see xdr.c), and Go interfaces (see
+ * how we use buffer structs in this file). This ends up being a bit
+ * wordy at the lowest level, but greatly simplifies the elf parsing
+ * code and removes a common source of bugs, namely, forgetting to
+ * flip type endianness when referencing a struct member.
+ *
+ * ELF files can have four combinations of data layout: 32/64, and
+ * big/little endian. Further, to add to the fun, depending on the
+ * word size, the size of the ELF structs varies. The coreboot SELF
+ * format is simpler in theory: it's supposed to be always BE, and the
+ * various struct members allow room for growth: the entry point is
+ * always 64 bits, for example, so the size of a SELF struct is
+ * constant, regardless of target architecture word size. Hence, we
+ * need to do some transformation of the ELF files.
+ *
+ * A given architecture, realistically, only supports one of the four
+ * combinations at a time as the 'native' format. Hence, our code has
+ * been sprinkled with every variation of [nh]to[hn][sll] over the
+ * years. We've never quite gotten it all right, however, and a quick
+ * pass over this code revealed another bug. It's all worked because,
+ * until now, all the working platforms that had CBFS were 32 LE. Even then,
+ * however, bugs crept in: we recently realized that we're not
+ * transforming the entry point to big format when we store into the
+ * SELF image.
+ *
+ * The problem is essentially an XDR operation:
+ * we have something in a foreign format and need to transform it.
+ * It's most like XDR because:
+ * 1) the byte order can be wrong
+ * 2) the word size can be wrong
+ * 3) the size of elements in the stream depends on the value
+ * of other elements in the stream
+ * it's not like XDR because:
+ * 1) the byte order can be right
+ * 2) the word size can be right
+ * 3) the struct members are all on a natural alignment
+ *
+ * Hence, this new approach. To cover word size issues, we *always*
+ * transform the two structs we care about, the file header and
+ * program header, into a native struct in the 64 bit format:
+ *
+ * [32,little] -> [Elf64_Ehdr, Elf64_Phdr]
+ * [64,little] -> [Elf64_Ehdr, Elf64_Phdr]
+ * [32,big] -> [Elf64_Ehdr, Elf64_Phdr]
+ * [64,big] -> [Elf64_Ehdr, Elf64_Phdr]
+ * Then we just use those structs, and all the need for inline ntoh* goes away,
+ * as well as all the chances for error.
+ * This works because all the SELF structs have fields large enough for
+ * the largest ELF 64 struct members, and all the Elf64 struct members
+ * are at least large enough for all ELF 32 struct members.
+ * We end up with one function to do all our ELF parsing, and two functions
+ * to transform the headers. For the put case, we also have
+ * XDR functions, and hopefully we'll never again spend 5 years with the
+ * wrong endian-ness on an output value :-)
+ * This should work for all word sizes and endianness we hope to target.
+ * I *really* don't want to be here for 128 bit addresses.
+ *
+ * The parse functions are called with a pointer to an input buffer
+ * struct. One might ask: are there enough bytes in the input buffer?
+ * We know there need to be at *least* sizeof(Elf32_Ehdr) +
+ * sizeof(Elf32_Phdr) bytes. Realistically, there has to be some data
+ * too. If we start to worry, though we have not in the past, we
+ * might apply the simple test: the input buffer needs to be at least
+ * sizeof(Elf64_Ehdr) + sizeof(Elf64_Phdr) bytes because, even if it's
+ * ELF 32, there's got to be *some* data! This is not theoretically
+ * accurate but it is actually good enough in practice. It allows the
+ * header transformation code to ignore the possibility of underrun.
+ *
+ * We also must accomodate different ELF files, and hence formats,
+ * in the same cbfs invocation. We might load a 64-bit payload
+ * on a 32-bit machine; we might even have a mixed armv7/armv8
+ * SOC or even a system with an x86/ARM!
+ *
+ * A possibly problematic (though unlikely to be so) assumption
+ * is that we expect the BIOS to remain in the lowest 32 bits
+ * of the physical address space. Since ARMV8 has standardized
+ * on that, and x86_64 also has, this seems a safe assumption.
+ *
+ * To repeat, ELF structs are different sizes because ELF struct
+ * members are different sizes, depending on values in the ELF file
+ * header. For this we use the functions defined in xdr.c, which
+ * consume bytes, convert the endianness, and advance the data pointer
+ * in the buffer struct.
+ */
-/* This is a wrapper around the swab32() macro to make it
- * usable for the current implementation of parse_elf_to_stage()
+/* Get the ident array, so we can figure out
+ * endian-ness, word size, and in future other useful
+ * parameters
*/
-static unsigned int swap32(unsigned int x)
+static void
+elf_eident(struct buffer *input, Elf64_Ehdr *ehdr)
{
- return swab32(x);
+ memmove(ehdr->e_ident, input->data, sizeof(ehdr->e_ident));
+ input->data += sizeof(ehdr->e_ident);
+ input->size -= sizeof(ehdr->e_ident);
}
-unsigned int (*elf32_to_native) (unsigned int) = idemp;
-/* returns size of result, or -1 if error */
-int parse_elf_to_stage(const struct buffer *input, struct buffer *output,
- comp_algo algo, uint32_t *location)
+static void
+elf_ehdr(struct buffer *input, Elf64_Ehdr *ehdr, struct xdr *xdr, int bit64)
{
- Elf32_Phdr *phdr;
- Elf32_Ehdr *ehdr = (Elf32_Ehdr *)input->data;
- char *header, *buffer;
-
- int headers;
- int i;
- struct cbfs_stage *stage;
- unsigned int data_start, data_end, mem_end;
+ ehdr->e_type = xdr->get16(input);
+ ehdr->e_machine = xdr->get16(input);
+ ehdr->e_version = xdr->get32(input);
+ if (bit64){
+ ehdr->e_entry = xdr->get64(input);
+ ehdr->e_phoff = xdr->get64(input);
+ ehdr->e_shoff = xdr->get64(input);
+ } else {
+ ehdr->e_entry = xdr->get32(input);
+ ehdr->e_phoff = xdr->get32(input);
+ ehdr->e_shoff = xdr->get32(input);
+ }
+ ehdr->e_flags = xdr->get32(input);
+ ehdr->e_ehsize = xdr->get16(input);
+ ehdr->e_phentsize = xdr->get16(input);
+ ehdr->e_phnum = xdr->get16(input);
+ ehdr->e_shentsize = xdr->get16(input);
+ ehdr->e_shnum = xdr->get16(input);
+ ehdr->e_shstrndx = xdr->get16(input);
+}
- int elf_bigendian = 0;
+static void
+elf_phdr(struct buffer *pinput, Elf64_Phdr *phdr,
+ int entsize, struct xdr *xdr, int bit64)
+{
+ /*
+ * The entsize need not be sizeof(*phdr).
+ * Hence, it is easier to keep a copy of the input,
+ * as the xdr functions may not advance the input
+ * pointer the full entsize; rather than get tricky
+ * we just advance it below.
+ */
+ struct buffer input = *pinput;
+ if (bit64){
+ phdr->p_type = xdr->get32(&input);
+ phdr->p_flags = xdr->get32(&input);
+ phdr->p_offset = xdr->get64(&input);
+ phdr->p_vaddr = xdr->get64(&input);
+ phdr->p_paddr = xdr->get64(&input);
+ phdr->p_filesz = xdr->get64(&input);
+ phdr->p_memsz = xdr->get64(&input);
+ phdr->p_align = xdr->get64(&input);
+ } else {
+ phdr->p_type = xdr->get32(&input);
+ phdr->p_offset = xdr->get32(&input);
+ phdr->p_vaddr = xdr->get32(&input);
+ phdr->p_paddr = xdr->get32(&input);
+ phdr->p_filesz = xdr->get32(&input);
+ phdr->p_memsz = xdr->get32(&input);
+ phdr->p_flags = xdr->get32(&input);
+ phdr->p_align = xdr->get32(&input);
+ }
+ pinput->size -= entsize;
+ pinput->data += entsize;
+}
- comp_func_ptr compress = compression_function(algo);
- if (!compress)
- return -1;
+/* Get the headers from the buffer.
+ * Return -1 in the event of an error.
+ */
+static int
+elf_headers(const struct buffer *pinput, Elf64_Ehdr *ehdr, Elf64_Phdr **pphdr)
+{
+ int i;
+ struct xdr *xdr = &xdr_le;
+ int bit64 = 0;
+ struct buffer input = *(struct buffer *)pinput;
+ struct buffer phdr_buf;
+ Elf64_Phdr *phdr;
- DEBUG("start: parse_elf_to_stage(location=0x%x)\n", *location);
- if (!iself((unsigned char *)input->data)) {
+ if (!iself((unsigned char *)pinput->data)) {
ERROR("The stage file is not in ELF format!\n");
return -1;
}
+ elf_eident(&input, ehdr);
+ bit64 = ehdr->e_ident[EI_CLASS] == ELFCLASS64;
+ /* Assume LE unless we are sure otherwise.
+ * We're not going to take on the task of
+ * fully validating the ELF file. That way
+ * lies madness.
+ */
+ if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
+ xdr = &xdr_be;
+
+ elf_ehdr(&input, ehdr, xdr, bit64);
+
// The tool may work in architecture-independent way.
if (arch != CBFS_ARCHITECTURE_UNKNOWN &&
!((ehdr->e_machine == EM_ARM) && (arch == CBFS_ARCHITECTURE_ARMV7)) &&
@@ -76,42 +234,84 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output,
return -1;
}
- if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB) {
- elf_bigendian = 1;
+ if (pinput->size < ehdr->e_phoff){
+ ERROR("The program header offset is greater than "
+ "the remaining file size."
+ "%ld bytes left, program header offset is %ld \n",
+ pinput->size, ehdr->e_phoff);
+ return -1;
}
- if (elf_bigendian != is_big_endian()) {
- elf32_to_native = swap32;
+ /* cons up an input buffer for the headers.
+ * Note that the program headers can be anywhere,
+ * per the ELF spec, You'd be surprised how many ELF
+ * readers miss this little detail.
+ */
+ phdr_buf.data = &pinput->data[ehdr->e_phoff];
+ phdr_buf.size = ehdr->e_phentsize * ehdr->e_phnum;
+ if (phdr_buf.size > (pinput->size - ehdr->e_phoff)){
+ ERROR("The file is not large enough for the program headers."
+ "%ld bytes left, %ld bytes of headers\n",
+ pinput->size - ehdr->e_phoff, phdr_buf.size);
+ return -1;
}
+ /* gather up all the phdrs.
+ * We do them all at once because there is more
+ * than one loop over all the phdrs.
+ */
+ phdr = calloc(sizeof(*phdr), ehdr->e_phnum);
+ for (i = 0; i < ehdr->e_phnum; i++)
+ elf_phdr(&phdr_buf, &phdr[i], ehdr->e_phentsize, xdr, bit64);
+ *pphdr = phdr;
+ return 0;
+}
- headers = ehdr->e_phnum;
- header = (char *)ehdr;
+/* returns size of result, or -1 if error.
+ * Note that, with the new code, this function
+ * works for all elf files, not just the restricted set.
+ */
+int parse_elf_to_stage(const struct buffer *input, struct buffer *output,
+ comp_algo algo, uint32_t *location)
+{
+ Elf64_Phdr *phdr;
+ Elf64_Ehdr ehdr;
+ char *buffer;
+ struct buffer outheader;
- phdr = (Elf32_Phdr *) & header[elf32_to_native(ehdr->e_phoff)];
+ int headers;
+ int i, outlen;
+ uint32_t data_start, data_end, mem_end;
- /* Now, regular headers - we only care about PT_LOAD headers,
- * because thats what we're actually going to load
- */
+ comp_func_ptr compress = compression_function(algo);
+ if (!compress)
+ return -1;
+
+ DEBUG("start: parse_elf_to_stage(location=0x%x)\n", *location);
+
+ if (elf_headers(input, &ehdr, &phdr) < 0)
+ return -1;
+
+ headers = ehdr.e_phnum;
- data_start = 0xFFFFFFFF;
+ data_start = ~0;
data_end = 0;
mem_end = 0;
for (i = 0; i < headers; i++) {
unsigned int start, mend, rend;
- if (elf32_to_native(phdr[i].p_type) != PT_LOAD)
+ if (phdr[i].p_type != PT_LOAD)
continue;
/* Empty segments are never interesting */
- if (elf32_to_native(phdr[i].p_memsz) == 0)
+ if (phdr[i].p_memsz == 0)
continue;
/* BSS */
- start = elf32_to_native(phdr[i].p_paddr);
+ start = phdr[i].p_paddr;
- mend = start + elf32_to_native(phdr[i].p_memsz);
- rend = start + elf32_to_native(phdr[i].p_filesz);
+ mend = start + phdr[i].p_memsz;
+ rend = start + phdr[i].p_filesz;
if (start < data_start)
data_start = start;
@@ -128,8 +328,9 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output,
}
if (data_end <= data_start) {
- ERROR("data ends before it starts. Make sure the "
- "ELF file is correct and resides in ROM space.\n");
+ ERROR("data ends (%08lx) before it starts (%08lx). Make sure "
+ "the ELF file is correct and resides in ROM space.\n",
+ (unsigned long)data_end, (unsigned long)data_start);
exit(1);
}
@@ -146,25 +347,39 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output,
for (i = 0; i < headers; i++) {
unsigned int l_start, l_offset = 0;
- if (elf32_to_native(phdr[i].p_type) != PT_LOAD)
+ if (phdr[i].p_type != PT_LOAD)
continue;
- if (elf32_to_native(phdr[i].p_memsz) == 0)
+ if (phdr[i].p_memsz == 0)
continue;
- l_start = elf32_to_native(phdr[i].p_paddr);
+ l_start = phdr[i].p_paddr;
if (l_start < *location) {
l_offset = *location - l_start;
l_start = *location;
}
+ /* A legal ELF file can have a program header with
+ * non-zero length but zero-length file size and a
+ * non-zero offset which, added together, are > than
+ * input->size (i.e. the total file size). So we need
+ * to not even test in the case that p_filesz is zero.
+ */
+ if (! phdr[i].p_filesz)
+ continue;
+ if (input->size < (phdr[i].p_offset + phdr[i].p_filesz)){
+ ERROR("Underflow copying out the segment."
+ "File has %ld bytes left, segment end is %ld\n",
+ input->size, phdr[i].p_offset + phdr[i].p_filesz);
+ return -1;
+ }
memcpy(buffer + (l_start - data_start),
- &header[elf32_to_native(phdr[i].p_offset)+l_offset],
- elf32_to_native(phdr[i].p_filesz)-l_offset);
+ &input->data[phdr[i].p_offset + l_offset],
+ phdr[i].p_filesz - l_offset);
}
/* Now make the output buffer */
- if (buffer_create(output, sizeof(*stage) + data_end - data_start,
+ if (buffer_create(output, sizeof(struct cbfs_stage) + data_end - data_start,
input->name) != 0) {
ERROR("Unable to allocate memory: %m\n");
free(buffer);
@@ -172,19 +387,31 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output,
}
memset(output->data, 0, output->size);
- stage = (struct cbfs_stage *)output->data;
-
- stage->load = data_start; /* FIXME: htonll */
- stage->memlen = mem_end - data_start;
- stage->compression = algo;
- stage->entry = ehdr->e_entry; /* FIXME: htonll */
-
- compress(buffer, data_end - data_start, (output->data + sizeof(*stage)),
- (int *)&stage->len);
+ /* Compress the data, at which point we'll know information
+ * to fill out the header. This seems backward but it works because
+ * - the output header is a known size (not always true in many xdr's)
+ * - we do need to know the compressed output size first
+ */
+ compress(buffer, data_end - data_start,
+ (output->data + sizeof(struct cbfs_stage)),
+ &outlen);
free(buffer);
+ /* Set up for output marshaling. */
+ outheader.data = output->data;
+ outheader.size = 0;
+ /* N.B. The original plan was that SELF data was B.E.
+ * but: this is all L.E.
+ * Maybe we should just change the spec.
+ */
+ xdr_le.put32(&outheader, algo);
+ xdr_le.put64(&outheader, ehdr.e_entry);
+ xdr_le.put64(&outheader, data_start);
+ xdr_le.put32(&outheader, outlen);
+ xdr_le.put32(&outheader, mem_end - data_start);
+
if (*location)
*location -= sizeof(struct cbfs_stage);
- output->size = sizeof(*stage) + stage->len;
+ output->size = sizeof(struct cbfs_stage) + outlen;
return 0;
}
diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c
index 401654e..2cd0c7a 100644
--- a/util/cbfstool/cbfs_image.c
+++ b/util/cbfstool/cbfs_image.c
@@ -69,7 +69,7 @@ static uint32_t align_up(uint32_t value, uint32_t align)
return value;
}
-uint32_t lookup_type_by_name(const struct typedesc_t *desc, const char *name,
+static uint32_t lookup_type_by_name(const struct typedesc_t *desc, const char *name,
uint32_t default_value)
{
int i;
@@ -79,7 +79,7 @@ uint32_t lookup_type_by_name(const struct typedesc_t *desc, const char *name,
return default_value;
}
-const char *lookup_name_by_type(const struct typedesc_t *desc, uint32_t type,
+static const char *lookup_name_by_type(const struct typedesc_t *desc, uint32_t type,
const char *default_value)
{
int i;
@@ -139,7 +139,7 @@ static int cbfs_fix_legacy_size(struct cbfs_image *image)
}
int cbfs_image_create(struct cbfs_image *image,
- uint32_t arch,
+ uint32_t myarch,
size_t size,
uint32_t align,
struct buffer *bootblock,
@@ -206,7 +206,7 @@ int cbfs_image_create(struct cbfs_image *image,
header->bootblocksize = htonl(bootblock->size);
header->align = htonl(align);
header->offset = htonl(entries_offset);
- header->architecture = htonl(arch);
+ header->architecture = htonl(myarch);
// Prepare entries
if (align_up(entries_offset, align) != entries_offset) {
@@ -356,10 +356,10 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer,
if (IS_TOP_ALIGNED_ADDRESS(content_offset)) {
// legacy cbfstool takes top-aligned address.
- uint32_t romsize = ntohl(image->header->romsize);
+ uint32_t theromsize = ntohl(image->header->romsize);
INFO("Converting top-aligned address 0x%x to offset: 0x%x\n",
- content_offset, content_offset + romsize);
- content_offset += romsize;
+ content_offset, content_offset + theromsize);
+ content_offset += theromsize;
}
// Merge empty entries.
@@ -488,7 +488,7 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name,
buffer.data = CBFS_SUBHEADER(entry);
buffer.size = ntohl(entry->len);
- buffer.name = "(cbfs_export_entry)";
+ buffer.name = (char *)"(cbfs_export_entry)";
if (buffer_write_file(&buffer, filename) != 0) {
ERROR("Failed to write %s into %s.\n",
entry_name, filename);
@@ -793,16 +793,6 @@ int cbfs_is_valid_entry(struct cbfs_image *image, struct cbfs_file *entry)
sizeof(entry->magic)) == 0);
}
-int cbfs_init_entry(struct cbfs_file *entry,
- struct buffer *buffer)
-{
- memset(entry, 0, sizeof(*entry));
- memcpy(entry->magic, CBFS_FILE_MAGIC, sizeof(entry->magic));
- entry->len = htonl(buffer->size);
- entry->offset = htonl(sizeof(*entry) + strlen(buffer->name) + 1);
- return 0;
-}
-
int cbfs_create_empty_entry(struct cbfs_image *image, struct cbfs_file *entry,
size_t len, const char *name)
{
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index 03345df..8f38a4a 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -144,10 +144,13 @@ void *loadfile(const char *filename, uint32_t * romsize_p, void *content,
return content;
}
-static struct cbfs_header *master_header;
+/* N.B.: there are declarations here that were shadowed in functions.
+ * Hence the rather clumsy cbfstool_ prefixes.
+ */
+static struct cbfs_header *cbfstool_master_header;
static uint32_t phys_start, phys_end, align;
uint32_t romsize;
-void *offset;
+void *cbfstool_offset;
uint32_t arch = CBFS_ARCHITECTURE_UNKNOWN;
static struct {
@@ -194,19 +197,19 @@ int find_master_header(void *romarea, size_t size)
{
size_t offset;
- if (master_header)
+ if (cbfstool_master_header)
return 0;
for (offset = 0; offset < size - sizeof(struct cbfs_header); offset++) {
struct cbfs_header *tmp = romarea + offset;
if (tmp->magic == ntohl(CBFS_HEADER_MAGIC)) {
- master_header = tmp;
+ cbfstool_master_header = tmp;
break;
}
}
- return master_header ? 0 : 1;
+ return cbfstool_master_header ? 0 : 1;
}
void recalculate_rom_geometry(void *romarea)
@@ -217,25 +220,25 @@ void recalculate_rom_geometry(void *romarea)
}
/* Update old headers */
- if (master_header->version == CBFS_HEADER_VERSION1 &&
- ntohl(master_header->architecture) == CBFS_ARCHITECTURE_UNKNOWN) {
+ if (cbfstool_master_header->version == CBFS_HEADER_VERSION1 &&
+ ntohl(cbfstool_master_header->architecture) == CBFS_ARCHITECTURE_UNKNOWN) {
DEBUG("Updating CBFS master header to version 2\n");
- master_header->architecture = htonl(CBFS_ARCHITECTURE_X86);
+ cbfstool_master_header->architecture = htonl(CBFS_ARCHITECTURE_X86);
}
- arch = ntohl(master_header->architecture);
+ arch = ntohl(cbfstool_master_header->architecture);
switch (arch) {
case CBFS_ARCHITECTURE_ARMV7:
- offset = romarea;
- phys_start = (0 + ntohl(master_header->offset)) & 0xffffffff;
+ cbfstool_offset = romarea;
+ phys_start = (0 + ntohl(cbfstool_master_header->offset)) & 0xffffffff;
phys_end = romsize & 0xffffffff;
break;
case CBFS_ARCHITECTURE_X86:
- offset = romarea + romsize - 0x100000000ULL;
- phys_start = (0 - romsize + ntohl(master_header->offset)) &
+ cbfstool_offset = romarea + romsize - 0x100000000ULL;
+ phys_start = (0 - romsize + ntohl(cbfstool_master_header->offset)) &
0xffffffff;
- phys_end = (0 - ntohl(master_header->bootblocksize) -
+ phys_end = (0 - ntohl(cbfstool_master_header->bootblocksize) -
sizeof(struct cbfs_header)) & 0xffffffff;
break;
default:
@@ -243,7 +246,7 @@ void recalculate_rom_geometry(void *romarea)
exit(1);
}
- align = ntohl(master_header->align);
+ align = ntohl(cbfstool_master_header->align);
}
void *loadrom(const char *filename)
@@ -351,8 +354,8 @@ void print_cbfs_directory(const char *filename)
printf
("%s: %d kB, bootblocksize %d, romsize %d, offset 0x%x\n"
"alignment: %d bytes, architecture: %s\n\n",
- basename(name), romsize / 1024, ntohl(master_header->bootblocksize),
- romsize, ntohl(master_header->offset), align, arch_to_string(arch));
+ basename(name), romsize / 1024, ntohl(cbfstool_master_header->bootblocksize),
+ romsize, ntohl(cbfstool_master_header->offset), align, arch_to_string(arch));
free(name);
printf("%-30s %-10s %-12s Size\n", "Name", "Offset", "Type");
uint32_t current = phys_start;
@@ -364,12 +367,12 @@ void print_cbfs_directory(const char *filename)
struct cbfs_file *thisfile =
(struct cbfs_file *)phys_to_virt(current);
uint32_t length = ntohl(thisfile->len);
- char *fname = (char *)(phys_to_virt(current) + sizeof(struct cbfs_file));
+ const char *fname = (char *)(phys_to_virt(current) + sizeof(struct cbfs_file));
if (strlen(fname) == 0)
fname = "(empty)";
printf("%-30s 0x%-8x %-12s %d\n", fname,
- current - phys_start + ntohl(master_header->offset),
+ current - phys_start + ntohl(cbfstool_master_header->offset),
strfiletype(ntohl(thisfile->type)), length);
/* note the components of the subheader are in host order ... */
@@ -664,7 +667,7 @@ void *create_cbfs_file(const char *filename, void *data, uint32_t * datasize,
}
int create_cbfs_image(const char *romfile, uint32_t _romsize,
- const char *bootblock, uint32_t align, uint32_t offs)
+ const char *bootblock, uint32_t create_align, uint32_t offs)
{
uint32_t bootblocksize = 0;
struct cbfs_header *master_header;
@@ -679,8 +682,8 @@ int create_cbfs_image(const char *romfile, uint32_t _romsize,
}
memset(romarea, 0xff, romsize);
- if (align == 0)
- align = 64;
+ if (create_align == 0)
+ create_align = 64;
bootblk = loadfile(bootblock, &bootblocksize,
romarea + romsize, SEEK_END);
@@ -695,7 +698,7 @@ int create_cbfs_image(const char *romfile, uint32_t _romsize,
switch (arch) {
case CBFS_ARCHITECTURE_ARMV7:
/* Set up physical/virtual mapping */
- offset = romarea;
+ cbfstool_offset = romarea;
/*
* The initial jump instruction and bootblock will be placed
@@ -746,7 +749,7 @@ int create_cbfs_image(const char *romfile, uint32_t _romsize,
case CBFS_ARCHITECTURE_X86:
// Set up physical/virtual mapping
- offset = romarea + romsize - 0x100000000ULL;
+ cbfstool_offset = romarea + romsize - 0x100000000ULL;
loadfile(bootblock, &bootblocksize, romarea + romsize,
SEEK_END);
diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h
index 6e12fcb..ed75a7f 100644
--- a/util/cbfstool/common.h
+++ b/util/cbfstool/common.h
@@ -62,7 +62,7 @@ int buffer_write_file(struct buffer *buffer, const char *filename);
/* Destroys a memory buffer. */
void buffer_delete(struct buffer *buffer);
-extern void *offset;
+extern void *cbfstool_offset;
extern uint32_t romsize;
extern int host_bigendian;
extern uint32_t arch;
@@ -72,12 +72,12 @@ uint32_t string_to_arch(const char *arch_string);
static inline void *phys_to_virt(uint32_t addr)
{
- return offset + addr;
+ return cbfstool_offset + addr;
}
static inline uint32_t virt_to_phys(void *addr)
{
- return (unsigned long)(addr - offset) & 0xffffffff;
+ return (unsigned long)(addr - cbfstool_offset) & 0xffffffff;
}
#define ALIGN(val, by) (((val) + (by)-1)&~((by)-1))
@@ -124,7 +124,6 @@ int add_file_to_cbfs(void *content, uint32_t contentsize, uint32_t location);
int remove_file_from_cbfs(const char *filename);
void print_cbfs_directory(const char *filename);
int extract_file_from_cbfs(const char *filename, const char *payloadname, const char *outpath);
-int remove_file_from_cbfs(const char *filename);
uint32_t cbfs_find_location(const char *romfile, uint32_t filesize,
const char *filename, uint32_t align);
@@ -132,5 +131,30 @@ uint32_t cbfs_find_location(const char *romfile, uint32_t filesize,
void print_supported_filetypes(void);
#define ARRAY_SIZE(a) (int)(sizeof(a) / sizeof((a)[0]))
+/* lzma/lzma.c */
+void do_lzma_compress(char *in, int in_len, char *out, int *out_len);
+void do_lzma_uncompress(char *dst, int dst_len, char *src, int src_len);
+/* xdr.c */
+struct xdr {
+ uint16_t (*get16)(struct buffer *input);
+ uint32_t (*get32)(struct buffer *input);
+ uint64_t (*get64)(struct buffer *input);
+ void (*put16)(struct buffer *input, uint16_t val);
+ void (*put32)(struct buffer *input, uint32_t val);
+ void (*put64)(struct buffer *input, uint64_t val);
+};
+
+/* common.c */
+
+int find_master_header(void *romarea, size_t size);
+void recalculate_rom_geometry(void *romarea);
+const char *strfiletype(uint32_t number);
+
+/* cbfs_image.c */
+uint32_t get_cbfs_entry_type(const char *name, uint32_t default_value);
+const char *get_cbfs_entry_type_name(uint32_t type);
+uint32_t get_cbfs_compression(const char *name, uint32_t unknown);
+
+extern struct xdr xdr_le, xdr_be;
#endif
diff --git a/util/cbfstool/compress.c b/util/cbfstool/compress.c
index 9ea1487..38fa03d 100644
--- a/util/cbfstool/compress.c
+++ b/util/cbfstool/compress.c
@@ -26,8 +26,6 @@
#include <stdio.h>
#include "common.h"
-void do_lzma_compress(char *in, int in_len, char *out, int *out_len);
-
static void lzma_compress(char *in, int in_len, char *out, int *out_len)
{
do_lzma_compress(in, in_len, out, out_len);
diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index c76ba48..f15ccf5 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -104,9 +104,9 @@ static inline int fit_entry_type(struct fit_entry *entry)
* in the host address space at [4G - romsize -> 4G). It also assume all
* pointers have values within this address range.
*/
-static inline int ptr_to_offset(uint32_t romsize, uint32_t host_ptr)
+static inline int ptr_to_offset(uint32_t theromsize, uint32_t host_ptr)
{
- return (int)(romsize + host_ptr);
+ return (int)(theromsize + host_ptr);
}
/*
@@ -114,9 +114,9 @@ static inline int ptr_to_offset(uint32_t romsize, uint32_t host_ptr)
* in the host address space at [4G - romsize -> 4G). It also assume all
* pointers have values within this address range.
*/
-static inline uint32_t offset_to_ptr(uint32_t romsize, int offset)
+static inline uint32_t offset_to_ptr(uint32_t theromsize, int offset)
{
- return -(romsize - (uint32_t )offset);
+ return -(theromsize - (uint32_t )offset);
}
static struct fit_table *locate_fit_table(struct cbfs_image *image)
diff --git a/util/cbfstool/xdr.c b/util/cbfstool/xdr.c
new file mode 100644
index 0000000..d779675
--- /dev/null
+++ b/util/cbfstool/xdr.c
@@ -0,0 +1,140 @@
+ /*
+ * cbfstool, CLI utility for CBFS file manipulation
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <unistd.h>
+#include <stdint.h>
+#include "common.h"
+
+/* The assumption in all this code is that we're given a pointer to enough data.
+ * Hence, we do not check for underflow.
+ */
+static uint8_t get8(struct buffer *input)
+{
+ uint8_t ret = *input->data++;
+ input->size--;
+ return ret;
+}
+
+static uint16_t get16be(struct buffer *input)
+{
+ uint16_t ret;
+ ret = get8(input) << 8;
+ ret |= get8(input);
+ return ret;
+}
+
+static uint32_t get32be(struct buffer *input)
+{
+ uint32_t ret;
+ ret = get16be(input) << 16;
+ ret |= get16be(input);
+ return ret;
+}
+
+static uint64_t get64be(struct buffer *input)
+{
+ uint64_t ret;
+ ret = get32be(input);
+ ret <<= 32;
+ ret |= get32be(input);
+ return ret;
+}
+
+static void put8(struct buffer *input, uint8_t val)
+{
+ input->data[input->size] = val;
+ input->size++;
+}
+
+static void put16be(struct buffer *input, uint16_t val)
+{
+ put8(input, val >> 8);
+ put8(input, val);
+}
+
+static void put32be(struct buffer *input, uint32_t val)
+{
+ put16be(input, val >> 16);
+ put16be(input, val);
+}
+
+static void put64be(struct buffer *input, uint64_t val)
+{
+ put32be(input, val >> 32);
+ put32be(input, val);
+}
+
+static uint16_t get16le(struct buffer *input)
+{
+ uint16_t ret;
+ ret = get8(input);
+ ret |= get8(input) << 8;
+ return ret;
+}
+
+static uint32_t get32le(struct buffer *input)
+{
+ uint32_t ret;
+ ret = get16le(input);
+ ret |= get16le(input) << 16;
+ return ret;
+}
+
+static uint64_t get64le(struct buffer *input)
+{
+ uint64_t ret;
+ uint32_t low;
+ low = get32le(input);
+ ret = get32le(input);
+ ret <<= 32;
+ ret |= low;
+ return ret;
+}
+
+static void put16le(struct buffer *input, uint16_t val)
+{
+ put8(input, val);
+ put8(input, val >> 8);
+}
+
+static void put32le(struct buffer *input, uint32_t val)
+{
+ put16le(input, val);
+ put16le(input, val >> 16);
+}
+
+static void put64le(struct buffer *input, uint64_t val)
+{
+ put32le(input, val);
+ put32le(input, val >> 32);
+}
+
+struct xdr xdr_be = {
+ get16be, get32be, get64be,
+ put16be, put32be, put64be
+};
+
+struct xdr xdr_le = {
+ get16le, get32le, get64le,
+ put16le, put32le, put64le
+};
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5079
-gerrit
commit 631e5c853881b66ddd89ac536e382aa889a07e6d
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Wed Jan 29 15:29:44 2014 +1100
Jetway NF81-T56N-LF: Serialize ACPI method remarks to avoid race-conditions.
Fix the remark introduced in ACPICA version 20130517 that gives the
following explanation:
If a thread blocks within the method for any reason, and another thread
enters the method, the method will fail because an attempt will be
made to create the same (named) object twice.
In this case, issue a remark that the method should be marked
serialized. ACPICA BZ 909.
The toolchain remarks fixed by this are as follows:
Intel ACPI Component Architecture
ASL Optimizing Compiler version 20130626-64 [Jan 26 2014]
Copyright (c) 2000 - 2013 Intel Corporation
dsdt.ramstage.asl 1034: Method(_GTM, 0)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.ramstage.asl 1069: Method(_STM, 3, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.ramstage.asl 1114: Method(_GTF) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.ramstage.asl 1146: Method(_GTF) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
ASL Input: dsdt.ramstage.asl - 1732 lines, 33264 bytes, 941 keywords
AML Output: dsdt.ramstage.aml - 10152 bytes, 406 named objects, 535 executable opcodes
Hex Dump: dsdt.ramstage.hex - 95502 bytes
Change-Id: I2b3605a31a8647c07be0830e54cd117d53985c81
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
index b3aed9c..4071f85 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl
@@ -77,7 +77,7 @@ Method(GTTM, 1) /* get total time*/
Device(PRID)
{
Name (_ADR, Zero)
- Method(_GTM, 0)
+ Method(_GTM, 0, Serialized)
{
NAME(OTBF, Buffer(20) { /* out buffer */
0xFF, 0xFF, 0xFF, 0xFF,
@@ -122,7 +122,7 @@ Device(PRID)
Return(OTBF) /* out buffer */
} /* End Method(_GTM) */
- Method(_STM, 3, NotSerialized)
+ Method(_STM, 3, Serialized)
{
NAME(INBF, Buffer(20) { /* in buffer */
0xFF, 0xFF, 0xFF, 0xFF,
@@ -173,7 +173,7 @@ Device(PRID)
Device(MST)
{
Name(_ADR, 0)
- Method(_GTF) {
+ Method(_GTF, 0, Serialized) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
@@ -209,7 +209,7 @@ Device(PRID)
Device(SLAV)
{
Name(_ADR, 1)
- Method(_GTF) {
+ Method(_GTF, 0, Serialized) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,