Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4888
-gerrit
commit 297a628df8e6892fb7c29167c0853a7f5204e2ee
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Oct 21 12:15:29 2013 -0500
x86: parallel MP initialization
Provide a common entry point for bringing up the APs
in parallel. This work is based off of the Haswell one
which can be moved over to this in the future. The APs
are brought up and have the BSP's MTRRs duplicated in
their own MTRRs. Additionally, Microcode is loaded before
enabling caching. However, the current microcode loading
support assumes Intel's mechanism.
The infrastructure provides a notion of a flight plan
for the BSP and APs. This allows for flexibility in the
order of operations for a given architecture/chip without
providing any specific policy. Therefore, the chipset
caller can provide the order that is required.
BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted on rambi with baytrail specific patches.
Change-Id: I0539047a1b24c13ef278695737cdba3b9344c820
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173703
---
src/cpu/x86/Kconfig | 7 +
src/cpu/x86/Makefile.inc | 25 ++
src/cpu/x86/mp_init.c | 586 ++++++++++++++++++++++++++++++++++++++++++++++
src/cpu/x86/sipi_header.c | 6 +
src/cpu/x86/sipi_vector.S | 192 +++++++++++++++
src/include/cpu/x86/mp.h | 120 ++++++++++
6 files changed, 936 insertions(+)
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index c64a8e4..21282c3 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -115,3 +115,10 @@ config X86_AMD_FIXED_MTRRS
help
This option informs the MTRR code to use the RdMem and WrMem fields
in the fixed MTRR MSRs.
+
+config PARALLEL_MP
+ def_bool n
+ help
+ This option uses common MP infrastructure for bringing up APs
+ in parallel. It additionally provides a more flexible mechanism
+ for sequencing the steps of bringing up the APs.
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
index ca755de..d5bc2fd 100644
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -1,2 +1,27 @@
romstage-$(CONFIG_EARLY_CBMEM_INIT) += car.c
romstage-$(CONFIG_HAVE_ACPI_RESUME) += car.c
+
+subdirs-$(CONFIG_PARALLEL_MP) += name
+ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
+
+SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf
+SIPI_BIN=$(SIPI_ELF:.elf=)
+SIPI_DOTO=$(SIPI_ELF:.elf=.o)
+
+ifeq ($(CONFIG_PARALLEL_MP),y)
+ramstage-srcs += $(SIPI_BIN)
+endif
+rmodules-$(CONFIG_PARALLEL_MP) += sipi_vector.S
+rmodules-$(CONFIG_PARALLEL_MP) += sipi_header.c
+
+$(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules.o $(dir $(SIPI_ELF))sipi_header.rmodules.o
+ $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^
+
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0))
+
+$(SIPI_BIN): $(SIPI_ELF)
+ $(OBJCOPY) -O binary $< $@
+
+$(SIPI_BIN).ramstage.o: $(SIPI_BIN)
+ @printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
+ cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
new file mode 100644
index 0000000..242d656
--- /dev/null
+++ b/src/cpu/x86/mp_init.c
@@ -0,0 +1,586 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <stdint.h>
+#include <rmodule.h>
+#include <arch/cpu.h>
+#include <cpu/cpu.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/name.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <cpu/x86/mp.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <lib.h>
+#include <smp/atomic.h>
+#include <smp/spinlock.h>
+#include <thread.h>
+
+#define MAX_APIC_IDS 256
+/* This needs to match the layout in the .module_parametrs section. */
+struct sipi_params {
+ uint16_t gdtlimit;
+ uint32_t gdt;
+ uint16_t unused;
+ uint32_t idt_ptr;
+ uint32_t stack_top;
+ uint32_t stack_size;
+ uint32_t microcode_lock; /* 0xffffffff means parallel loading. */
+ uint32_t microcode_ptr;
+ uint32_t msr_table_ptr;
+ uint32_t msr_count;
+ uint32_t c_handler;
+ atomic_t ap_count;
+} __attribute__((packed));
+
+/* This also needs to match the assembly code for saved MSR encoding. */
+struct saved_msr {
+ uint32_t index;
+ uint32_t lo;
+ uint32_t hi;
+} __attribute__((packed));
+
+
+/* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */
+extern char _binary_sipi_vector_start[];
+/* These symbols are defined in c_start.S. */
+extern char gdt[];
+extern char gdt_end[];
+extern char idtarg[];
+
+/* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the
+ * memory range is already reserved so the OS cannot use it. That region is
+ * free to use for AP bringup before SMM is initialized. */
+static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE;
+static const int sipi_vector_location_size = SMM_DEFAULT_SIZE;
+
+struct mp_flight_plan {
+ int num_records;
+ struct mp_flight_record *records;
+};
+
+static struct mp_flight_plan mp_info;
+
+struct cpu_map {
+ device_t dev;
+ int apic_id;
+};
+
+/* Keep track of apic and device structure for each cpu. */
+static struct cpu_map cpus[CONFIG_MAX_CPUS];
+
+static inline void barrier_wait(atomic_t *b)
+{
+ while (atomic_read(b) == 0) {
+ asm ("pause");
+ }
+ mfence();
+}
+
+static inline void release_barrier(atomic_t *b)
+{
+ mfence();
+ atomic_set(b, 1);
+}
+
+/* Returns 1 if timeout waiting for APs. 0 if target aps found. */
+static int wait_for_aps(atomic_t *val, int target, int total_delay,
+ int delay_step)
+{
+ int timeout = 0;
+ int delayed = 0;
+ while (atomic_read(val) != target) {
+ udelay(delay_step);
+ delayed += delay_step;
+ if (delayed >= total_delay) {
+ timeout = 1;
+ break;
+ }
+ }
+
+ return timeout;
+}
+
+static void ap_do_flight_plan(void)
+{
+ int i;
+
+ for (i = 0; i < mp_info.num_records; i++) {
+ struct mp_flight_record *rec = &mp_info.records[i];
+
+ atomic_inc(&rec->cpus_entered);
+ barrier_wait(&rec->barrier);
+
+ if (rec->ap_call != NULL) {
+ rec->ap_call(rec->ap_arg);
+ }
+ }
+}
+
+/* By the time APs call ap_init() caching has been setup, and microcode has
+ * been loaded. */
+static void asmlinkage ap_init(unsigned int cpu)
+{
+ struct cpu_info *info;
+ int apic_id;
+
+ /* Ensure the local apic is enabled */
+ enable_lapic();
+
+ info = cpu_info();
+ info->index = cpu;
+ info->cpu = cpus[cpu].dev;
+ thread_init_cpu_info_non_bsp(info);
+
+ apic_id = lapicid();
+ info->cpu->path.apic.apic_id = apic_id;
+ cpus[cpu].apic_id = apic_id;
+
+ printk(BIOS_INFO, "AP: slot %d apic_id %x.\n", cpu, apic_id);
+
+ /* Walk the flight plan */
+ ap_do_flight_plan();
+
+ /* Park the AP. */
+ stop_this_cpu();
+}
+
+static void setup_default_sipi_vector_params(struct sipi_params *sp)
+{
+ sp->gdt = (uint32_t)&gdt;
+ sp->gdtlimit = (uint32_t)&gdt_end - (u32)&gdt - 1;
+ sp->idt_ptr = (uint32_t)&idtarg;
+ sp->stack_size = CONFIG_STACK_SIZE;
+ sp->stack_top = (uint32_t)&_estack;
+ /* Adjust the stack top to take into account cpu_info. */
+ sp->stack_top -= sizeof(struct cpu_info);
+}
+
+#define NUM_FIXED_MTRRS 11
+static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
+ MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
+ MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR,
+ MTRRfix4K_D8000_MSR, MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR,
+ MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
+};
+
+static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
+{
+ msr_t msr;
+
+ msr = rdmsr(index);
+ entry->index = index;
+ entry->lo = msr.lo;
+ entry->hi = msr.hi;
+
+ /* Return the next entry. */
+ entry++;
+ return entry;
+}
+
+static int save_bsp_msrs(char *start, int size)
+{
+ int msr_count;
+ int num_var_mtrrs;
+ struct saved_msr *msr_entry;
+ int i;
+ msr_t msr;
+
+ /* Determine number of MTRRs need to be saved. */
+ msr = rdmsr(MTRRcap_MSR);
+ num_var_mtrrs = msr.lo & 0xff;
+
+ /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE. */
+ msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
+
+ if ((msr_count * sizeof(struct saved_msr)) > size) {
+ printk(BIOS_CRIT, "Cannot mirror all %d msrs.\n", msr_count);
+ return -1;
+ }
+
+ msr_entry = (void *)start;
+ for (i = 0; i < NUM_FIXED_MTRRS; i++) {
+ msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
+ }
+
+ for (i = 0; i < num_var_mtrrs; i++) {
+ msr_entry = save_msr(MTRRphysBase_MSR(i), msr_entry);
+ msr_entry = save_msr(MTRRphysMask_MSR(i), msr_entry);
+ }
+
+ msr_entry = save_msr(MTRRdefType_MSR, msr_entry);
+
+ return msr_count;
+}
+
+static atomic_t *load_sipi_vector(struct mp_params *mp_params)
+{
+ struct rmodule sipi_mod;
+ int module_size;
+ int num_msrs;
+ struct sipi_params *sp;
+ char *mod_loc = (void *)sipi_vector_location;
+ const int loc_size = sipi_vector_location_size;
+ atomic_t *ap_count = NULL;
+
+ if (rmodule_parse(&_binary_sipi_vector_start, &sipi_mod)) {
+ printk(BIOS_CRIT, "Unable to parse sipi module.\n");
+ return ap_count;
+ }
+
+ if (rmodule_entry_offset(&sipi_mod) != 0) {
+ printk(BIOS_CRIT, "SIPI module entry offset is not 0!\n");
+ return ap_count;
+ }
+
+ if (rmodule_load_alignment(&sipi_mod) != 4096) {
+ printk(BIOS_CRIT, "SIPI module load alignment(%d) != 4096.\n",
+ rmodule_load_alignment(&sipi_mod));
+ return ap_count;
+ }
+
+ module_size = rmodule_memory_size(&sipi_mod);
+
+ /* Align to 4 bytes. */
+ module_size = ALIGN(module_size, 4);
+
+ if (module_size > loc_size) {
+ printk(BIOS_CRIT, "SIPI module size (%d) > region size (%d).\n",
+ module_size, loc_size);
+ return ap_count;
+ }
+
+ num_msrs = save_bsp_msrs(&mod_loc[module_size], loc_size - module_size);
+
+ if (num_msrs < 0) {
+ printk(BIOS_CRIT, "Error mirroring BSP's msrs.\n");
+ return ap_count;
+ }
+
+ if (rmodule_load(mod_loc, &sipi_mod)) {
+ printk(BIOS_CRIT, "Unable to load SIPI module.\n");
+ return ap_count;
+ }
+
+ sp = rmodule_parameters(&sipi_mod);
+
+ if (sp == NULL) {
+ printk(BIOS_CRIT, "SIPI module has no parameters.\n");
+ return ap_count;
+ }
+
+ setup_default_sipi_vector_params(sp);
+ /* Setup MSR table. */
+ sp->msr_table_ptr = (uint32_t)&mod_loc[module_size];
+ sp->msr_count = num_msrs;
+ /* Provide pointer to microcode patch. */
+ sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer;
+ /* Pass on abiility to load microcode in parallel. */
+ if (mp_params->parallel_microcode_load) {
+ sp->microcode_lock = 0;
+ } else {
+ sp->microcode_lock = ~0;
+ }
+ sp->c_handler = (uint32_t)&ap_init;
+ ap_count = &sp->ap_count;
+ atomic_set(ap_count, 0);
+
+ return ap_count;
+}
+
+static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p)
+{
+ int i;
+ int max_cpus;
+ struct cpu_info *info;
+
+ max_cpus = p->num_cpus;
+ if (max_cpus > CONFIG_MAX_CPUS) {
+ printk(BIOS_CRIT, "CPU count(%d) exceeds CONFIG_MAX_CPUS(%d)\n",
+ max_cpus, CONFIG_MAX_CPUS);
+ max_cpus = CONFIG_MAX_CPUS;
+ }
+
+ info = cpu_info();
+ for (i = 1; i < max_cpus; i++) {
+ struct device_path cpu_path;
+ device_t new;
+ int apic_id;
+
+ /* Build the cpu device path */
+ cpu_path.type = DEVICE_PATH_APIC;
+
+ /* Assuming linear APIC space allocation. */
+ apic_id = info->cpu->path.apic.apic_id + i;
+ if (p->adjust_apic_id != NULL) {
+ apic_id = p->adjust_apic_id(i, apic_id);
+ }
+ cpu_path.apic.apic_id = apic_id;
+
+ /* Allocate the new cpu device structure */
+ new = alloc_find_dev(cpu_bus, &cpu_path);
+ if (new == NULL) {
+ printk(BIOS_CRIT, "Could not allocte cpu device\n");
+ max_cpus--;
+ }
+ cpus[i].dev = new;
+ }
+
+ return max_cpus;
+}
+
+/* Returns 1 for timeout. 0 on success. */
+static int apic_wait_timeout(int total_delay, int delay_step)
+{
+ int total = 0;
+ int timeout = 0;
+
+ while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
+ udelay(delay_step);
+ total += delay_step;
+ if (total >= total_delay) {
+ timeout = 1;
+ break;
+ }
+ }
+
+ return timeout;
+}
+
+static int start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_aps)
+{
+ int sipi_vector;
+ /* Max location is 4KiB below 1MiB */
+ const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
+
+ if (ap_count == 0)
+ return 0;
+
+ /* The vector is sent as a 4k aligned address in one byte. */
+ sipi_vector = sipi_vector_location >> 12;
+
+ if (sipi_vector > max_vector_loc) {
+ printk(BIOS_CRIT, "SIPI vector too large! 0x%08x\n",
+ sipi_vector);
+ return -1;
+ }
+
+ printk(BIOS_DEBUG, "Attempting to start %d APs\n", ap_count);
+
+ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
+ printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
+ if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
+ printk(BIOS_DEBUG, "timed out. Aborting.\n");
+ return -1;
+ } else
+ printk(BIOS_DEBUG, "done.\n");
+ }
+
+ /* Send INIT IPI to all but self. */
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
+ lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
+ LAPIC_DM_INIT);
+ printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n");
+ mdelay(10);
+
+ /* Send 1st SIPI */
+ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
+ printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
+ if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
+ printk(BIOS_DEBUG, "timed out. Aborting.\n");
+ return -1;
+ } else
+ printk(BIOS_DEBUG, "done.\n");
+ }
+
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
+ lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
+ LAPIC_DM_STARTUP | sipi_vector);
+ printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete...");
+ if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) {
+ printk(BIOS_DEBUG, "timed out.\n");
+ return -1;
+ } else {
+ printk(BIOS_DEBUG, "done.\n");
+ }
+
+ /* Wait for CPUs to check in up to 200 us. */
+ wait_for_aps(num_aps, ap_count, 200 /* us */, 15 /* us */);
+
+ /* Send 2nd SIPI */
+ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
+ printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
+ if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
+ printk(BIOS_DEBUG, "timed out. Aborting.\n");
+ return -1;
+ } else
+ printk(BIOS_DEBUG, "done.\n");
+ }
+
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
+ lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
+ LAPIC_DM_STARTUP | sipi_vector);
+ printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete...");
+ if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) {
+ printk(BIOS_DEBUG, "timed out.\n");
+ return -1;
+ } else {
+ printk(BIOS_DEBUG, "done.\n");
+ }
+
+ /* Wait for CPUs to check in. */
+ if (wait_for_aps(num_aps, ap_count, 10000 /* 10 ms */, 50 /* us */)) {
+ printk(BIOS_DEBUG, "Not all APs checked in: %d/%d.\n",
+ atomic_read(num_aps), ap_count);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int bsp_do_flight_plan(struct mp_params *mp_params)
+{
+ int i;
+ int ret = 0;
+ const int timeout_us = 100000;
+ const int step_us = 100;
+ int num_aps = mp_params->num_cpus - 1;
+
+ for (i = 0; i < mp_params->num_records; i++) {
+ struct mp_flight_record *rec = &mp_params->flight_plan[i];
+
+ /* Wait for APs if the record is not released. */
+ if (atomic_read(&rec->barrier) == 0) {
+ /* Wait for the APs to check in. */
+ if (wait_for_aps(&rec->cpus_entered, num_aps,
+ timeout_us, step_us)) {
+ printk(BIOS_ERR, "MP record %d timeout.\n", i);
+ ret = -1;
+ }
+ }
+
+ if (rec->bsp_call != NULL) {
+ rec->bsp_call(rec->bsp_arg);
+ }
+
+ release_barrier(&rec->barrier);
+ }
+ return ret;
+}
+
+static void init_bsp(struct bus *cpu_bus)
+{
+ struct device_path cpu_path;
+ struct cpu_info *info;
+ char processor_name[49];
+
+ /* Print processor name */
+ fill_processor_name(processor_name);
+ printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
+ /* Ensure the local apic is enabled */
+ enable_lapic();
+
+ /* Set the device path of the boot cpu. */
+ cpu_path.type = DEVICE_PATH_APIC;
+ cpu_path.apic.apic_id = lapicid();
+
+ /* Find the device structure for the boot cpu. */
+ info = cpu_info();
+ info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
+
+ if (info->index != 0)
+ printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index);
+
+ /* Track BSP in cpu_map structures. */
+ cpus[info->index].dev = info->cpu;
+ cpus[info->index].apic_id = cpu_path.apic.apic_id;
+}
+
+int mp_init(struct bus *cpu_bus, struct mp_params *p)
+{
+ int num_cpus;
+ int num_aps;
+ atomic_t *ap_count;
+
+ init_bsp(cpu_bus);
+
+ if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
+ printk(BIOS_CRIT, "Invalid MP parameters\n");
+ return -1;
+ }
+
+ /* Default to currently running CPU. */
+ num_cpus = allocate_cpu_devices(cpu_bus, p);
+
+ if (num_cpus < p->num_cpus) {
+ printk(BIOS_CRIT,
+ "ERROR: More cpus requested (%d) than supported (%d).\n",
+ p->num_cpus, num_cpus);
+ return -1;
+ }
+
+ /* Copy needed parameters so that APs have a reference to the plan. */
+ mp_info.num_records = p->num_records;
+ mp_info.records = p->flight_plan;
+
+ /* Load the SIPI vector. */
+ ap_count = load_sipi_vector(p);
+ if (ap_count == NULL)
+ return -1;
+
+ /* Make sure SIPI data hits RAM so the APs that come up will see
+ * the startup code even if the caches are disabled. */
+ wbinvd();
+
+ /* Start the APs providing number of APs and the cpus_entered field. */
+ num_aps = p->num_cpus - 1;
+ if (start_aps(cpu_bus, num_aps, ap_count) < 0) {
+ mdelay(1000);
+ printk(BIOS_DEBUG, "%d/%d eventually checked in?\n",
+ atomic_read(ap_count), num_aps);
+ return -1;
+ }
+
+ /* Walk the flight plan for the BSP. */
+ return bsp_do_flight_plan(p);
+}
+
+void mp_initialize_cpu(void *unused)
+{
+ /* Call back into driver infrastructure for the AP initialization. */
+ struct cpu_info *info = cpu_info();
+ cpu_initialize(info->index);
+}
+
+int mp_get_apic_id(int cpu_slot)
+{
+ if (cpu_slot >= CONFIG_MAX_CPUS || cpu_slot < 0)
+ return -1;
+
+ return cpus[cpu_slot].apic_id;
+}
diff --git a/src/cpu/x86/sipi_header.c b/src/cpu/x86/sipi_header.c
new file mode 100644
index 0000000..846a82d
--- /dev/null
+++ b/src/cpu/x86/sipi_header.c
@@ -0,0 +1,6 @@
+#include <rmodule.h>
+
+
+extern void *ap_start;
+
+DEFINE_RMODULE_HEADER(sipi_vector_header, ap_start, RMODULE_TYPE_SIPI_VECTOR);
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
new file mode 100644
index 0000000..52b12d0
--- /dev/null
+++ b/src/cpu/x86/sipi_vector.S
@@ -0,0 +1,192 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* The SIPI vector is responsible for initializing the APs in the sytem. It
+ * loads microcode, sets up MSRs, and enables caching before calling into
+ * C code. */
+
+/* These segment selectors need to match the gdt entries in c_start.S. */
+#define CODE_SEG 0x10
+#define DATA_SEG 0x18
+
+#define IA32_UPDT_TRIG 0x79
+#define IA32_BIOS_SIGN_ID 0x8b
+
+.section ".module_parameters", "aw", @progbits
+ap_start_params:
+gdtaddr:
+.word 0 /* limit */
+.long 0 /* table */
+.word 0 /* unused */
+idt_ptr:
+.long 0
+stack_top:
+.long 0
+stack_size:
+.long 0
+microcode_lock:
+.long 0
+microcode_ptr:
+.long 0
+msr_table_ptr:
+.long 0
+msr_count:
+.long 0
+c_handler:
+.long 0
+ap_count:
+.long 0
+
+.text
+.code16
+.global ap_start
+ap_start:
+ cli
+ xorl %eax, %eax
+ movl %eax, %cr3 /* Invalidate TLB*/
+
+ /* On hyper threaded cpus, invalidating the cache here is
+ * very very bad. Don't.
+ */
+
+ /* setup the data segment */
+ movw %cs, %ax
+ movw %ax, %ds
+
+ /* The gdtaddr needs to be releative to the data segment in order
+ * to properly dereference it. The .text section comes first in an
+ * rmodule so ap_start can be used as a proxy for the load address. */
+ movl $(gdtaddr), %ebx
+ sub $(ap_start), %ebx
+
+ data32 lgdt (%ebx)
+
+ movl %cr0, %eax
+ andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
+ orl $0x60000001, %eax /* CD, NW, PE = 1 */
+ movl %eax, %cr0
+
+ ljmpl $CODE_SEG, $1f
+1:
+ .code32
+ movw $DATA_SEG, %ax
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %ss
+ movw %ax, %fs
+ movw %ax, %gs
+
+ /* Load the Interrupt descriptor table */
+ mov idt_ptr, %ebx
+ lidt (%ebx)
+
+ /* Obtain cpu number. */
+ movl ap_count, %eax
+1:
+ movl %eax, %ecx
+ inc %ecx
+ lock cmpxchg %ecx, ap_count
+ jnz 1b
+
+ /* Setup stacks for each CPU. */
+ movl stack_size, %eax
+ mul %ecx
+ movl stack_top, %edx
+ subl %eax, %edx
+ mov %edx, %esp
+ /* Save cpu number. */
+ mov %ecx, %esi
+
+ /* Determine if one should check microcode versions. */
+ mov microcode_ptr, %edi
+ test %edi, %edi
+ jz microcode_done /* Bypass if no microde exists. */
+
+ /* Get the Microcode version. */
+ mov $1, %eax
+ cpuid
+ mov $IA32_BIOS_SIGN_ID, %ecx
+ rdmsr
+ /* If something already loaded skip loading again. */
+ test %edx, %edx
+ jnz microcode_done
+
+ /* Determine if parallel microcode loading is allowed. */
+ cmp $0xffffffff, microcode_lock
+ je load_microcode
+
+ /* Protect microcode loading. */
+lock_microcode:
+ lock bts $0, microcode_lock
+ jc lock_microcode
+
+load_microcode:
+ /* Load new microcode. */
+ mov $IA32_UPDT_TRIG, %ecx
+ xor %edx, %edx
+ mov %edi, %eax
+ /* The microcode pointer is passed in pointing to the header. Adjust
+ * pointer to reflect the payload (header size is 48 bytes). */
+ add $48, %eax
+ pusha
+ wrmsr
+ popa
+
+ /* Unconditionally unlock microcode loading. */
+ cmp $0xffffffff, microcode_lock
+ je microcode_done
+
+ xor %eax, %eax
+ mov %eax, microcode_lock
+
+microcode_done:
+ /*
+ * Load MSRs. Each entry in the table consists of:
+ * 0: index,
+ * 4: value[31:0]
+ * 8: value[63:32]
+ */
+ mov msr_table_ptr, %edi
+ mov msr_count, %ebx
+ test %ebx, %ebx
+ jz 1f
+load_msr:
+ mov (%edi), %ecx
+ mov 4(%edi), %eax
+ mov 8(%edi), %edx
+ wrmsr
+ add $12, %edi
+ dec %ebx
+ jnz load_msr
+
+1:
+ /* Enable caching. */
+ mov %cr0, %eax
+ and $0x9fffffff, %eax /* CD, NW = 0 */
+ mov %eax, %cr0
+
+ /* c_handler(cpu_num) */
+ push %esi /* cpu_num */
+ mov c_handler, %eax
+ call *%eax
+halt_jump:
+ hlt
+ jmp halt_jump
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
new file mode 100644
index 0000000..5112848
--- /dev/null
+++ b/src/include/cpu/x86/mp.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _X86_MP_H_
+#define _X86_MP_H_
+
+#include <arch/smp/atomic.h>
+
+#define CACHELINE_SIZE 64
+
+struct cpu_info;
+struct bus;
+
+static inline void mfence(void)
+{
+ __asm__ __volatile__("mfence\t\n": : :"memory");
+}
+
+typedef void (*mp_callback_t)(void *arg);
+
+/*
+ * A mp_flight_record details a sequence of calls for the APs to perform
+ * along with the BSP to coordinate sequencing. Each flight record either
+ * provides a barrier for each AP before calling the callback or the APs
+ * are allowed to perform the callback without waiting. Regardless, each
+ * record has the cpus_entered field incremented for each record. When
+ * the BSP observes that the cpus_entered matches the number of APs
+ * the bsp_call is called with bsp_arg and upon returning releases the
+ * barrier allowing the APs to make further progress.
+ *
+ * Note that ap_call() and bsp_call() can be NULL. In the NULL case the
+ * callback will just not be called.
+ */
+struct mp_flight_record {
+ atomic_t barrier;
+ atomic_t cpus_entered;
+ mp_callback_t ap_call;
+ void *ap_arg;
+ mp_callback_t bsp_call;
+ void *bsp_arg;
+} __attribute__((aligned(CACHELINE_SIZE)));
+
+#define _MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
+ { \
+ .barrier = ATOMIC_INIT(barrier_), \
+ .cpus_entered = ATOMIC_INIT(0), \
+ .ap_call = ap_func_, \
+ .ap_arg = ap_arg_, \
+ .bsp_call = bsp_func_, \
+ .bsp_arg = bsp_arg_, \
+ }
+
+#define MP_FR_BLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
+ _MP_FLIGHT_RECORD(0, ap_func_, ap_arg_, bsp_func_, bsp_arg_)
+
+#define MP_FR_NOBLOCK_APS(ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
+ _MP_FLIGHT_RECORD(1, ap_func_, ap_arg_, bsp_func_, bsp_arg_)
+
+/* The mp_params structure provides the arguments to the mp subsystem
+ * for bringing up APs. */
+struct mp_params {
+ int num_cpus; /* Total cpus include BSP */
+ int parallel_microcode_load;
+ const void *microcode_pointer;
+ /* adjust_apic_id() is called for every potential apic id in the
+ * system up from 0 to CONFIG_MAX_CPUS. Return adjusted apic_id. */
+ int (*adjust_apic_id)(int index, int apic_id);
+ /* Flight plan for APs and BSP. */
+ struct mp_flight_record *flight_plan;
+ int num_records;
+};
+
+/*
+ * mp_init() will set up the SIPI vector and bring up the APs according to
+ * mp_params. Each flight record will be executed according to the plan. Note
+ * that the MP infrastructure uses SMM default area without saving it. It's
+ * up to the chipset or mainboard to either e820 reserve this area or save this
+ * region prior to calling mp_init() and restoring it after mp_init returns.
+ *
+ * At the time mp_init() is called the MTRR MSRs are mirrored into APs then
+ * caching is enabled before running the flight plan.
+ *
+ * The MP initialization has the following properties:
+ * 1. APs are brought up in parallel.
+ * 2. The ordering of coreboot cpu number and APIC ids is not deterministic.
+ * Therefore, one cannot rely on this property or the order of devices in
+ * the device tree unless the chipset or mainboard know the APIC ids
+ * a priori.
+ *
+ * mp_init() returns < 0 on error, 0 on success.
+ */
+int mp_init(struct bus *cpu_bus, struct mp_params *params);
+
+/*
+ * Useful functions to use in flight records when sequencing APs.
+ */
+
+/* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */
+void mp_initialize_cpu(void *unused);
+
+/* Returns apic id for coreboot cpu number or < 0 on failure. */
+int mp_get_apic_id(int cpu_slot);
+
+#endif /* _X86_MP_H_ */
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4891
-gerrit
commit 07ecd37b9577d047952339d40dbaf3bb99c27ef8
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Oct 21 22:24:40 2013 -0500
x86: Add SMM helper functions to MP infrastructure
In order for the cpu code to start SMM relocation 2 new
functions are added to be shared:
- void smm_initiate_relocation_parallel()
- void smm_initiate_relocation()
The both initiate an SMI on the currently running cpu.
The 2 variants allow for parallel relocation or serialized
relocation.
BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted rambi using these functions.
Change-Id: I325777bac27e9a0efc3f54f7223c38310604c5a2
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173982
---
src/cpu/x86/mp_init.c | 31 +++++++++++++++++++++++++++++++
src/include/cpu/x86/mp.h | 9 +++++++++
2 files changed, 40 insertions(+)
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 242d656..676c2f6 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -584,3 +584,34 @@ int mp_get_apic_id(int cpu_slot)
return cpus[cpu_slot].apic_id;
}
+
+void smm_initiate_relocation_parallel(void)
+{
+ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
+ printk(BIOS_DEBUG, "Waiting for ICR not to be busy...");
+ if (apic_wait_timeout(1000 /* 1 ms */, 50)) {
+ printk(BIOS_DEBUG, "timed out. Aborting.\n");
+ return;
+ } else
+ printk(BIOS_DEBUG, "done.\n");
+ }
+
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(lapicid()));
+ lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT | LAPIC_DM_SMI);
+ if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */)) {
+ printk(BIOS_DEBUG, "SMI Relocation timed out.\n");
+ } else
+ printk(BIOS_DEBUG, "Relocation complete.\n");
+
+}
+
+DECLARE_SPIN_LOCK(smm_relocation_lock);
+
+/* Send SMI to self with single user serialization. */
+void smm_initiate_relocation(void)
+{
+ spin_lock(&smm_relocation_lock);
+ smm_initiate_relocation_parallel();
+ spin_unlock(&smm_relocation_lock);
+}
+
diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h
index 5112848..7e90ee4 100644
--- a/src/include/cpu/x86/mp.h
+++ b/src/include/cpu/x86/mp.h
@@ -117,4 +117,13 @@ void mp_initialize_cpu(void *unused);
/* Returns apic id for coreboot cpu number or < 0 on failure. */
int mp_get_apic_id(int cpu_slot);
+/*
+ * SMM helpers to use with initializing CPUs.
+ */
+
+/* Send SMI to self without any serialization. */
+void smm_initiate_relocation_parallel(void);
+/* Send SMI to self with single execution. */
+void smm_initiate_relocation(void);
+
#endif /* _X86_MP_H_ */
Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5076
-gerrit
commit 94e8732b29c294a918e8198da97912ca377e43e4
Author: Lubomir Rintel <lkundrak(a)v3.sk>
Date: Tue Jan 28 16:33:37 2014 +0000
Update addresses in license text
rpmlint is unhappy about the old addresses. Changed inline where appropriate.
The full license text were replaced with ones from the FSF web site [1] [2].
They change nothing in text apart from cosmetical issues. The diff might not be
very useful for the LGPL text, but using the up-to-date files from FSF ensures
that it's easily verified that the files are intact.
[1] http://www.gnu.org/licenses/gpl-2.0.txt
[2] http://www.gnu.org/licenses/lgpl-2.1.txt
Change-Id: I16d5d5ae0d3fff907689ff96424eace78e0c938a
Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk>
---
payloads/bayou/util/pbuilder/lzma/C/LGPL.txt | 1006 +++++++++++++-------------
payloads/libpayload/arch/x86/string.c | 4 +-
payloads/libpayload/include/endian.h | 4 +-
payloads/libpayload/include/ipchksum.h | 4 +-
src/arch/armv7/bootblock.inc | 4 +-
src/arch/armv7/div0.c | 4 +-
src/arch/armv7/include/armv7.h | 4 +-
src/arch/armv7/include/clocks.h | 4 +-
src/arch/armv7/include/utils.h | 4 +-
src/arch/armv7/interrupts.c | 4 +-
src/arch/x86/lib/memset.c | 4 +-
src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 4 +-
src/cpu/samsung/exynos5420/dp.c | 4 +-
src/cpu/samsung/exynos5420/dp_lowlevel.c | 4 +-
src/cpu/ti/am335x/header.c | 4 +-
src/cpu/ti/am335x/header.h | 4 +-
src/cpu/ti/am335x/pinmux.c | 4 +-
src/cpu/ti/am335x/pinmux.h | 4 +-
src/cpu/ti/am335x/timer.c | 4 +-
src/cpu/ti/am335x/uart.c | 2 +-
src/cpu/ti/am335x/uart.h | 4 +-
src/drivers/maxim/max77686/max77686.c | 4 +-
src/drivers/maxim/max77686/max77686.h | 4 +-
src/drivers/maxim/max77802/max77802.h | 4 +-
src/drivers/spi/spansion.c | 4 +-
src/drivers/spi/stmicro.c | 4 +-
src/ec/google/chromeec/ec_message.h | 4 +-
src/include/endian.h | 4 +-
src/include/spi-generic.h | 4 +-
src/include/spi_flash.h | 4 +-
src/lib/hexdump.c | 4 +-
src/mainboard/emulation/qemu-i440fx/dsdt.asl | 2 +-
src/southbridge/intel/bd82x6x/spi.c | 4 +-
src/southbridge/intel/fsp_bd82x6x/spi.c | 4 +-
src/southbridge/intel/ibexpeak/spi.c | 4 +-
src/southbridge/intel/lynxpoint/spi.c | 4 +-
util/acpi/acpidump-all | 2 +-
util/mkelfImage/COPYING | 44 +-
util/mkelfImage/config/config.guess | 2 +-
util/mkelfImage/config/config.sub | 4 +-
40 files changed, 595 insertions(+), 599 deletions(-)
diff --git a/payloads/bayou/util/pbuilder/lzma/C/LGPL.txt b/payloads/bayou/util/pbuilder/lzma/C/LGPL.txt
index 63ac1b6..4362b49 100644
--- a/payloads/bayou/util/pbuilder/lzma/C/LGPL.txt
+++ b/payloads/bayou/util/pbuilder/lzma/C/LGPL.txt
@@ -1,504 +1,502 @@
- GNU LESSER GENERAL PUBLIC LICENSE
- Version 2.1, February 1999
-
- Copyright (C) 1991, 1999 Free Software Foundation, Inc.
- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-[This is the first released version of the Lesser GPL. It also counts
- as the successor of the GNU Library Public License, version 2, hence
- the version number 2.1.]
-
- Preamble
-
- The licenses for most software are designed to take away your
-freedom to share and change it. By contrast, the GNU General Public
-Licenses are intended to guarantee your freedom to share and change
-free software--to make sure the software is free for all its users.
-
- This license, the Lesser General Public License, applies to some
-specially designated software packages--typically libraries--of the
-Free Software Foundation and other authors who decide to use it. You
-can use it too, but we suggest you first think carefully about whether
-this license or the ordinary General Public License is the better
-strategy to use in any particular case, based on the explanations below.
-
- When we speak of free software, we are referring to freedom of use,
-not price. Our General Public Licenses are designed to make sure that
-you have the freedom to distribute copies of free software (and charge
-for this service if you wish); that you receive source code or can get
-it if you want it; that you can change the software and use pieces of
-it in new free programs; and that you are informed that you can do
-these things.
-
- To protect your rights, we need to make restrictions that forbid
-distributors to deny you these rights or to ask you to surrender these
-rights. These restrictions translate to certain responsibilities for
-you if you distribute copies of the library or if you modify it.
-
- For example, if you distribute copies of the library, whether gratis
-or for a fee, you must give the recipients all the rights that we gave
-you. You must make sure that they, too, receive or can get the source
-code. If you link other code with the library, you must provide
-complete object files to the recipients, so that they can relink them
-with the library after making changes to the library and recompiling
-it. And you must show them these terms so they know their rights.
-
- We protect your rights with a two-step method: (1) we copyright the
-library, and (2) we offer you this license, which gives you legal
-permission to copy, distribute and/or modify the library.
-
- To protect each distributor, we want to make it very clear that
-there is no warranty for the free library. Also, if the library is
-modified by someone else and passed on, the recipients should know
-that what they have is not the original version, so that the original
-author's reputation will not be affected by problems that might be
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-
- Finally, software patents pose a constant threat to the existence of
-any free program. We wish to make sure that a company cannot
-effectively restrict the users of a free program by obtaining a
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-any patent license obtained for a version of the library must be
-consistent with the full freedom of use specified in this license.
-
- Most GNU software, including some libraries, is covered by the
-ordinary GNU General Public License. This license, the GNU Lesser
-General Public License, applies to certain designated libraries, and
-is quite different from the ordinary General Public License. We use
-this license for certain libraries in order to permit linking those
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- When a program is linked with a library, whether statically or using
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-Public License permits more lax criteria for linking other code with
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- We call this license the "Lesser" General Public License because it
-does Less to protect the user's freedom than the ordinary General
-Public License. It also provides other free software developers Less
-of an advantage over competing non-free programs. These disadvantages
-are the reason we use the ordinary General Public License for many
-libraries. However, the Lesser license provides advantages in certain
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-operating system, as well as its variant, the GNU/Linux operating
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+ 7. You may place library facilities that are a work based on the
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+ 9. You are not required to accept this License, since you have not
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+ 11. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
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+
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+
+ 12. If the distribution and/or use of the Library is restricted in
+certain countries either by patents or by copyrighted interfaces, the
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+so that distribution is permitted only in or among countries not thus
+excluded. In such case, this License incorporates the limitation as if
+written in the body of this License.
+
+ 13. The Free Software Foundation may publish revised and/or new
+versions of the Lesser General Public License from time to time.
+Such new versions will be similar in spirit to the present version,
+but may differ in detail to address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Library
+specifies a version number of this License which applies to it and
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+conditions either of that version or of any later version published by
+the Free Software Foundation. If the Library does not specify a
+license version number, you may choose any version ever published by
+the Free Software Foundation.
+
+ 14. If you wish to incorporate parts of the Library into other free
+programs whose distribution conditions are incompatible with these,
+write to the author to ask for permission. For software which is
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+Software Foundation; we sometimes make exceptions for this. Our
+decision will be guided by the two goals of preserving the free status
+of all derivatives of our free software and of promoting the sharing
+and reuse of software generally.
+
+ NO WARRANTY
+
+ 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO
+WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
+EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
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+ 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
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+AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU
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+FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
+SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Libraries
+
+ If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
+everyone can redistribute and change. You can do so by permitting
+redistribution under these terms (or, alternatively, under the terms of the
+ordinary General Public License).
+
+ To apply these terms, attach the following notices to the library. It is
+safest to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least the
+"copyright" line and a pointer to where the full notice is found.
+
+ <one line to give the library's name and a brief idea of what it does.>
+ Copyright (C) <year> <name of author>
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+Also add information on how to contact you by electronic and paper mail.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the library, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the
+ library `Frob' (a library for tweaking knobs) written by James Random Hacker.
+
+ <signature of Ty Coon>, 1 April 1990
+ Ty Coon, President of Vice
+
+That's all there is to it!
diff --git a/payloads/libpayload/arch/x86/string.c b/payloads/libpayload/arch/x86/string.c
index 19047ee..117bde1 100644
--- a/payloads/libpayload/arch/x86/string.c
+++ b/payloads/libpayload/arch/x86/string.c
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/* From glibc-2.14, sysdeps/i386/memset.c */
diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h
index cb50443..ee409e5 100644
--- a/payloads/libpayload/include/endian.h
+++ b/payloads/libpayload/include/endian.h
@@ -16,8 +16,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _ENDIAN_H_
diff --git a/payloads/libpayload/include/ipchksum.h b/payloads/libpayload/include/ipchksum.h
index b7ded08..ac47573 100644
--- a/payloads/libpayload/include/ipchksum.h
+++ b/payloads/libpayload/include/ipchksum.h
@@ -16,8 +16,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __IPCHKSUM_H__
diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc
index b2c993a..eb14aa5 100644
--- a/src/arch/armv7/bootblock.inc
+++ b/src/arch/armv7/bootblock.inc
@@ -25,8 +25,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
.section ".start", "a", %progbits
diff --git a/src/arch/armv7/div0.c b/src/arch/armv7/div0.c
index ab06ad3..60cd415 100644
--- a/src/arch/armv7/div0.c
+++ b/src/arch/armv7/div0.c
@@ -17,8 +17,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <console/console.h>
diff --git a/src/arch/armv7/include/armv7.h b/src/arch/armv7/include/armv7.h
index 1473234..366b7a4 100644
--- a/src/arch/armv7/include/armv7.h
+++ b/src/arch/armv7/include/armv7.h
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef ARMV7_H
#define ARMV7_H
diff --git a/src/arch/armv7/include/clocks.h b/src/arch/armv7/include/clocks.h
index 8f35303..b87a12b 100644
--- a/src/arch/armv7/include/clocks.h
+++ b/src/arch/armv7/include/clocks.h
@@ -15,8 +15,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/* Standard clock speeds */
diff --git a/src/arch/armv7/include/utils.h b/src/arch/armv7/include/utils.h
index 828b86c..33cb770 100644
--- a/src/arch/armv7/include/utils.h
+++ b/src/arch/armv7/include/utils.h
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _UTILS_H_
#define _UTILS_H_
diff --git a/src/arch/armv7/interrupts.c b/src/arch/armv7/interrupts.c
index 7508c69..f384893 100644
--- a/src/arch/armv7/interrupts.c
+++ b/src/arch/armv7/interrupts.c
@@ -31,8 +31,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <reset.h>
diff --git a/src/arch/x86/lib/memset.c b/src/arch/x86/lib/memset.c
index 7c8129a..9060be6 100644
--- a/src/arch/x86/lib/memset.c
+++ b/src/arch/x86/lib/memset.c
@@ -17,8 +17,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/* From glibc-2.14, sysdeps/i386/memset.c */
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index ebfe1e1..17bd95e 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -20,8 +20,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <console/console.h>
diff --git a/src/cpu/samsung/exynos5420/dp.c b/src/cpu/samsung/exynos5420/dp.c
index a1c69c5..c05a19a 100644
--- a/src/cpu/samsung/exynos5420/dp.c
+++ b/src/cpu/samsung/exynos5420/dp.c
@@ -15,8 +15,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <arch/io.h>
diff --git a/src/cpu/samsung/exynos5420/dp_lowlevel.c b/src/cpu/samsung/exynos5420/dp_lowlevel.c
index 64a2962..aeaa526 100644
--- a/src/cpu/samsung/exynos5420/dp_lowlevel.c
+++ b/src/cpu/samsung/exynos5420/dp_lowlevel.c
@@ -15,8 +15,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <arch/io.h>
diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c
index 5ed943e..fafd3d9 100644
--- a/src/cpu/ti/am335x/header.c
+++ b/src/cpu/ti/am335x/header.c
@@ -13,8 +13,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <config.h>
diff --git a/src/cpu/ti/am335x/header.h b/src/cpu/ti/am335x/header.h
index 84afd35..09b502e 100644
--- a/src/cpu/ti/am335x/header.h
+++ b/src/cpu/ti/am335x/header.h
@@ -13,8 +13,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __CPU_TI_AM335X_HEADER_H
diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c
index 292865a..9b76e20 100644
--- a/src/cpu/ti/am335x/pinmux.c
+++ b/src/cpu/ti/am335x/pinmux.c
@@ -14,8 +14,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include "pinmux.h"
diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h
index 1b488e8..7f23616 100644
--- a/src/cpu/ti/am335x/pinmux.h
+++ b/src/cpu/ti/am335x/pinmux.h
@@ -14,8 +14,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __CPU_TI_AM335X_PINMUX_H
diff --git a/src/cpu/ti/am335x/timer.c b/src/cpu/ti/am335x/timer.c
index 07b162a..9b7e490 100644
--- a/src/cpu/ti/am335x/timer.c
+++ b/src/cpu/ti/am335x/timer.c
@@ -16,8 +16,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <console/console.h>
diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c
index bd2ff44..82a2ab0 100644
--- a/src/cpu/ti/am335x/uart.c
+++ b/src/cpu/ti/am335x/uart.c
@@ -13,7 +13,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <config.h>
diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h
index 645cd43..e38a55e 100644
--- a/src/cpu/ti/am335x/uart.h
+++ b/src/cpu/ti/am335x/uart.h
@@ -13,8 +13,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef AM335X_UART_H
diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c
index adc1627..649be6a 100644
--- a/src/drivers/maxim/max77686/max77686.c
+++ b/src/drivers/maxim/max77686/max77686.c
@@ -17,8 +17,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <console/console.h>
diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h
index cebd2d9..83ccccf 100644
--- a/src/drivers/maxim/max77686/max77686.h
+++ b/src/drivers/maxim/max77686/max77686.h
@@ -17,8 +17,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __MAX77686_H_
diff --git a/src/drivers/maxim/max77802/max77802.h b/src/drivers/maxim/max77802/max77802.h
index beb7195..925d31d 100644
--- a/src/drivers/maxim/max77802/max77802.h
+++ b/src/drivers/maxim/max77802/max77802.h
@@ -17,8 +17,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef __MAX77802_H_
diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c
index 6dd6df9..2ff4eee 100644
--- a/src/drivers/spi/spansion.c
+++ b/src/drivers/spi/spansion.c
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <stdlib.h>
diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c
index af23853..debc789 100644
--- a/src/drivers/spi/stmicro.c
+++ b/src/drivers/spi/stmicro.c
@@ -23,8 +23,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <stdlib.h>
diff --git a/src/ec/google/chromeec/ec_message.h b/src/ec/google/chromeec/ec_message.h
index a2421c7..37719e3 100644
--- a/src/ec/google/chromeec/ec_message.h
+++ b/src/ec/google/chromeec/ec_message.h
@@ -17,8 +17,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _CROS_MESSAGE_H
diff --git a/src/include/endian.h b/src/include/endian.h
index b511a49..bb12c39 100644
--- a/src/include/endian.h
+++ b/src/include/endian.h
@@ -13,8 +13,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _ENDIAN_H_
diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h
index 6cdb87a..fc6bc7d 100644
--- a/src/include/spi-generic.h
+++ b/src/include/spi-generic.h
@@ -17,8 +17,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _SPI_GENERIC_H_
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index fe48d3b..e11d800 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -17,8 +17,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#ifndef _SPI_FLASH_H_
#define _SPI_FLASH_H_
diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c
index 82b0a3b..b0f99a1 100644
--- a/src/lib/hexdump.c
+++ b/src/lib/hexdump.c
@@ -16,8 +16,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
#include <console/console.h>
diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl
index e63d10f..6800a4f 100644
--- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl
+++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl
@@ -14,7 +14,7 @@
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
DefinitionBlock (
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 1f2511e..72e2cfb 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/* This file is derived from the flashrom project. */
diff --git a/src/southbridge/intel/fsp_bd82x6x/spi.c b/src/southbridge/intel/fsp_bd82x6x/spi.c
index 887463a..c93b36f 100644
--- a/src/southbridge/intel/fsp_bd82x6x/spi.c
+++ b/src/southbridge/intel/fsp_bd82x6x/spi.c
@@ -16,8 +16,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/* This file is derived from the flashrom project. */
diff --git a/src/southbridge/intel/ibexpeak/spi.c b/src/southbridge/intel/ibexpeak/spi.c
index 7080fe1..9a7890b 100644
--- a/src/southbridge/intel/ibexpeak/spi.c
+++ b/src/southbridge/intel/ibexpeak/spi.c
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/* This file is derived from the flashrom project. */
diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c
index 5501efc..10efec9 100644
--- a/src/southbridge/intel/lynxpoint/spi.c
+++ b/src/southbridge/intel/lynxpoint/spi.c
@@ -16,8 +16,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
*/
/* This file is derived from the flashrom project. */
diff --git a/util/acpi/acpidump-all b/util/acpi/acpidump-all
index aa73a15..5d87fc1 100755
--- a/util/acpi/acpidump-all
+++ b/util/acpi/acpidump-all
@@ -13,7 +13,7 @@
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
#
rm -rf out
diff --git a/util/mkelfImage/COPYING b/util/mkelfImage/COPYING
index 0d1ceba..d159169 100644
--- a/util/mkelfImage/COPYING
+++ b/util/mkelfImage/COPYING
@@ -1,13 +1,12 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
- GNU GENERAL PUBLIC LICENSE
- Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
- Preamble
+ Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
@@ -16,7 +15,7 @@ software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.) You can apply it to
+the GNU Lesser General Public License instead.) You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
@@ -56,8 +55,8 @@ patent must be licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and
modification follow.
-
- GNU GENERAL PUBLIC LICENSE
+
+ GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains
@@ -111,7 +110,7 @@ above, provided that you also meet all of these conditions:
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
-
+
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
@@ -169,7 +168,7 @@ access to copy from a designated place, then offering equivalent
access to copy the source code from the same place counts as
distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
-
+
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
@@ -226,7 +225,7 @@ impose that choice.
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
-
+
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
@@ -256,7 +255,7 @@ make exceptions for this. Our decision will be guided by the two goals
of preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
- NO WARRANTY
+ NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
@@ -278,9 +277,9 @@ YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
- END OF TERMS AND CONDITIONS
-
- How to Apply These Terms to Your New Programs
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
@@ -292,7 +291,7 @@ convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
<one line to give the program's name and a brief idea of what it does.>
- Copyright (C) 19yy <name of author>
+ Copyright (C) <year> <name of author>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -304,17 +303,16 @@ the "copyright" line and a pointer to where the full notice is found.
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
- Gnomovision version 69, Copyright (C) 19yy name of author
+ Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
@@ -337,5 +335,5 @@ necessary. Here is a sample; alter the names:
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
-library. If this is what you want to do, use the GNU Library General
+library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.
diff --git a/util/mkelfImage/config/config.guess b/util/mkelfImage/config/config.guess
index ff40ddb0..0a927a5 100755
--- a/util/mkelfImage/config/config.guess
+++ b/util/mkelfImage/config/config.guess
@@ -17,7 +17,7 @@ timestamp='2002-03-20'
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
#
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
diff --git a/util/mkelfImage/config/config.sub b/util/mkelfImage/config/config.sub
index f365797..33f2cd8 100755
--- a/util/mkelfImage/config/config.sub
+++ b/util/mkelfImage/config/config.sub
@@ -21,8 +21,8 @@ timestamp='2002-03-07'
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330,
-# Boston, MA 02111-1307, USA.
+# Foundation, Inc., 51 Franklin Street, Fifth Floor,
+# Boston, MA 02110-1301 USA.
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
the following patch was just integrated into master:
commit 1fae0d2f34e02b54790f5ae21d7758c279948c1b
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 25 14:38:51 2014 +0100
bachmann/ot200: Fix cmos.layout.
In current cmos.layout baud_rate overlaps with hardcoded reboot byte.
Fix the layout and provide the default for upgrade.
Change-Id: I979b8743c4aab6f17b3acf61b92a74a333203379
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
See http://review.coreboot.org/4804 for details.
-gerrit
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4801
-gerrit
commit a107c9e3f0ea216ff5842e3784a9319204cef926
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sat Jan 25 21:46:10 2014 +1100
Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
Step 2: change the Persimmon code to adapt it to the new board's hardware.
The NF81-T56N-LF is a IPC form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) APU
- 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (1.5 or 1.35V)?
- VGA and LVDS (via Analogix ANX3110)
- AMD A55E (Hudson-E1) southbridge
- 6x USB 2.0/1.1 ports
- 5x SATA3 6Gb/s, 1x mSATA socket
- 6-Channel HD Audio (via VIA VT1705)
- PCI and ISA (via ITE IT8888)??
- NEC uPD78F0532 microcontroller on I2C ("SEMA")??
- 2x RJ45 GbE (via Realtek RTL8111E x2)
- Fintek F71869AD Super I/O
- PS/2 KB/MS port
- RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
- GPIO header
- CIR header
- 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)
Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies*
claiming the SPI flash is 16MB. They also use red pen over the chip
so you wont see this deceit.
Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/Kconfig | 3 ++
src/mainboard/jetway/nf81-t56n-lf/Kconfig | 18 ++++---
src/mainboard/jetway/nf81-t56n-lf/board_info.txt | 5 +-
src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 62 ++++++++++++++++--------
src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 3 ++
src/mainboard/jetway/nf81-t56n-lf/romstage.c | 7 +--
6 files changed, 65 insertions(+), 33 deletions(-)
diff --git a/src/mainboard/jetway/Kconfig b/src/mainboard/jetway/Kconfig
index 7e6e29d..5b55daa 100644
--- a/src/mainboard/jetway/Kconfig
+++ b/src/mainboard/jetway/Kconfig
@@ -11,6 +11,8 @@ config BOARD_JETWAY_J7F4K1G5D
bool "J7F4K1G5D"
config BOARD_JETWAY_PA78VM5
bool "PA78VM5 (Fam10)"
+config BOARD_JETWAY_NF81_T56N_LF
+ bool "NF81_T56N_LF"
endchoice
@@ -18,6 +20,7 @@ source "src/mainboard/jetway/j7f2/Kconfig"
source "src/mainboard/jetway/j7f4k1g2e/Kconfig"
source "src/mainboard/jetway/j7f4k1g5d/Kconfig"
source "src/mainboard/jetway/pa78vm5/Kconfig"
+source "src/mainboard/jetway/nf81-t56n-lf/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index febd8dd..d602ffa 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -17,7 +18,7 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-if BOARD_AMD_PERSIMMON
+if BOARD_JETWAY_NF81_T56N_LF
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -25,22 +26,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
- select SUPERIO_FINTEK_F81865F
+ select SUPERIO_FINTEK_F71869AD
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select HAVE_ACPI_RESUME
+# FIXME: Disable S3 for now. Enable by default once stabilised.
+# select HAVE_ACPI_RESUME
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_4096
+ select BOARD_ROMSIZE_KB_2048
select GFXUMA
config MAINBOARD_DIR
string
- default amd/persimmon
+ default jetway/nf81-t56n-lf
config APIC_ID_OFFSET
hex
@@ -48,7 +50,7 @@ config APIC_ID_OFFSET
config MAINBOARD_PART_NUMBER
string
- default "Persimmon"
+ default "NF81-T56N-LF"
config HW_MEM_HOLE_SIZEK
hex
@@ -101,7 +103,7 @@ config VGA_BIOS
config VGA_BIOS_ID
string
- default "1002,9802"
+ default "1002,9806" # FUSION_G_T56N
config SB800_AHCI_ROM
bool
@@ -111,4 +113,4 @@ config DRIVERS_PS2_KEYBOARD
bool
default n
-endif # BOARD_AMD_PERSIMMON
+endif # BOARD_JETWAY_NF81_T56N_LF
diff --git a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
index 85cb19a..6748751 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
+++ b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt
@@ -1,5 +1,6 @@
-Board name: DBFT1-00-EVAL-KT (Persimmon)
-Category: eval
+Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T5…
+Category: Mini-ITX
+ROM package: SOIC8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 8b1acd5..3624744 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -2,6 +2,7 @@
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -29,7 +30,8 @@ chip northbridge/amd/agesa/family14/root_complex
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
- device pci 4.0 on end # PCIE P2P bridge on-board NIC
+# device pci 1.1 on end # Internal Audio P2P bridge 0x1314
+ device pci 4.0 off end # PCIE P2P bridge on-board NIC
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge PCIe slot
device pci 7.0 off end # PCIE P2P bridge
@@ -50,43 +52,58 @@ chip northbridge/amd/agesa/family14/root_complex
device i2c 51 on end
end
end # SM
- device pci 14.1 on end # IDE 0x439c
+ device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
- chip superio/fintek/f81865f
- device pnp 4e.0 off # Floppy
+ chip superio/fintek/f71869ad
+# XXX: 4e is the default index port and .xy is the
+# LDN indexing the pnp_info array found in the superio.c
+ device pnp 4e.00 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
- device pnp 4e.3 off end # Parallel Port
- device pnp 4e.4 off end # Hardware Monitor
- device pnp 4e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 4e.6 off end # GPIO
- device pnp 4e.a off end # PME
- device pnp 4e.10 on # COM1
+ device pnp 4e.01 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 4e.11 on # COM2
+ device pnp 4e.02 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
- end # f81865f
+ device pnp 4e.03 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 4e.04 on # Hardware Monitor
+ io 0x60 = 0x295
+ irq 0x70 = 0
+ end
+ device pnp 4e.05 on # KBC
+ io 0x60 = 0x060
+ irq 0x70 = 1 # Keyboard IRQ
+ irq 0x70 = 12 # Mouse IRQ
+ end
+ device pnp 4e.06 off end # GPIO
+# TODO: Verify BSEL register content with vendor BIOS using
+# $ sudo isadump 0x4e 0x4f 0x7
+# which select logical device (LDN) 7. Then read that we have in 0x27, bit1
+ device pnp 4e.07 on # BSEL
+ io 0x60 = 0x000
+ end
+ device pnp 4e.0a on end # PME
+ end # f71869ad
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
- device pci 14.5 off end # OHCI FS/LS USB
+ device pci 14.5 on end # OHCI FS/LS USB (0x4399)
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
- device pci 15.0 off end # PCIe PortA
+ device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
- device pci 16.0 off end # OHCI USB 10-13
- device pci 16.2 off end # EHCI USB 10-13
+ device pci 16.0 on end # OHCI USB 10-13 (0x4397)
+ device pci 16.2 on end # EHCI USB 10-13 (0x4396)
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
@@ -150,6 +167,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.6 on end
device pci 18.7 on end
+#
+# TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
+# with i2cdump tool.
+# Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
+#
register "spdAddrLookup" = "
{
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
index 0578e27..e638892 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -227,6 +228,7 @@
*/
#define GEC_CONFIG 0
+/* FIXME: Verify this for sound to work! */
static const CODECENTRY persimmon_codec_alc269[] =
{
/* NID, PinConfig */
@@ -244,6 +246,7 @@ static const CODECENTRY persimmon_codec_alc269[] =
{0xff, 0xffffffff} /* end of table */
};
+/* FIXME: Verify this for sound to work! */
static const CODECTBLLIST codec_tablelist[] =
{
{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 98c64ed..f8271f7 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,7 +32,7 @@
#include <cpu/x86/mtrr.h>
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
-#include "superio/fintek/f81865f/f81865f_early_serial.c"
+#include "superio/fintek/f71869ad/f71869ad.h"
#include "cpu/x86/lapic.h"
#include "drivers/pc80/i8254.c"
#include "drivers/pc80/i8259.c"
@@ -45,7 +46,7 @@
void disable_cache_as_ram(void); /* cache_as_ram.inc */
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
+#define SERIAL_DEV PNP_DEV(0x4e, F71869AD_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -70,7 +71,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init();
post_code(0x31);
- f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}