Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4762
-gerrit
commit f04bd812d75d11f32d2c950a5f1abe0aed431d58
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Mon Jan 20 22:26:05 2014 +0100
Revert "Butterfly, Stout: Force SATA link speed to 3 Gbps"
This reverts commit 7b8952c19d8d809b7aeec629b31e1c3d66f19884.
This commit was a hack to solve potential hangs caused by SSD bugs,
but the workaround limited the SATA speed of all connected drives,
despite the problem being localized to one specific model. As such,
this solution is a layering violation, as it makes too many
assumptions about the connected hardware.
Change-Id: Ia35f7e8a24f9cb701ce0e357d9b3e929c4e0a4fb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/google/butterfly/devicetree.cb | 2 --
src/mainboard/google/stout/devicetree.cb | 2 --
2 files changed, 4 deletions(-)
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 9a7a1d5..c797fb0 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge
# Enable SATA ports 0 & 1
register "sata_port_map" = "0x3"
- # Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_support" = "0x2"
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 653d3fe..a9e499f 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge
register "gpi6_routing" = "2"
register "sata_port_map" = "0x3"
- # Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_support" = "0x2"
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4762
-gerrit
commit 0911dbe254f004dbc7fbb289a006acb38b691079
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Mon Jan 20 22:26:05 2014 +0100
Revert "Butterfly, Stout: Force SATA link speed to 3 Gbps"
This reverts commit 7b8952c19d8d809b7aeec629b31e1c3d66f19884.
This commit was a hack with no real usefulness, as there is no way to
replace the shipping coreboot on a write-protected chromebook. As a
result, this change was inconsequential, and only affects people who
compile and install coreboot post-mortem.
Also, there was no information as to what the commit was supposed to
fix, and as such, it is considered moot.
Change-Id: Ia35f7e8a24f9cb701ce0e357d9b3e929c4e0a4fb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/google/butterfly/devicetree.cb | 2 --
src/mainboard/google/stout/devicetree.cb | 2 --
2 files changed, 4 deletions(-)
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 9a7a1d5..c797fb0 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge
# Enable SATA ports 0 & 1
register "sata_port_map" = "0x3"
- # Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_support" = "0x2"
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 653d3fe..a9e499f 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge
register "gpi6_routing" = "2"
register "sata_port_map" = "0x3"
- # Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_support" = "0x2"
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4762
-gerrit
commit ce74ebf93a65dcee9b6b445cb59071cacbb0c3f5
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Mon Jan 20 22:26:05 2014 +0100
Revert "Butterfly, Stout: Force SATA link speed to 3 Gbps"
This reverts commit 7b8952c19d8d809b7aeec629b31e1c3d66f19884.
This commit was a hack with no real usefulness, as there is no way to
replace the shipping coreboot on a write-protected chromebook. As a
result, this change was irrelevant, and only affects people who
compiled and installed coreboot post-mortem. Kill it.
Change-Id: Ia35f7e8a24f9cb701ce0e357d9b3e929c4e0a4fb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/google/butterfly/devicetree.cb | 5 +----
src/mainboard/google/stout/devicetree.cb | 2 --
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index e7a50c0..ca8118a 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -58,10 +58,7 @@ chip northbridge/intel/sandybridge
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
- # Enable SATA ports 0 & 1
- register "sata_port_map" = "0x3"
- # Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_support" = "0x2"
+ register "sata_port_map" = "0x3" #enable SATA ports 0 & 1
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 6e02020..c58a8d6 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -60,8 +60,6 @@ chip northbridge/intel/sandybridge
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x3"
- # Set max SATA speed to 3.0 Gb/s
- register "sata_interface_speed_support" = "0x2"
# Enable EC Port 0x68/0x6C
register "gen1_dec" = "0x00040069"
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4760
-gerrit
commit 18fae998e4cef652d33b716ab021710a46e9a502
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Mon Jan 20 20:43:25 2014 +0100
asus/a8n-e/board_info.txt: Set ROM Protocol.
Change-Id: I65f2faee672d4d7dea50b67cf6426f503034b380
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/asus/a8n_e/board_info.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/asus/a8n_e/board_info.txt b/src/mainboard/asus/a8n_e/board_info.txt
index bba9585..e86f89b 100644
--- a/src/mainboard/asus/a8n_e/board_info.txt
+++ b/src/mainboard/asus/a8n_e/board_info.txt
@@ -1,5 +1,6 @@
Category: desktop
Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8NE/
ROM package: PLCC
+ROM protocol: LPC
ROM socketed: y
Flashrom support: y
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4650
-gerrit
commit 90dfb69f912d302060730d52c018ab08c5535e78
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Jun 7 02:11:41 2013 +0200
Make version look like something thinkpad_acpi would accept
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.
Not cleaned up as the idea of this patch seems to be met with resistance.
Can make it Thinkpad-specific if the idea is accepted.
Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/arch/x86/boot/smbios.c | 7 +++++--
src/mainboard/lenovo/Kconfig | 4 ++++
src/mainboard/lenovo/x230/board_info.txt | 6 ++++++
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index 65bf538..25bdb37 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -130,12 +130,15 @@ static int smbios_write_type0(unsigned long *current, int handle)
t->vendor = smbios_add_string(t->eos, "coreboot");
#if !CONFIG_CHROMEOS
+#ifndef CONFIG_VENDOR_VERSION
+#define CONFIG_VENDOR_VERSION ""
+#endif
t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
if (strlen(CONFIG_LOCALVERSION))
- t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION CONFIG_LOCALVERSION);
else
- t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+ t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION COREBOOT_VERSION);
#else
#define SPACES \
" "
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index a29fdbf..21413fc 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -41,4 +41,8 @@ config MAINBOARD_VENDOR
string
default "Lenovo"
+config VENDOR_VERSION
+ string
+ default "CBET4000 "
+
endif # VENDOR_LENOVO
diff --git a/src/mainboard/lenovo/x230/board_info.txt b/src/mainboard/lenovo/x230/board_info.txt
new file mode 100644
index 0000000..da3ef07
--- /dev/null
+++ b/src/mainboard/lenovo/x230/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+Board name: X230
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n