coreboot-gerrit September 2013

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Patch set updated for coreboot: f547be0 CBMEM northbridges: Remove references to global high_tables_base
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3561 -gerrit commit f547be0acfd81651f072c201e0e1c0381e41b8b7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 27 08:20:09 2013 +0300 CBMEM northbridges: Remove references to global high_tables_base Use the new helper function set_top_of_ram() to remove remaining uses of high_tables_base and _size under northbridge/. Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 +--- src/northbridge/amd/gx1/northbridge.c | 4 +--- src/northbridge/amd/gx2/northbridge.c | 4 +--- src/northbridge/amd/lx/northbridge.c | 4 +--- src/northbridge/dmp/vortex86ex/northbridge.c | 5 +---- src/northbridge/intel/e7501/northbridge.c | 4 +--- src/northbridge/intel/e7505/northbridge.c | 4 +--- src/northbridge/intel/e7520/northbridge.c | 4 +--- src/northbridge/intel/e7525/northbridge.c | 4 +--- src/northbridge/intel/gm45/northbridge.c | 4 +--- src/northbridge/intel/i3100/northbridge.c | 4 +--- src/northbridge/intel/i440bx/northbridge.c | 4 +--- src/northbridge/intel/i440lx/northbridge.c | 4 +--- src/northbridge/intel/i5000/northbridge.c | 5 +---- src/northbridge/intel/i82810/northbridge.c | 4 +--- src/northbridge/intel/i82830/northbridge.c | 4 +--- src/northbridge/intel/i855/northbridge.c | 4 +--- src/northbridge/intel/i945/northbridge.c | 4 +--- src/northbridge/intel/sandybridge/northbridge.c | 4 +--- src/northbridge/intel/sch/northbridge.c | 6 +----- src/northbridge/rdc/r8610/northbridge.c | 4 +--- src/northbridge/via/cn400/northbridge.c | 5 +---- src/northbridge/via/cn700/northbridge.c | 5 +---- src/northbridge/via/cx700/northbridge.c | 5 +---- src/northbridge/via/vt8601/northbridge.c | 5 +---- src/northbridge/via/vt8623/northbridge.c | 5 +---- src/northbridge/via/vx900/northbridge.c | 6 +----- 27 files changed, 27 insertions(+), 92 deletions(-) diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 2ea4a68..a2cd37b 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -86,9 +86,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) } #if !CONFIG_DYNAMIC_CBMEM - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); #endif if (i440fx) { diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index b895a75..c8f7f94 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -108,9 +108,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 8ebb204..e2f4d11 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -290,9 +290,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */ - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 33387f9..df69b51 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -389,9 +389,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index 5eaaf2a..fcebed8 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -101,10 +101,7 @@ static void pci_domain_set_resources(device_t dev) */ tolmk = tomk; - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk * 1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 551e107..b0b150d 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -84,9 +84,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 5fbc2e4..a63029b 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -85,9 +85,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 57d30fa..c632b2d 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -102,9 +102,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 1865a7c..7625596 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -101,9 +101,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 687479e..afd270f 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -166,9 +166,7 @@ static void mch_domain_read_resources(device_t dev) pcie_config_size >> 10, IORESOURCE_RESERVE); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk << 10) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk << 10); } static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 99a48ba..dcce48d 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -126,9 +126,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tolmk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 7f9e7df..1e6b58e 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -67,9 +67,7 @@ static void i440bx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 2c6866f..ca4ec6e 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -93,9 +93,7 @@ static void i440lx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index 01f150e..c28b0c1 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -111,10 +111,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = tolm - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); + set_top_of_ram(tolm); } static struct pci_operations intel_pci_ops = { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index a98a8d3..2e07db8 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -121,9 +121,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 768, tomk - 768); uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk_stolen * 1024); assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 94a95bc..08ed279 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -90,9 +90,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk_stolen * 1024); } static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 7a0c77c..5c0379c 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -105,9 +105,7 @@ static void pci_domain_set_resources(device_t dev) /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 7e21164..922a819 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -170,9 +170,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk_stolen * 1024); } /* TODO We could determine how many PCIe busses we need in diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index e3290d8..4cd86cd 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -274,9 +274,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } /* TODO We could determine how many PCIe busses we need in diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 600bd13..9dc33f5 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -182,11 +182,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - /* Leave some space for ACPI, PIRQ and MP tables. */ - high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE; - high_tables_base -= uma_memory_size; - high_tables_base -= tseg_memory_base; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024 - uma_memory_size - tseg_memory_base); } /* diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index 92025a0..d69c4f6 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -64,9 +64,7 @@ static void cpu_pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); assign_resources(dev->link_list); } diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 6e01dbb..149eab3 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -204,10 +204,7 @@ static void cn400_domain_set_resources(device_t dev) } /* Locate the High Tables at the Top of Low Memory below the Video RAM */ - high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024); /* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index a7a64a3..a326baf 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -134,10 +134,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram((tolmk - CONFIG_VIDEO_MB * 1024) * 1024); /* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 0fdc5c5..7514ec4 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -68,10 +68,7 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory } - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 77dd9fb..bed434d 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -84,10 +84,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index e70035c..6e0f4ea 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -143,10 +143,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } - high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", - tomk*1024, high_tables_base, high_tables_size); + set_top_of_ram(tolmk * 1024); /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 854e175..25e6045 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -266,11 +266,7 @@ static void vx900_set_resources(device_t dev) u64 tor = vx900_remap_above_4g(mcu, pci_tolm); ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tolmk << 10) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", - high_tables_base, high_tables_size); + set_top_of_ram(tolmk << 10); print_debug("======================================================\n"); assign_resources(dev->link_list);

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Patch set updated for coreboot: 8cd03ec CBMEM AMD: Remove references to global high_tables_base
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3894 -gerrit commit 8cd03ec57f4543b12a2ccf51fb3a40fd10811448 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 27 08:20:09 2013 +0300 CBMEM AMD: Remove references to global high_tables_base Prepare for removal of globals high_tables_base and _size by replacing the references with a helper function. Added set_top_of_ram_once() may be called several times, but only the first call (with non-zero argument) takes effect. Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/Makefile.inc | 1 + src/arch/x86/boot/cbmem.c | 35 ++++++++++++++++++++++ src/include/cbmem.h | 1 + src/northbridge/amd/agesa/family10/northbridge.c | 18 +++-------- src/northbridge/amd/agesa/family12/northbridge.c | 23 +++----------- src/northbridge/amd/agesa/family14/northbridge.c | 22 +++----------- src/northbridge/amd/agesa/family15/northbridge.c | 18 +++-------- src/northbridge/amd/agesa/family15tn/northbridge.c | 18 +++-------- src/northbridge/amd/agesa/family16kb/northbridge.c | 18 +++-------- src/northbridge/amd/amdfam10/northbridge.c | 18 +++-------- src/northbridge/amd/amdk8/northbridge.c | 18 +++-------- 11 files changed, 69 insertions(+), 121 deletions(-) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 7b67e49..9334839 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += boot.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c ramstage-y += tables.c +ramstage-y += cbmem.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c new file mode 100644 index 0000000..888c1f4 --- /dev/null +++ b/src/arch/x86/boot/cbmem.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <console/console.h> +#include <cbmem.h> + +#if !CONFIG_DYNAMIC_CBMEM +/* This is for compatibility with old boards only. Any new chipset and board + * must implement get_top_of_ram() for both romstage and ramstage to support + * features like CAR_MIGRATION and CBMEM_CONSOLE. + */ +void set_top_of_ram_once(uint64_t ramtop) +{ + if (high_tables_base == 0) { + high_tables_base = ramtop - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + } + printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", + high_tables_base, high_tables_size); +} +#endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b241d34..fe960d7 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -136,6 +136,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; +void set_top_of_ram_once(uint64_t ramtop); void set_cbmem_toc(struct cbmem_entry *); #endif diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index ceb1d50..602d473 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1036,17 +1036,11 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -1063,15 +1057,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 621246f..4c230f1 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -722,20 +722,12 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), - high_tables_base); - } } - basek = mmio_basek; } if ((basek + sizek) <= 4*1024*1024) { @@ -751,20 +743,13 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base); + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); - printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", - high_tables_size); #if CONFIG_GFXUMA uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e7de273..fbf8e44 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -716,19 +716,12 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base == 0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } - basek = mmio_basek; } if ((basek + sizek) <= 4 * 1024 * 1024) { @@ -744,20 +737,13 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (high_tables_base == 0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base); + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); - printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", - high_tables_size); #if CONFIG_GFXUMA uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 78e9966..bdd6939 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -807,17 +807,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -834,15 +828,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 0a69ad8..736e634 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -793,17 +793,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -821,15 +815,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index c27a1b2..266319c 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -799,17 +799,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -827,15 +821,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 3f7ca25..8dbb480 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1038,17 +1038,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_MEMORY_SIZE / 1024, high_tables_base); - } } #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1076,15 +1070,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 9610587..c7321a4 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1042,17 +1042,11 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_MEMORY_SIZE / 1024, high_tables_base); - } } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) @@ -1077,15 +1071,11 @@ static void amdk8_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA

1 0

Patch set updated for coreboot: d1b415a CBMEM AMD: Fix calls to set_top_of_ram_once()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3895 -gerrit commit d1b415af98b79c621e75eb3d762b4d483dce80a2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Sep 3 05:25:57 2013 +0300 CBMEM AMD: Fix calls to set_top_of_ram_once() We can postpone the call to set_top_of_ram_once() outside the loops and make just one call instead. As set_top_of_ram() is now only called once, it is no longer necessary to check if high_tables_base was already set. Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 8 +++----- src/include/cbmem.h | 2 +- src/northbridge/amd/agesa/family10/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family12/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family14/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family15/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family15tn/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family16kb/northbridge.c | 18 ++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 19 ++++++++----------- src/northbridge/amd/amdk8/northbridge.c | 18 ++++++++---------- 10 files changed, 68 insertions(+), 87 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 888c1f4..3f738be 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -23,12 +23,10 @@ * must implement get_top_of_ram() for both romstage and ramstage to support * features like CAR_MIGRATION and CBMEM_CONSOLE. */ -void set_top_of_ram_once(uint64_t ramtop) +void set_top_of_ram(uint64_t ramtop) { - if (high_tables_base == 0) { - high_tables_base = ramtop - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - } + high_tables_base = ramtop - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index fe960d7..00d74d6 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -136,7 +136,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; -void set_top_of_ram_once(uint64_t ramtop); +void set_top_of_ram(uint64_t ramtop); void set_cbmem_toc(struct cbmem_entry *); #endif diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 602d473..1c7e547 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -914,6 +914,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1036,11 +1037,8 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -1057,15 +1055,15 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 4c230f1..42b4b3d 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -590,6 +590,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -722,11 +723,8 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -743,16 +741,16 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index fbf8e44..7cc812b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -575,6 +575,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -716,11 +717,8 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -737,16 +735,16 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for (link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index bdd6939..a8cc1cc 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -684,6 +684,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -807,11 +808,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -828,15 +826,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 736e634..b55d52b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -671,6 +671,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -793,11 +794,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -815,15 +813,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 266319c..b8bba50 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -677,6 +677,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -799,11 +800,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -821,15 +819,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8dbb480..6bcab41 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -877,6 +877,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1037,12 +1038,8 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1070,15 +1067,15 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c7321a4..8f0a11b 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -874,6 +874,7 @@ static void amdk8_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; @@ -1042,11 +1043,8 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) @@ -1071,15 +1069,15 @@ static void amdk8_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif assign_resources(dev->link_list);

1 0

Patch set updated for coreboot: 6ad7eda CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3902 -gerrit commit 6ad7edab77122592b757d27aff23868c82925140 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:05:01 2013 +0300 CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base This helper function is for compatibility only for chipsets that do not implement get_top_of_ram() to support early CBMEM. Also remove references to globals high_tables_base and _size under arch/ and from two ARMv7 boards. Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/tables.c | 7 ------- src/arch/x86/boot/cbmem.c | 5 +---- src/arch/x86/boot/tables.c | 2 -- src/include/cbmem.h | 1 + src/lib/cbmem.c | 10 ++++++++++ src/mainboard/google/pit/mainboard.c | 17 +++++++++++------ src/mainboard/google/snow/mainboard.c | 17 +++++++++++------ 7 files changed, 34 insertions(+), 25 deletions(-) diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index 0fc7399..0f174d3 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -29,13 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -/* - * TODO: "High" tables are a convention used on x86. Maybe we can - * clean up that naming at some point. - */ -uint64_t high_tables_base = 0; -uint64_t high_tables_size; - void cbmem_arch_init(void) { } diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 3f738be..6ec005d 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -25,9 +25,6 @@ */ void set_top_of_ram(uint64_t ramtop) { - high_tables_base = ramtop - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", - high_tables_base, high_tables_size); + cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } #endif diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 67d7911..81d5453 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -32,8 +32,6 @@ #include <lib.h> #include <smbios.h> -uint64_t high_tables_base = 0; -uint64_t high_tables_size; void cbmem_arch_init(void) { diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 00d74d6..3d04763 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -137,6 +137,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); +void cbmem_late_set_table(uint64_t base, uint64_t size); void set_cbmem_toc(struct cbmem_entry *); #endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 9e2ce0d..206fdbf 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -42,6 +42,8 @@ struct cbmem_entry { } __attribute__((packed)); #ifndef __PRE_RAM__ +uint64_t high_tables_base = 0; +uint64_t high_tables_size = 0; static struct cbmem_entry *bss_cbmem_toc; struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) @@ -60,7 +62,15 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); return NULL; } +#endif +#if !defined(__PRE_RAM__) +void cbmem_late_set_table(uint64_t base, uint64_t size) +{ + printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", base, base+size-1, __FUNCTION__); + high_tables_base = base; + high_tables_size = size; +} #endif /** diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 54ea042..7dd8388 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -221,17 +221,22 @@ static void mainboard_init(device_t dev) // gpio_info(); } +static void setup_cbmem(void) +{ + u64 size = CONFIG_COREBOOT_TABLES_SIZE; + u64 base = CONFIG_SYS_SDRAM_BASE + + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + cbmem_late_set_table(base, size); + cbmem_init(base, size); +} + static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); + setup_cbmem(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 5aedac9..8805be5 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -262,17 +262,22 @@ static void mainboard_init(device_t dev) // gpio_info(); } +static void setup_cbmem(void) +{ + u64 size = CONFIG_COREBOOT_TABLES_SIZE; + u64 base = CONFIG_SYS_SDRAM_BASE + + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + cbmem_late_set_table(base, size); + cbmem_init(base, size); +} + static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); + setup_cbmem(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */

1 0

Patch set updated for coreboot: 2e0573a CBMEM tables: Remove references to global high_tables_base
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3559 -gerrit commit 2e0573abfa7a815365246e0f6105c90f76ea59d8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 14:11:08 2013 +0300 CBMEM tables: Remove references to global high_tables_base Unify checks and writing of CBMEM tables for x86 and ARMv7. Change-Id: I89c012bce1b86d0710748719a8840ec532ce6939 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/tables.c | 6 +----- src/arch/x86/boot/tables.c | 19 +++++++++++-------- src/include/cbmem.h | 9 ++++----- src/lib/cbmem.c | 17 +++++++++++++++++ src/lib/coreboot_table.c | 5 ----- 5 files changed, 33 insertions(+), 23 deletions(-) diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index 0f174d3..de6b6fa 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -37,11 +37,7 @@ struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer; - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); - } - - printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); + cbmem_base_check(); post_code(0x9d); diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 81d5453..970bd40 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -51,13 +51,7 @@ struct lb_memory *write_tables(void) unsigned long high_table_pointer; #if !CONFIG_DYNAMIC_CBMEM - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); - // Are there any boards without? - // Stepan thinks we should die() here! - } - - printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); + cbmem_base_check(); #endif rom_table_start = 0xf0000; @@ -225,9 +219,18 @@ struct lb_memory *write_tables(void) if (high_table_pointer) { unsigned long new_high_table_pointer; + /* FIXME: The high_table_base parameter is not reference when tables are high, + * or high_table_pointer >1 MB. + */ +#if !CONFIG_DYNAMIC_CBMEM + u64 high_table_base = (u32)get_cbmem_toc(); +#else + u64 high_table_base = 0; +#endif + /* Also put a forwarder entry into 0-4K */ new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, - high_tables_base, high_table_pointer); + high_table_base, high_table_pointer); if (new_high_table_pointer > (high_table_pointer + MAX_COREBOOT_TABLE_SIZE)) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 3d04763..d81335f 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -126,11 +126,6 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); -#ifndef __PRE_RAM__ -/* Add the cbmem memory used to the memory tables. */ -struct lb_memory; -void cbmem_add_lb_mem(struct lb_memory *mem); -#endif /* __PRE_RAM__ */ #else /* !CONFIG_DYNAMIC_CBMEM */ @@ -139,6 +134,7 @@ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); void set_cbmem_toc(struct cbmem_entry *); +int cbmem_base_check(void); #endif void cbmem_init(u64 baseaddr, u64 size); @@ -162,6 +158,9 @@ void *cbmem_find(u32 id); #ifndef __PRE_RAM__ /* Ramstage only functions. */ +/* Add the cbmem memory used to the memory tables. */ +struct lb_memory; +void cbmem_add_lb_mem(struct lb_memory *mem); void cbmem_list(void); void cbmem_arch_init(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 206fdbf..32a4614 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -21,6 +21,7 @@ #include <string.h> #include <bootstate.h> #include <cbmem.h> +#include <boot/coreboot_tables.h> #include <console/console.h> #include <cpu/x86/car.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) @@ -260,6 +261,22 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_post_device, NULL), }; +int cbmem_base_check(void) +{ + if (!high_tables_base) { + printk(BIOS_ERR, "ERROR: CBMEM Base is not set.\n"); + // Are there any boards without? + // Stepan thinks we should die() here! + } + printk(BIOS_DEBUG, "CBMEM Base is %llx.\n", high_tables_base); + return !!high_tables_base; +} + +void cbmem_add_lb_mem(struct lb_memory *mem) +{ + lb_add_memory_range(mem, LB_MEM_TABLE, high_tables_base, high_tables_size); +} + void cbmem_list(void) { struct cbmem_entry *cbmem_toc; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3fad4c7..e5729ba 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -539,12 +539,7 @@ unsigned long write_coreboot_table( lb_add_memory_range(mem, LB_MEM_TABLE, rom_table_start, rom_table_end - rom_table_start); -#if CONFIG_DYNAMIC_CBMEM cbmem_add_lb_mem(mem); -#else /* CONFIG_DYNAMIC_CBMEM */ - lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); -#endif /* CONFIG_DYNAMIC_CBMEM */ /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */

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Patch merged into coreboot/master: 0306b50 usbdebug: Fixes for LynxPoint LP
by gerrit＠coreboot.org 06 Sep '13

06 Sep '13

the following patch was just integrated into master: commit 0306b502804ead6f56ad9dee814d0bc5062870f7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Aug 13 09:10:31 2013 +0300 usbdebug: Fixes for LynxPoint LP Keep the EHCI BAR unchanged to keep usbdebug working. Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3477 for details. -gerrit

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Patch merged into coreboot/master: 690bf2f usbdebug: Use CAR migration
by gerrit＠coreboot.org 06 Sep '13

06 Sep '13

the following patch was just integrated into master: commit 690bf2f333322e764262e60fd24802205280df5e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jul 6 11:41:21 2013 +0300 usbdebug: Use CAR migration If we already initialized EHCI controller and USB device in romstage, locate active configuration from salvaged CAR_GLOBAL and avoid doing the hardware initialisation again. Change-Id: I7cb3a359488b25abc9de49c96c0197f6563a4a2c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3476 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3476 for details. -gerrit

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Patch merged into coreboot/master: e53cece usbdebug: Dump low-level protocol details
by gerrit＠coreboot.org 06 Sep '13

06 Sep '13

the following patch was just integrated into master: commit e53cece07b14eab1912db3d18d2cb50423d996ec Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Aug 10 10:50:43 2013 +0300 usbdebug: Dump low-level protocol details Dumping these EHCI host controller registers is useful to solve problems with debug devices. Change-Id: I0610cecca57b1b952d4f87211dd00c8c0bc398b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3866 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3866 for details. -gerrit

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Patch merged into coreboot/master: 5c87d2f usbdebug: Adjust endpoint retry timeouts
by gerrit＠coreboot.org 06 Sep '13

06 Sep '13

the following patch was just integrated into master: commit 5c87d2f17e162c40b9f43415ccc049ef482f9336 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Aug 19 12:45:16 2013 +0300 usbdebug: Adjust endpoint retry timeouts Change Setup Stage of control messages to have no retries, while data and status stages may retry until timing out after 1000 retries. The correct amount of retries might vary by endpoint and device dongle used, so make it a variable. Change-Id: I63313f994d0bd3444a3aab527ca942da5de9e6fa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3882 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3882 for details. -gerrit

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Patch merged into coreboot/master: 2de841b usbdebug: Adjust transaction retries
by gerrit＠coreboot.org 06 Sep '13

06 Sep '13

the following patch was just integrated into master: commit 2de841b355f632bd4cee3f0419dab34ec57ad804 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Aug 19 12:45:16 2013 +0300 usbdebug: Adjust transaction retries Transaction consistently completes with 80 to 150 status reads on my setups. Hardware should always be able to complete this within 125us as the debug port is serviced at the beginning of each microframe. Timeout is set to DBGP_MICROFRAME_TIMEOUT_LOOPS=1000 status reads. Do not retry transactions if this timeout is reached as the host controller probably needs full re-initialisation to recover. If this timeout is not reached, but a transaction is corrupted on the wire, or it is otherwise not properly delivered to the USB device, transaction is retried upto DBGP_MICROFRAME_RETRIES=10 times. Change-Id: I44bc0a1bd194cdb5a2c13d5b81fc39bc568ae054 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3881 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3881 for details. -gerrit

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coreboot-gerrit September 2013