coreboot-gerrit September 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 0e89bc3 timestamps intel: Move timestamp scratchpad to chipset
by Kyösti Mälkki 08 Sep '13

08 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3908 -gerrit commit 0e89bc3663f48d48abe971077ae239ea7e87a1e2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Sep 7 11:38:56 2013 +0300 timestamps intel: Move timestamp scratchpad to chipset This retrieves back the value stored with store_initial_timestamp() in the bootblock for southbridge. Change-Id: I377c823706c33ed65af023d20d2e4323edd31199 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/haswell/romstage.c | 5 +---- src/include/timestamp.h | 1 + src/mainboard/google/butterfly/romstage.c | 5 +---- src/mainboard/google/link/romstage.c | 5 +---- src/mainboard/google/parrot/romstage.c | 5 +---- src/mainboard/google/stout/romstage.c | 5 +---- src/mainboard/intel/emeraldlake2/romstage.c | 5 +---- src/mainboard/kontron/ktqm77/romstage.c | 5 +---- src/mainboard/lenovo/t60/romstage.c | 5 +---- src/mainboard/lenovo/x60/romstage.c | 5 +---- src/mainboard/samsung/lumpy/romstage.c | 5 +---- src/mainboard/samsung/stumpy/romstage.c | 5 +---- src/southbridge/intel/bd82x6x/Makefile.inc | 2 +- src/southbridge/intel/bd82x6x/early_pch.c | 33 +++++++++++++++++++++++++++++ src/southbridge/intel/i82801gx/Makefile.inc | 3 +-- src/southbridge/intel/i82801gx/early_lpc.c | 33 +++++++++++++++++++++++++++++ src/southbridge/intel/lynxpoint/early_pch.c | 12 +++++++++++ 17 files changed, 92 insertions(+), 47 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 0cef888..06e3a85 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -204,10 +204,7 @@ void romstage_common(const struct romstage_params *params) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif #if CONFIG_COLLECT_TIMESTAMPS diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 9dd0d0f..2a39b97 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -61,6 +61,7 @@ void timestamp_add(enum timestamp_id id, tsc_t ts_time); void timestamp_add_now(enum timestamp_id id); void timestamp_stash(enum timestamp_id id); void timestamp_sync(void); +tsc_t get_initial_timestamp(void); #else #define timestamp_init(base) #define timestamp_add(id, time) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 5e2b713..554df83 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -122,10 +122,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif struct pei_data pei_data = { pei_version: PEI_VERSION, diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index f20a722..ad4da84 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -158,10 +158,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif struct pei_data pei_data = { pei_version: PEI_VERSION, diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 9968226..79f9c2a 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -123,10 +123,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif struct pei_data pei_data = { pei_version: PEI_VERSION, diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 14820dd..80de53d 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -162,10 +162,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif struct pei_data pei_data = { pei_version: PEI_VERSION, diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 88bcced..bb47cb8 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -174,10 +174,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif struct pei_data pei_data = { pei_version: PEI_VERSION, diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 79fafe0..f78e293 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -160,10 +160,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif struct pei_data pei_data = { pei_version: PEI_VERSION, diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 5bb7ac1..79a2988 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -216,10 +216,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif #if CONFIG_COLLECT_TIMESTAMPS diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 4d0eac7..ec4c00c 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -223,10 +223,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif #if CONFIG_COLLECT_TIMESTAMPS diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 449a81c..1a17949 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -141,10 +141,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif struct pei_data pei_data = { pei_version: PEI_VERSION, diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index daa8d55..1169732 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -177,10 +177,7 @@ void main(unsigned long bist) tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; + tsc_t base_time = get_initial_timestamp(); #endif struct pei_data pei_data = { pei_version: PEI_VERSION, diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index ffd8943..8abc56a 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -47,7 +47,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c romstage-y += reset.c -romstage-y += early_spi.c +romstage-y += early_spi.c early_pch.c ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c new file mode 100644 index 0000000..9f80d41 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <timestamp.h> + +#if CONFIG_COLLECT_TIMESTAMPS +tsc_t get_initial_timestamp(void) +{ + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; + return base_time; +} +#endif diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index ff9fbee..94c84ed 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -36,5 +36,4 @@ ramstage-y += watchdog.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -romstage-y += early_smbus.c - +romstage-y += early_smbus.c early_lpc.c diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c new file mode 100644 index 0000000..9f80d41 --- /dev/null +++ b/src/southbridge/intel/i82801gx/early_lpc.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <timestamp.h> + +#if CONFIG_COLLECT_TIMESTAMPS +tsc_t get_initial_timestamp(void) +{ + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; + return base_time; +} +#endif diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index a390d73..1a78d57 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <arch/io.h> #include <device/pci_def.h> +#include <timestamp.h> #include <elog.h> #include "pch.h" @@ -62,6 +63,17 @@ static void pch_generic_setup(void) printk(BIOS_DEBUG, " done.\n"); } +#if CONFIG_COLLECT_TIMESTAMPS +tsc_t get_initial_timestamp(void) +{ + tsc_t base_time = { + .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), + .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) + }; + return base_time; +} +#endif + static int sleep_type_s3(void) { u32 pm1_cnt;

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Patch set updated for coreboot: 6de6b09 CBMEM ARM: Prefer get_cbmem_table() over cbmem_late_set_table()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3560 -gerrit commit 6de6b0961613e743c17035a6eec123013a21fd9e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 22 14:05:28 2013 +0300 CBMEM ARM: Prefer get_cbmem_table() over cbmem_late_set_table() Implementing get_cbmem_table() allows initializing CBMEM earlier. Change-Id: I973f3a84dd9aaa2839959df5dda22909fdb9edeb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/pit/mainboard.c | 10 ++++------ src/mainboard/google/snow/mainboard.c | 10 ++++------ 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 7dd8388..b91040c 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -221,14 +221,12 @@ static void mainboard_init(device_t dev) // gpio_info(); } -static void setup_cbmem(void) +void get_cbmem_table(uint64_t *base, uint64_t *size) { - u64 size = CONFIG_COREBOOT_TABLES_SIZE; - u64 base = CONFIG_SYS_SDRAM_BASE + + *size = CONFIG_COREBOOT_TABLES_SIZE; + *base = CONFIG_SYS_SDRAM_BASE + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_late_set_table(base, size); - cbmem_init(base, size); } static void mainboard_enable(device_t dev) @@ -236,7 +234,7 @@ static void mainboard_enable(device_t dev) dev->ops->init = &mainboard_init; /* set up coreboot tables */ - setup_cbmem(); + cbmem_initialize(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 8805be5..93cc303 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -262,14 +262,12 @@ static void mainboard_init(device_t dev) // gpio_info(); } -static void setup_cbmem(void) +void get_cbmem_table(uint64_t *base, uint64_t *size) { - u64 size = CONFIG_COREBOOT_TABLES_SIZE; - u64 base = CONFIG_SYS_SDRAM_BASE + + *size = CONFIG_COREBOOT_TABLES_SIZE; + *base = CONFIG_SYS_SDRAM_BASE + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_late_set_table(base, size); - cbmem_init(base, size); } static void mainboard_enable(device_t dev) @@ -277,7 +275,7 @@ static void mainboard_enable(device_t dev) dev->ops->init = &mainboard_init; /* set up coreboot tables */ - setup_cbmem(); + cbmem_initialize(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */

1 0

Patch set updated for coreboot: 6909ff6 CBMEM: Drop parameter from cbmem_reinit()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3564 -gerrit commit 6909ff6c268e2ba1fa08923ec924b6d82234a581 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 23 17:01:29 2013 +0300 CBMEM: Drop parameter from cbmem_reinit() Function is always called with get_top_of_ram() - HIGH_MEMORY_SIZE which equals cbmem_base, thus no need to pass it as a parameter. Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 11 +---------- src/cpu/amd/car/post_cache_as_ram.c | 9 +-------- src/include/cbmem.h | 2 +- src/lib/cbmem.c | 14 +++++++------- src/mainboard/getac/p470/romstage.c | 5 +---- src/mainboard/google/stout/romstage.c | 3 +-- src/mainboard/ibase/mb899/romstage.c | 5 +---- src/mainboard/intel/d945gclf/romstage.c | 5 +---- src/mainboard/kontron/986lcd-m/romstage.c | 5 +---- src/mainboard/roda/rk886ex/romstage.c | 5 +---- src/mainboard/roda/rk9/romstage.c | 5 +---- 11 files changed, 17 insertions(+), 52 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index fcc1604..ef19b53 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -109,18 +109,9 @@ void restore_mtrr(void) inline void *backup_resume(void) { - unsigned long high_ram_base; void *resume_backup_memory; - /* Start address of high memory tables */ - high_ram_base = (u32) get_cbmem_toc(); - - /* - * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); - * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); - */ - - if (!cbmem_reinit((u64)high_ram_base)) + if (!cbmem_reinit()) return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index d20c393..eca7673 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -32,20 +32,13 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi #if CONFIG_HAVE_ACPI_RESUME static inline void *backup_resume(void) { - unsigned long high_ram_base; void *resume_backup_memory; int suspend = acpi_is_wakeup_early(); if (!suspend) return NULL; - /* Start address of high memory tables */ - high_ram_base = (u32) get_cbmem_toc(); - - print_debug_pcar("CBMEM TOC is at: ", (uint32_t)high_ram_base); - print_debug_pcar("CBMEM TOC 0-size: ",(uint32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); - - if (!cbmem_reinit((u64)high_ram_base)) + if (!cbmem_reinit()) return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 00998f3..04ecde2 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -138,7 +138,7 @@ int cbmem_base_check(void); #endif void cbmem_init(u64 baseaddr, u64 size); -int cbmem_reinit(u64 baseaddr); +int cbmem_reinit(void); void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 2307054..d7f866b 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -47,7 +47,6 @@ uint64_t high_tables_base = 0; uint64_t high_tables_size = 0; #endif -#if !defined(__PRE_RAM__) static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) { if (base && size && s) { @@ -55,7 +54,6 @@ static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) base, base + size - 1, s); } } -#endif static void cbmem_locate_table(uint64_t *base, uint64_t *size) { @@ -120,13 +118,15 @@ void cbmem_init(u64 baseaddr, u64 size) }; } -int cbmem_reinit(u64 baseaddr) +int cbmem_reinit(void) { + uint64_t baseaddr, size; struct cbmem_entry *cbmem_toc; - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - printk(BIOS_DEBUG, "Re-Initializing CBMEM area to 0x%lx\n", - (unsigned long)baseaddr); + cbmem_locate_table(&baseaddr, &size); + cbmem_trace_location(baseaddr, size, __FUNCTION__); + + cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; return (cbmem_toc[0].magic == CBMEM_MAGIC); } @@ -226,7 +226,7 @@ int cbmem_initialize(void) cbmem_locate_table(&base, &size); /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit(base)) { + if (!cbmem_reinit()) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) /* Something went wrong, our high memory area got wiped */ if (acpi_slp_type == 3 || acpi_slp_type == 2) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 90d38eb..f4e43e5 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -358,13 +358,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 14820dd..83be94e 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -313,8 +313,7 @@ void main(unsigned long bist) #if CONFIG_EARLY_CBMEM_INIT cbmem_was_initted = !cbmem_initialize(); #else - cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() - - HIGH_MEMORY_SIZE)); + cbmem_was_initted = cbmem_reinit(); #endif #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 79eaa0b..b059a57 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -312,13 +312,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index a37f605..248aa3b 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -270,13 +270,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 03b24d8..324f442 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -411,13 +411,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index ab200d2..cb141f9 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -347,13 +347,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 56eea84..075790d 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -184,13 +184,10 @@ void main(unsigned long bist) init_iommu(); #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_reinit((u64)high_ram_base)) { + if (s3resume && cbmem_reinit() { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

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Patch set updated for coreboot: d73f8ba CBMEM: Drop parameters from cbmem_init()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3565 -gerrit commit d73f8bacafcc00606138498e0af256cf25f545ca Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 14:36:31 2013 +0300 CBMEM: Drop parameters from cbmem_init() The parameters can be dropped as initialisation always happens for the region resolved with cbmem_locate_table(). This is no longer referenced externally, make it static. Change-Id: Ia40350a5232dcbf30aca7b5998e7995114c44551 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 1 - src/lib/cbmem.c | 17 +++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 04ecde2..83ccd1b 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -137,7 +137,6 @@ void cbmem_late_set_table(uint64_t base, uint64_t size); int cbmem_base_check(void); #endif -void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(void); void get_cbmem_table(uint64_t *base, uint64_t *size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index d7f866b..a394f31 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -95,13 +95,16 @@ void cbmem_late_set_table(uint64_t base, uint64_t size) * - suspend/resume backup memory */ -void cbmem_init(u64 baseaddr, u64 size) +#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) +static void cbmem_init(void) { + uint64_t baseaddr, size; struct cbmem_entry *cbmem_toc; - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", - baseaddr, size); + cbmem_locate_table(&baseaddr, &size); + cbmem_trace_location(baseaddr, size, __FUNCTION__); + + cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; if (size < (64 * 1024)) { printk(BIOS_DEBUG, "Increase CBMEM size!\n"); @@ -117,6 +120,7 @@ void cbmem_init(u64 baseaddr, u64 size) .size = size - CBMEM_TOC_RESERVED }; } +#endif int cbmem_reinit(void) { @@ -220,11 +224,8 @@ void *cbmem_find(u32 id) /* Returns True if it was not initialized before. */ int cbmem_initialize(void) { - uint64_t base = 0, size = 0; int rv = 0; - cbmem_locate_table(&base, &size); - /* We expect the romstage to always initialize it. */ if (!cbmem_reinit()) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) @@ -232,7 +233,7 @@ int cbmem_initialize(void) if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; #endif - cbmem_init(base, size); + cbmem_init(); rv = 1; } #ifndef __PRE_RAM__

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Patch set updated for coreboot: bae7405 CBMEM: Rename high_tables variables and make them static
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3906 -gerrit commit bae7405f3563bbcf4ff5da3383d903a9d868adfe Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 23 20:03:50 2013 +0300 CBMEM: Rename high_tables variables and make them static Old name was too much x86. All external references have been removed. Change-Id: I982b9abfcee57a7ea421c245dadb84342949efae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 1 - src/lib/cbmem.c | 26 +++++++++++++------------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 83ccd1b..b3d3fff 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -130,7 +130,6 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry); #else /* !CONFIG_DYNAMIC_CBMEM */ #ifndef __PRE_RAM__ -extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index a394f31..495ee5a 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -43,8 +43,8 @@ struct cbmem_entry { } __attribute__((packed)); #ifndef __PRE_RAM__ -uint64_t high_tables_base = 0; -uint64_t high_tables_size = 0; +static uint64_t cbmem_base = 0; +static uint64_t cbmem_size = 0; #endif static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) @@ -60,12 +60,12 @@ static void cbmem_locate_table(uint64_t *base, uint64_t *size) #ifdef __PRE_RAM__ get_cbmem_table(base, size); #else - if (!(high_tables_base && high_tables_size)) { - get_cbmem_table(&high_tables_base, &high_tables_size); - cbmem_trace_location(high_tables_base, high_tables_size, __FUNCTION__); + if (!(cbmem_base && cbmem_size)) { + get_cbmem_table(&cbmem_base, &cbmem_size); + cbmem_trace_location(cbmem_base, cbmem_size, __FUNCTION__); } - *base = high_tables_base; - *size = high_tables_size; + *base = cbmem_base; + *size = cbmem_size; #endif } @@ -80,8 +80,8 @@ struct cbmem_entry *get_cbmem_toc(void) void cbmem_late_set_table(uint64_t base, uint64_t size) { cbmem_trace_location(base, size, __FUNCTION__); - high_tables_base = base; - high_tables_size = size; + cbmem_base = base; + cbmem_size = size; } #endif @@ -262,18 +262,18 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { int cbmem_base_check(void) { - if (!high_tables_base) { + if (!cbmem_base) { printk(BIOS_ERR, "ERROR: CBMEM Base is not set.\n"); // Are there any boards without? // Stepan thinks we should die() here! } - printk(BIOS_DEBUG, "CBMEM Base is %llx.\n", high_tables_base); - return !!high_tables_base; + printk(BIOS_DEBUG, "CBMEM Base is %llx.\n", cbmem_base); + return !!cbmem_base; } void cbmem_add_lb_mem(struct lb_memory *mem) { - lb_add_memory_range(mem, LB_MEM_TABLE, high_tables_base, high_tables_size); + lb_add_memory_range(mem, LB_MEM_TABLE, cbmem_base, cbmem_size); } void cbmem_list(void)

1 0

Patch set updated for coreboot: 820412a CBMEM x86: Unify get_cbmem_toc()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3907 -gerrit commit 820412abe5df0a6ba0ec9817d6b93a274236e450 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Sep 6 10:46:22 2013 +0300 CBMEM x86: Unify get_cbmem_toc() Remove any chipset-specific implementations and use arch-specific implementation of get_cbmem_table() instead. Change-Id: I338ee2c1bd51f5e517462115170dc926e040159e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 2 +- src/lib/cbmem.c | 2 +- src/mainboard/emulation/qemu-i440fx/memory.c | 7 +------ src/northbridge/intel/i945/raminit.c | 5 ----- src/northbridge/intel/sandybridge/northbridge.c | 8 -------- src/northbridge/intel/sandybridge/raminit.c | 5 ----- src/northbridge/via/vx900/early_vx900.c | 5 ----- 7 files changed, 3 insertions(+), 31 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index bbdfe38..00998f3 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -141,7 +141,7 @@ void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); void get_cbmem_table(uint64_t *base, uint64_t *size); -extern struct cbmem_entry *get_cbmem_toc(void); +struct cbmem_entry *get_cbmem_toc(void); #endif /* CONFIG_DYNAMIC_CBMEM */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index b6751de..2307054 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -71,7 +71,7 @@ static void cbmem_locate_table(uint64_t *base, uint64_t *size) #endif } -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +struct cbmem_entry *get_cbmem_toc(void) { uint64_t base, size; cbmem_locate_table(&base, &size); diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 08077e9..027deb9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -45,12 +45,7 @@ unsigned long get_top_of_ram(void) return qemu_get_memory_size() * 1024; } -#if !CONFIG_DYNAMIC_CBMEM -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} -#else +#if CONFIG_DYNAMIC_CBMEM void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1a0684..b50f1d8 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,11 +28,6 @@ #include "i945.h" #include <cbmem.h> -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4abcec3..a03b8a6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -58,14 +58,6 @@ unsigned long get_top_of_ram(void) return (unsigned long) tom; } -struct cbmem_entry *get_cbmem_toc(void) -{ - static struct cbmem_entry *toc = NULL; - if (!toc) - toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); - return toc; -} - /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3eb2fb3..3b321d7 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -305,11 +305,6 @@ void sdram_initialize(struct pei_data *pei_data) save_mrc_data(pei_data); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 2439c8d..2896680 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -27,11 +27,6 @@ unsigned long get_top_of_ram(void) return (((unsigned long)reg_tom) << 24) - (256 << 20); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /** * \brief Enable accessing of PCI configuration space for all devices. *

1 0

Patch set updated for coreboot: d611103 CBMEM: Add cbmem_locate_table()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3558 -gerrit commit d61110378f3e3a5ffbee36415127e3f60c27985f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:31:39 2013 +0300 CBMEM: Add cbmem_locate_table() For both romstage and ramstage, this calls an arch-specific function get_cbmem_table() to resolve the base and size of CBMEM region. In ramstage, the result is cached as the query may be relatively slow involving multiple PCI configuration reads. For x86 CBMEM tables are located right below top of low ram and have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation. Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/tables.c | 7 ++++++ src/arch/x86/boot/Makefile.inc | 2 ++ src/arch/x86/boot/cbmem.c | 21 +++++++++++++++++ src/include/cbmem.h | 1 + src/lib/cbmem.c | 52 +++++++++++++++++++++++------------------- 5 files changed, 60 insertions(+), 23 deletions(-) diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index de6b6fa..b566ff6 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -29,6 +29,13 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) +void __attribute__((weak)) get_cbmem_table(uint64_t *base, uint64_t *size) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_table for your board\n"); + *base = 0; + *size = 0; +} + void cbmem_arch_init(void) { } diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 9334839..d3a5f21 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,3 +1,5 @@ +romstage-y += cbmem.c + ramstage-y += boot.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 6ec005d..333ca55 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -18,7 +18,28 @@ #include <console/console.h> #include <cbmem.h> +unsigned long __attribute__((weak)) get_top_of_ram(void) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); + return 0; +} + #if !CONFIG_DYNAMIC_CBMEM +void get_cbmem_table(uint64_t *base, uint64_t *size) +{ + uint64_t top_of_ram = get_top_of_ram(); + + if (top_of_ram >= HIGH_MEMORY_SIZE) { + *base = top_of_ram - HIGH_MEMORY_SIZE; + *size = HIGH_MEMORY_SIZE; + } else { + *base = 0; + *size = 0; + } +} +#endif + +#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) /* This is for compatibility with old boards only. Any new chipset and board * must implement get_top_of_ram() for both romstage and ramstage to support * features like CAR_MIGRATION and CBMEM_CONSOLE. diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 96b9da8..4ee0b2e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -140,6 +140,7 @@ int cbmem_base_check(void); void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); +void get_cbmem_table(uint64_t *base, uint64_t *size); extern struct cbmem_entry *get_cbmem_toc(void); #endif /* CONFIG_DYNAMIC_CBMEM */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 41d80b8..c5a11e3 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -45,30 +45,46 @@ struct cbmem_entry { #ifndef __PRE_RAM__ uint64_t high_tables_base = 0; uint64_t high_tables_size = 0; -static struct cbmem_entry *bss_cbmem_toc; -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) { - return bss_cbmem_toc; + /* do nothing, this should be called by chipset to save TOC in NVRAM */ } -void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) +static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) { - /* do nothing, this should be called by chipset to save TOC in NVRAM */ + if (base && size && s) { + printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", + base, base + size - 1, s); + } } +#endif + +static void cbmem_locate_table(uint64_t *base, uint64_t *size) +{ +#ifdef __PRE_RAM__ + get_cbmem_table(base, size); #else + if (!(high_tables_base && high_tables_size)) { + get_cbmem_table(&high_tables_base, &high_tables_size); + cbmem_trace_location(high_tables_base, high_tables_size, __FUNCTION__); + } + *base = high_tables_base; + *size = high_tables_size; +#endif +} struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) { - printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); - return NULL; + uint64_t base, size; + cbmem_locate_table(&base, &size); + return (struct cbmem_entry *)(unsigned long)base; } -#endif #if !defined(__PRE_RAM__) void cbmem_late_set_table(uint64_t base, uint64_t size) { - printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", base, base+size-1, __FUNCTION__); + cbmem_trace_location(base, size, __FUNCTION__); high_tables_base = base; high_tables_size = size; } @@ -89,10 +105,6 @@ void cbmem_init(u64 baseaddr, u64 size) struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); @@ -123,10 +135,6 @@ int cbmem_reinit(u64 baseaddr) printk(BIOS_DEBUG, "Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - return (cbmem_toc[0].magic == CBMEM_MAGIC); } @@ -219,21 +227,19 @@ void *cbmem_find(u32 id) /* Returns True if it was not initialized before. */ int cbmem_initialize(void) { + uint64_t base = 0, size = 0; int rv = 0; -#ifdef __PRE_RAM__ - uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - uint64_t high_tables_size = HIGH_MEMORY_SIZE; -#endif + cbmem_locate_table(&base, &size); /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit(high_tables_base)) { + if (!cbmem_reinit(base)) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) /* Something went wrong, our high memory area got wiped */ if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; #endif - cbmem_init(high_tables_base, high_tables_size); + cbmem_init(base, size); rv = 1; } #ifndef __PRE_RAM__

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Patch set updated for coreboot: 16b0462 CBMEM: Backup top_of_ram instead of cbmem_toc
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3557 -gerrit commit 16b0462cbc94cfa34a74b266c0bfee5f4bace502 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:26:11 2013 +0300 CBMEM: Backup top_of_ram instead of cbmem_toc AMD northbridges have a complex way to resolve top_of_ram. Once it is resolved, it is stored in NVRAM to be used on resume. TODO: Redesign these get_top_of_ram() functions from scratch. Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 6 ++++++ src/cpu/amd/agesa/s3_resume.c | 3 ++- src/cpu/amd/car/post_cache_as_ram.c | 3 ++- src/include/cbmem.h | 2 +- src/lib/cbmem.c | 11 ++--------- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.c | 13 ++++++++----- src/southbridge/amd/cimx/sb700/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb800/cfg.c | 12 ++++++++---- src/southbridge/amd/sb700/early_setup.c | 8 +++++--- src/southbridge/amd/sb700/lpc.c | 4 ++-- src/southbridge/amd/sb800/early_setup.c | 8 +++++--- src/southbridge/via/k8t890/early_car.c | 9 +++++++-- src/southbridge/via/k8t890/host_ctrl.c | 9 ++------- src/southbridge/via/k8t890/k8t890.h | 2 +- 15 files changed, 55 insertions(+), 43 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 333ca55..991a3e6 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -40,12 +40,18 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) #endif #if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) +void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) +{ + /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ +} + /* This is for compatibility with old boards only. Any new chipset and board * must implement get_top_of_ram() for both romstage and ramstage to support * features like CAR_MIGRATION and CBMEM_CONSOLE. */ void set_top_of_ram(uint64_t ramtop) { + backup_top_of_ram(ramtop); cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } #endif diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6ba9212..fcc1604 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -120,7 +120,8 @@ inline void *backup_resume(void) * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); */ - cbmem_reinit((u64) high_ram_base); + if (!cbmem_reinit((u64)high_ram_base)) + return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (((u32) resume_backup_memory == 0) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 18c278e..d20c393 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -45,7 +45,8 @@ static inline void *backup_resume(void) { print_debug_pcar("CBMEM TOC is at: ", (uint32_t)high_ram_base); print_debug_pcar("CBMEM TOC 0-size: ",(uint32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); - cbmem_reinit((u64)high_ram_base); + if (!cbmem_reinit((u64)high_ram_base)) + return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4ee0b2e..bbdfe38 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -132,8 +132,8 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); +void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); -void set_cbmem_toc(struct cbmem_entry *); int cbmem_base_check(void); #endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index c5a11e3..b6751de 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -45,12 +45,9 @@ struct cbmem_entry { #ifndef __PRE_RAM__ uint64_t high_tables_base = 0; uint64_t high_tables_size = 0; +#endif -void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) -{ - /* do nothing, this should be called by chipset to save TOC in NVRAM */ -} - +#if !defined(__PRE_RAM__) static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) { if (base && size && s) { @@ -113,10 +110,6 @@ void cbmem_init(u64 baseaddr, u64 size) for (;;) ; } - /* we don't need to call this in romstage, useful only from ramstage */ -#ifndef __PRE_RAM__ - set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr); -#endif memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); cbmem_toc[0] = (struct cbmem_entry) { diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..96861c9 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -95,7 +95,7 @@ int acpi_is_wakeup_early(void) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; @@ -105,7 +105,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } #endif diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index e4cbc07..2139911 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -40,9 +40,9 @@ int acpi_get_sleep_type(void) } #endif -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ for (i = 0; i<4; i++) { @@ -132,19 +132,22 @@ void hudson_enable(device_t dev) } } -struct cbmem_entry *get_cbmem_toc(void) +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } - +#endif struct chip_operations southbridge_amd_agesa_hudson_ops = { CHIP_NAME("ATI HUDSON") diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 826ac05..91d7d2f 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -27,9 +27,9 @@ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 90ad5a9..8520548 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -37,9 +37,9 @@ int acpi_get_sleep_type(void) #endif #ifndef __PRE_RAM__ -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ printk(BIOS_DEBUG, "dword=%x\n", dword); for (i = 0; i<4; i++) { @@ -51,18 +51,22 @@ void set_cbmem_toc(struct cbmem_entry *toc) } #endif -struct cbmem_entry *get_cbmem_toc(void) +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) { u32 xdata = 0; int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } +#endif /** * @brief South Bridge CIMx configuration diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index a16fc9f..ddba1a8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -729,19 +729,21 @@ int acpi_is_wakeup_early(void) printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); return (((tmp & (7 << 10)) >> 10) == 3); } -#endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; + if (!acpi_is_wakeup_early()) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 23775b0..a175210 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -84,9 +84,9 @@ static void lpc_init(device_t dev) rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 4f0c98a..b3d16bf 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -673,19 +673,21 @@ static int acpi_is_wakeup_early(void) printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); return (((tmp & (7 << 10)) >> 10) == 3); } -#endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; + if (!acpi_is_wakeup_early()) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 000a532..d7049ae 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -183,6 +183,11 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) +{ + if (!acpi_is_wakeup_early()) + return 0; + return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } +#endif diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 151a228..74351bc 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -113,13 +113,8 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) { pci_write_config8(dev, 0xa6, 0x83); } -#if 0 -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); -} -#endif -void set_cbmem_toc(struct cbmem_entry *toc) { - outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +void backup_top_of_ram(uint64_t ramtop) { + outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h index f0d0fe0..7f83ffa 100644 --- a/src/southbridge/via/k8t890/k8t890.h +++ b/src/southbridge/via/k8t890/k8t890.h @@ -31,7 +31,7 @@ /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 -#define K8T890_NVRAM_CBMEM_TOC 0xfc +#define K8T890_NVRAM_TOP_OF_RAM 0xfc #define K8T890_MMCONFIG_MBAR 0x61 #define K8T890_MULTIPLE_FN_EN 0x4f

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Patch set updated for coreboot: c19fd7d CBMEM: Unify get_top_of_ram()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3904 -gerrit commit c19fd7dc1ec6781001ffd83958314a465519c23b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 01:11:16 2013 +0300 CBMEM: Unify get_top_of_ram() Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 2 ++ src/lib/cbmem.c | 1 - src/mainboard/emulation/qemu-i440fx/memory.c | 1 - src/northbridge/amd/lx/northbridge.h | 1 - src/northbridge/amd/lx/northbridgeinit.c | 3 ++- src/northbridge/intel/e7505/raminit.c | 1 + src/northbridge/intel/e7505/raminit.h | 1 - src/northbridge/intel/gm45/gm45.h | 1 - src/northbridge/intel/gm45/ram_calc.c | 3 ++- src/northbridge/intel/haswell/raminit.h | 1 - src/northbridge/intel/i945/raminit.h | 1 - src/northbridge/intel/sandybridge/northbridge.c | 2 +- src/northbridge/intel/sandybridge/raminit.h | 1 - src/northbridge/via/vx900/early_vx900.h | 1 - 14 files changed, 8 insertions(+), 12 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index d81335f..96b9da8 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -146,6 +146,8 @@ extern struct cbmem_entry *get_cbmem_toc(void); /* Common API between cbmem and dynamic cbmem. */ +unsigned long get_top_of_ram(void); + /* By default cbmem is attempted to be recovered. Returns 0 if cbmem was * recovered or 1 if cbmem had to be reinitialized. */ int cbmem_initialize(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 32a4614..41d80b8 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -222,7 +222,6 @@ int cbmem_initialize(void) int rv = 0; #ifdef __PRE_RAM__ - extern unsigned long get_top_of_ram(void); uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; uint64_t high_tables_size = HIGH_MEMORY_SIZE; #endif diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 000a0f6..08077e9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -40,7 +40,6 @@ static unsigned long qemu_get_memory_size(void) return tomk; } -unsigned long get_top_of_ram(void); unsigned long get_top_of_ram(void) { return qemu_get_memory_size() * 1024; diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h index fd62184..25075bd 100644 --- a/src/northbridge/amd/lx/northbridge.h +++ b/src/northbridge/amd/lx/northbridge.h @@ -28,7 +28,6 @@ int sizeram(void); /* northbridgeinit.c */ void northbridge_init_early(void); -uint32_t get_top_of_ram(void); /* pll_reset.c */ unsigned int GeodeLinkSpeed(void); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 3768777..f4c13f7 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -30,6 +30,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> +#include <cbmem.h> struct gliutable { unsigned long desc_name; @@ -713,7 +714,7 @@ static void setup_lx_cache(void) wbinvd(); } -uint32_t get_top_of_ram(void) +unsigned long get_top_of_ram(void) { struct gliutable *gl = 0; uint32_t systop; diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index ae02a7c..3d4dfe2 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -25,6 +25,7 @@ #include <assert.h> #include <spd.h> #include <sdram_mode.h> +#include <cbmem.h> #include "raminit.h" #include "e7505.h" diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index f9ba796..8eb4990 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -20,7 +20,6 @@ void e7505_mch_scrub_ecc(unsigned long ret_addr); void e7505_mch_done(const struct mem_controller *memctrl); int e7505_mch_is_ready(void); -unsigned long get_top_of_ram(void); /* Mainboard exports this. */ int spd_read_byte(unsigned device, unsigned address); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 2dffcad..227baef 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -422,7 +422,6 @@ void gm45_late_init(stepping_t); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); -u32 get_top_of_ram(void); void init_iommu(void); #endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 28e947b..a029020 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -26,6 +26,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> +#include <cbmem.h> #include "gm45.h" /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ @@ -83,7 +84,7 @@ u32 decode_igd_gtt_size(const u32 gsm) } } -u32 get_top_of_ram(void) +unsigned long get_top_of_ram(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 46be570..706c286 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -23,7 +23,6 @@ #include "pei_data.h" void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_haswell_errata(void); /* save_mrc_data() must be called after cbmem has been initialized. */ void save_mrc_data(struct pei_data *pei_data); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2d8ef9e..9eb4193 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -69,7 +69,6 @@ struct sys_info { void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); -unsigned long get_top_of_ram(void); int fixup_i945_errata(void); void udelay(u32 us); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4cd86cd..4abcec3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,7 +51,7 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -static unsigned long get_top_of_ram(void) +unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 23bdbd9..2e9b1f3 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -30,7 +30,6 @@ struct sys_info { } __attribute__ ((packed)); void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_sandybridge_errata(void); #endif /* RAMINIT_H */ diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h index dcb24b5..46e3023 100644 --- a/src/northbridge/via/vx900/early_vx900.h +++ b/src/northbridge/via/vx900/early_vx900.h @@ -61,7 +61,6 @@ #define RAMINIT_USE_HW_RXCR_CALIB 0 #define RAMINIT_USE_HW_MRS_SEQ 0 -unsigned long get_top_of_ram(void); void enable_smbus(void); void dump_spd_data(spd_raw_data spd);

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Patch set updated for coreboot: d786d0a CBMEM: Add cbmem_locate_table()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3558 -gerrit commit d786d0afec0808d3ec4a188fc3e7ba97523ed7ce Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:31:39 2013 +0300 CBMEM: Add cbmem_locate_table() For both romstage and ramstage, this calls an arch-specific function get_cbmem_table() to resolve the base and size of CBMEM region. In ramstage, the result is cached as the query may be relatively slow involving multiple PCI configuration reads. For x86 CBMEM tables are located right below top of low ram and have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation. Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/Makefile.inc | 2 ++ src/arch/x86/boot/cbmem.c | 21 ++++++++++++++++ src/include/cbmem.h | 1 + src/lib/cbmem.c | 54 ++++++++++++++++++++++++------------------ 4 files changed, 55 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 9334839..d3a5f21 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,3 +1,5 @@ +romstage-y += cbmem.c + ramstage-y += boot.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 6ec005d..333ca55 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -18,7 +18,28 @@ #include <console/console.h> #include <cbmem.h> +unsigned long __attribute__((weak)) get_top_of_ram(void) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); + return 0; +} + #if !CONFIG_DYNAMIC_CBMEM +void get_cbmem_table(uint64_t *base, uint64_t *size) +{ + uint64_t top_of_ram = get_top_of_ram(); + + if (top_of_ram >= HIGH_MEMORY_SIZE) { + *base = top_of_ram - HIGH_MEMORY_SIZE; + *size = HIGH_MEMORY_SIZE; + } else { + *base = 0; + *size = 0; + } +} +#endif + +#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) /* This is for compatibility with old boards only. Any new chipset and board * must implement get_top_of_ram() for both romstage and ramstage to support * features like CAR_MIGRATION and CBMEM_CONSOLE. diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 96b9da8..4ee0b2e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -140,6 +140,7 @@ int cbmem_base_check(void); void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); +void get_cbmem_table(uint64_t *base, uint64_t *size); extern struct cbmem_entry *get_cbmem_toc(void); #endif /* CONFIG_DYNAMIC_CBMEM */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 41d80b8..c69a8e6 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -45,30 +45,48 @@ struct cbmem_entry { #ifndef __PRE_RAM__ uint64_t high_tables_base = 0; uint64_t high_tables_size = 0; -static struct cbmem_entry *bss_cbmem_toc; +#endif -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) { - return bss_cbmem_toc; + /* do nothing, this should be called by chipset to save TOC in NVRAM */ } -void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) +#if !defined(__PRE_RAM__) +static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) { - /* do nothing, this should be called by chipset to save TOC in NVRAM */ + if (base && size && s) { + printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", + base, base + size - 1, s); + } } +#endif + +static void cbmem_locate_table(uint64_t *base, uint64_t *size) +{ +#ifdef __PRE_RAM__ + get_cbmem_table(base, size); #else + if (!(high_tables_base && high_tables_size)) { + get_cbmem_table(&high_tables_base, &high_tables_size); + cbmem_trace_location(high_tables_base, high_tables_size, __FUNCTION__); + } + *base = high_tables_base; + *size = high_tables_size; +#endif +} struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) { - printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); - return NULL; + uint64_t base, size; + cbmem_locate_table(&base, &size); + return (struct cbmem_entry *)(unsigned long)base; } -#endif #if !defined(__PRE_RAM__) void cbmem_late_set_table(uint64_t base, uint64_t size) { - printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", base, base+size-1, __FUNCTION__); + cbmem_trace_location(base, size, __FUNCTION__); high_tables_base = base; high_tables_size = size; } @@ -89,10 +107,6 @@ void cbmem_init(u64 baseaddr, u64 size) struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); @@ -123,10 +137,6 @@ int cbmem_reinit(u64 baseaddr) printk(BIOS_DEBUG, "Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - return (cbmem_toc[0].magic == CBMEM_MAGIC); } @@ -219,21 +229,19 @@ void *cbmem_find(u32 id) /* Returns True if it was not initialized before. */ int cbmem_initialize(void) { + uint64_t base = 0, size = 0; int rv = 0; -#ifdef __PRE_RAM__ - uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - uint64_t high_tables_size = HIGH_MEMORY_SIZE; -#endif + cbmem_locate_table(&base, &size); /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit(high_tables_base)) { + if (!cbmem_reinit(base)) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) /* Something went wrong, our high memory area got wiped */ if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; #endif - cbmem_init(high_tables_base, high_tables_size); + cbmem_init(base, size); rv = 1; } #ifndef __PRE_RAM__

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coreboot-gerrit September 2013