coreboot-gerrit September 2013

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Patch set updated for coreboot: 1d7e945 CBMEM: Backup top_of_ram instead of cbmem_toc
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3557 -gerrit commit 1d7e945d0eca4419eaf258ce01d011c6b8647e2b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:26:11 2013 +0300 CBMEM: Backup top_of_ram instead of cbmem_toc AMD northbridges have a complex way to resolve top_of_ram. Once it is resolved, it is stored in NVRAM to be used on resume. TODO: Redesign these get_top_of_ram() functions from scratch. Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 6 ++++++ src/cpu/amd/agesa/s3_resume.c | 3 ++- src/cpu/amd/car/post_cache_as_ram.c | 3 ++- src/include/cbmem.h | 2 +- src/lib/cbmem.c | 9 --------- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.c | 13 ++++++++----- src/southbridge/amd/cimx/sb700/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb800/cfg.c | 12 ++++++++---- src/southbridge/amd/sb700/early_setup.c | 8 +++++--- src/southbridge/amd/sb700/lpc.c | 4 ++-- src/southbridge/amd/sb800/early_setup.c | 8 +++++--- src/southbridge/via/k8t890/early_car.c | 9 +++++++-- src/southbridge/via/k8t890/host_ctrl.c | 9 ++------- src/southbridge/via/k8t890/k8t890.h | 2 +- 15 files changed, 53 insertions(+), 43 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 333ca55..991a3e6 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -40,12 +40,18 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) #endif #if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) +void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) +{ + /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ +} + /* This is for compatibility with old boards only. Any new chipset and board * must implement get_top_of_ram() for both romstage and ramstage to support * features like CAR_MIGRATION and CBMEM_CONSOLE. */ void set_top_of_ram(uint64_t ramtop) { + backup_top_of_ram(ramtop); cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } #endif diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6ba9212..fcc1604 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -120,7 +120,8 @@ inline void *backup_resume(void) * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); */ - cbmem_reinit((u64) high_ram_base); + if (!cbmem_reinit((u64)high_ram_base)) + return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (((u32) resume_backup_memory == 0) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 18c278e..d20c393 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -45,7 +45,8 @@ static inline void *backup_resume(void) { print_debug_pcar("CBMEM TOC is at: ", (uint32_t)high_ram_base); print_debug_pcar("CBMEM TOC 0-size: ",(uint32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); - cbmem_reinit((u64)high_ram_base); + if (!cbmem_reinit((u64)high_ram_base)) + return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4ee0b2e..bbdfe38 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -132,8 +132,8 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); +void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); -void set_cbmem_toc(struct cbmem_entry *); int cbmem_base_check(void); #endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index c69a8e6..b6751de 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -47,11 +47,6 @@ uint64_t high_tables_base = 0; uint64_t high_tables_size = 0; #endif -void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) -{ - /* do nothing, this should be called by chipset to save TOC in NVRAM */ -} - #if !defined(__PRE_RAM__) static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) { @@ -115,10 +110,6 @@ void cbmem_init(u64 baseaddr, u64 size) for (;;) ; } - /* we don't need to call this in romstage, useful only from ramstage */ -#ifndef __PRE_RAM__ - set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr); -#endif memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); cbmem_toc[0] = (struct cbmem_entry) { diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..96861c9 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -95,7 +95,7 @@ int acpi_is_wakeup_early(void) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; @@ -105,7 +105,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } #endif diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index e4cbc07..dac0ede 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -40,9 +40,9 @@ int acpi_get_sleep_type(void) } #endif -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ for (i = 0; i<4; i++) { @@ -132,19 +132,22 @@ void hudson_enable(device_t dev) } } -struct cbmem_entry *get_cbmem_toc(void) +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; + if (!acpi_is_wakeup_early()) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } - +#endif struct chip_operations southbridge_amd_agesa_hudson_ops = { CHIP_NAME("ATI HUDSON") diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 826ac05..91d7d2f 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -27,9 +27,9 @@ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 90ad5a9..8520548 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -37,9 +37,9 @@ int acpi_get_sleep_type(void) #endif #ifndef __PRE_RAM__ -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ printk(BIOS_DEBUG, "dword=%x\n", dword); for (i = 0; i<4; i++) { @@ -51,18 +51,22 @@ void set_cbmem_toc(struct cbmem_entry *toc) } #endif -struct cbmem_entry *get_cbmem_toc(void) +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) { u32 xdata = 0; int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } +#endif /** * @brief South Bridge CIMx configuration diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index a16fc9f..ddba1a8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -729,19 +729,21 @@ int acpi_is_wakeup_early(void) printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); return (((tmp & (7 << 10)) >> 10) == 3); } -#endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; + if (!acpi_is_wakeup_early()) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 23775b0..a175210 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -84,9 +84,9 @@ static void lpc_init(device_t dev) rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 4f0c98a..b3d16bf 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -673,19 +673,21 @@ static int acpi_is_wakeup_early(void) printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); return (((tmp & (7 << 10)) >> 10) == 3); } -#endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; + if (!acpi_is_wakeup_early()) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 000a532..d7049ae 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -183,6 +183,11 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) +{ + if (!acpi_is_wakeup_early()) + return 0; + return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } +#endif diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 151a228..74351bc 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -113,13 +113,8 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) { pci_write_config8(dev, 0xa6, 0x83); } -#if 0 -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); -} -#endif -void set_cbmem_toc(struct cbmem_entry *toc) { - outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +void backup_top_of_ram(uint64_t ramtop) { + outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h index f0d0fe0..7f83ffa 100644 --- a/src/southbridge/via/k8t890/k8t890.h +++ b/src/southbridge/via/k8t890/k8t890.h @@ -31,7 +31,7 @@ /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 -#define K8T890_NVRAM_CBMEM_TOC 0xfc +#define K8T890_NVRAM_TOP_OF_RAM 0xfc #define K8T890_MMCONFIG_MBAR 0x61 #define K8T890_MULTIPLE_FN_EN 0x4f

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New patch to review for coreboot: ef09e8f CBMEM: Unify get_cbmem_toc()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3907 -gerrit commit ef09e8fdedb6a851041e38d6a898101afefaf6ed Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Sep 6 10:46:22 2013 +0300 CBMEM: Unify get_cbmem_toc() Change-Id: I338ee2c1bd51f5e517462115170dc926e040159e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 2 +- src/lib/cbmem.c | 2 +- src/mainboard/emulation/qemu-i440fx/memory.c | 7 +------ src/northbridge/intel/i945/raminit.c | 5 ----- src/northbridge/intel/sandybridge/northbridge.c | 8 -------- src/northbridge/intel/sandybridge/raminit.c | 5 ----- src/northbridge/via/vx900/early_vx900.c | 5 ----- 7 files changed, 3 insertions(+), 31 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index bbdfe38..00998f3 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -141,7 +141,7 @@ void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); void get_cbmem_table(uint64_t *base, uint64_t *size); -extern struct cbmem_entry *get_cbmem_toc(void); +struct cbmem_entry *get_cbmem_toc(void); #endif /* CONFIG_DYNAMIC_CBMEM */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 5ee81ac..e27167c 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -69,7 +69,7 @@ static void cbmem_locate_table(uint64_t *base, uint64_t *size) #endif } -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +struct cbmem_entry *get_cbmem_toc(void) { uint64_t base, size; cbmem_locate_table(&base, &size); diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 08077e9..027deb9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -45,12 +45,7 @@ unsigned long get_top_of_ram(void) return qemu_get_memory_size() * 1024; } -#if !CONFIG_DYNAMIC_CBMEM -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} -#else +#if CONFIG_DYNAMIC_CBMEM void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1a0684..b50f1d8 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,11 +28,6 @@ #include "i945.h" #include <cbmem.h> -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4abcec3..a03b8a6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -58,14 +58,6 @@ unsigned long get_top_of_ram(void) return (unsigned long) tom; } -struct cbmem_entry *get_cbmem_toc(void) -{ - static struct cbmem_entry *toc = NULL; - if (!toc) - toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); - return toc; -} - /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3eb2fb3..3b321d7 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -305,11 +305,6 @@ void sdram_initialize(struct pei_data *pei_data) save_mrc_data(pei_data); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 2439c8d..2896680 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -27,11 +27,6 @@ unsigned long get_top_of_ram(void) return (((unsigned long)reg_tom) << 24) - (256 << 20); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /** * \brief Enable accessing of PCI configuration space for all devices. *

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Patch set updated for coreboot: 7abdc42 CBMEM: Unify get_top_of_ram()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3904 -gerrit commit 7abdc421ba7f978eb3a4f83d442b913218e9b114 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 01:11:16 2013 +0300 CBMEM: Unify get_top_of_ram() Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 2 ++ src/mainboard/emulation/qemu-i440fx/memory.c | 1 - src/northbridge/amd/lx/northbridge.h | 1 - src/northbridge/amd/lx/northbridgeinit.c | 3 ++- src/northbridge/intel/e7505/raminit.c | 1 + src/northbridge/intel/e7505/raminit.h | 1 - src/northbridge/intel/gm45/gm45.h | 1 - src/northbridge/intel/gm45/ram_calc.c | 3 ++- src/northbridge/intel/haswell/raminit.h | 1 - src/northbridge/intel/i945/raminit.h | 1 - src/northbridge/intel/sandybridge/northbridge.c | 2 +- src/northbridge/intel/sandybridge/raminit.h | 1 - src/northbridge/via/vx900/early_vx900.h | 1 - 13 files changed, 8 insertions(+), 11 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index d81335f..96b9da8 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -146,6 +146,8 @@ extern struct cbmem_entry *get_cbmem_toc(void); /* Common API between cbmem and dynamic cbmem. */ +unsigned long get_top_of_ram(void); + /* By default cbmem is attempted to be recovered. Returns 0 if cbmem was * recovered or 1 if cbmem had to be reinitialized. */ int cbmem_initialize(void); diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 000a0f6..08077e9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -40,7 +40,6 @@ static unsigned long qemu_get_memory_size(void) return tomk; } -unsigned long get_top_of_ram(void); unsigned long get_top_of_ram(void) { return qemu_get_memory_size() * 1024; diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h index fd62184..25075bd 100644 --- a/src/northbridge/amd/lx/northbridge.h +++ b/src/northbridge/amd/lx/northbridge.h @@ -28,7 +28,6 @@ int sizeram(void); /* northbridgeinit.c */ void northbridge_init_early(void); -uint32_t get_top_of_ram(void); /* pll_reset.c */ unsigned int GeodeLinkSpeed(void); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 3768777..f4c13f7 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -30,6 +30,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> +#include <cbmem.h> struct gliutable { unsigned long desc_name; @@ -713,7 +714,7 @@ static void setup_lx_cache(void) wbinvd(); } -uint32_t get_top_of_ram(void) +unsigned long get_top_of_ram(void) { struct gliutable *gl = 0; uint32_t systop; diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index ae02a7c..3d4dfe2 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -25,6 +25,7 @@ #include <assert.h> #include <spd.h> #include <sdram_mode.h> +#include <cbmem.h> #include "raminit.h" #include "e7505.h" diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index f9ba796..8eb4990 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -20,7 +20,6 @@ void e7505_mch_scrub_ecc(unsigned long ret_addr); void e7505_mch_done(const struct mem_controller *memctrl); int e7505_mch_is_ready(void); -unsigned long get_top_of_ram(void); /* Mainboard exports this. */ int spd_read_byte(unsigned device, unsigned address); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 2dffcad..227baef 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -422,7 +422,6 @@ void gm45_late_init(stepping_t); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); -u32 get_top_of_ram(void); void init_iommu(void); #endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 28e947b..a029020 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -26,6 +26,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> +#include <cbmem.h> #include "gm45.h" /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ @@ -83,7 +84,7 @@ u32 decode_igd_gtt_size(const u32 gsm) } } -u32 get_top_of_ram(void) +unsigned long get_top_of_ram(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 46be570..706c286 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -23,7 +23,6 @@ #include "pei_data.h" void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_haswell_errata(void); /* save_mrc_data() must be called after cbmem has been initialized. */ void save_mrc_data(struct pei_data *pei_data); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2d8ef9e..9eb4193 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -69,7 +69,6 @@ struct sys_info { void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); -unsigned long get_top_of_ram(void); int fixup_i945_errata(void); void udelay(u32 us); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4cd86cd..4abcec3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,7 +51,7 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -static unsigned long get_top_of_ram(void) +unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 23bdbd9..2e9b1f3 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -30,7 +30,6 @@ struct sys_info { } __attribute__ ((packed)); void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_sandybridge_errata(void); #endif /* RAMINIT_H */ diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h index dcb24b5..46e3023 100644 --- a/src/northbridge/via/vx900/early_vx900.h +++ b/src/northbridge/via/vx900/early_vx900.h @@ -61,7 +61,6 @@ #define RAMINIT_USE_HW_RXCR_CALIB 0 #define RAMINIT_USE_HW_MRS_SEQ 0 -unsigned long get_top_of_ram(void); void enable_smbus(void); void dump_spd_data(spd_raw_data spd);

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Patch set updated for coreboot: fe8dc29 CBMEM: Add cbmem_locate_table()
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3558 -gerrit commit fe8dc298354944b4f74c7bb2c4036e2656d77b4b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:31:39 2013 +0300 CBMEM: Add cbmem_locate_table() For both romstage and ramstage, this calls an arch-specific function get_cbmem_table() to resolve the base and size of CBMEM region. In ramstage, the result is cached as the query may be relatively slow involving multiple PCI configuration reads. For x86 CBMEM tables are located right below top of low ram and have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation. Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/Makefile.inc | 2 ++ src/arch/x86/boot/cbmem.c | 21 +++++++++++++++++ src/include/cbmem.h | 1 + src/lib/cbmem.c | 53 +++++++++++++++++++++++------------------- 4 files changed, 53 insertions(+), 24 deletions(-) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 9334839..d3a5f21 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,3 +1,5 @@ +romstage-y += cbmem.c + ramstage-y += boot.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 6ec005d..333ca55 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -18,7 +18,28 @@ #include <console/console.h> #include <cbmem.h> +unsigned long __attribute__((weak)) get_top_of_ram(void) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); + return 0; +} + #if !CONFIG_DYNAMIC_CBMEM +void get_cbmem_table(uint64_t *base, uint64_t *size) +{ + uint64_t top_of_ram = get_top_of_ram(); + + if (top_of_ram >= HIGH_MEMORY_SIZE) { + *base = top_of_ram - HIGH_MEMORY_SIZE; + *size = HIGH_MEMORY_SIZE; + } else { + *base = 0; + *size = 0; + } +} +#endif + +#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) /* This is for compatibility with old boards only. Any new chipset and board * must implement get_top_of_ram() for both romstage and ramstage to support * features like CAR_MIGRATION and CBMEM_CONSOLE. diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 96b9da8..4ee0b2e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -140,6 +140,7 @@ int cbmem_base_check(void); void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); +void get_cbmem_table(uint64_t *base, uint64_t *size); extern struct cbmem_entry *get_cbmem_toc(void); #endif /* CONFIG_DYNAMIC_CBMEM */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 32a4614..6db9cb5 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -45,30 +45,46 @@ struct cbmem_entry { #ifndef __PRE_RAM__ uint64_t high_tables_base = 0; uint64_t high_tables_size = 0; -static struct cbmem_entry *bss_cbmem_toc; +#endif -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) { - return bss_cbmem_toc; + /* do nothing, this should be called by chipset to save TOC in NVRAM */ } -void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) +static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) { - /* do nothing, this should be called by chipset to save TOC in NVRAM */ + if (base && size && s) { + printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", + base, base + size - 1, s); + } } + +static void cbmem_locate_table(uint64_t *base, uint64_t *size) +{ +#ifdef __PRE_RAM__ + get_cbmem_table(base, size); #else + if (!(high_tables_base && high_tables_size)) { + get_cbmem_table(&high_tables_base, &high_tables_size); + cbmem_trace_location(high_tables_base, high_tables_size, __FUNCTION__); + } + *base = high_tables_base; + *size = high_tables_size; +#endif +} struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) { - printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); - return NULL; + uint64_t base, size; + cbmem_locate_table(&base, &size); + return (struct cbmem_entry *)(unsigned long)base; } -#endif #if !defined(__PRE_RAM__) void cbmem_late_set_table(uint64_t base, uint64_t size) { - printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", base, base+size-1, __FUNCTION__); + cbmem_trace_location(base, size, __FUNCTION__); high_tables_base = base; high_tables_size = size; } @@ -89,10 +105,6 @@ void cbmem_init(u64 baseaddr, u64 size) struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); @@ -123,10 +135,6 @@ int cbmem_reinit(u64 baseaddr) printk(BIOS_DEBUG, "Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - return (cbmem_toc[0].magic == CBMEM_MAGIC); } @@ -219,22 +227,19 @@ void *cbmem_find(u32 id) /* Returns True if it was not initialized before. */ int cbmem_initialize(void) { + uint64_t base = 0, size = 0; int rv = 0; -#ifdef __PRE_RAM__ - extern unsigned long get_top_of_ram(void); - uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - uint64_t high_tables_size = HIGH_MEMORY_SIZE; -#endif + cbmem_locate_table(&base, &size); /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit(high_tables_base)) { + if (!cbmem_reinit(base)) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) /* Something went wrong, our high memory area got wiped */ if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; #endif - cbmem_init(high_tables_base, high_tables_size); + cbmem_init(base, size); rv = 1; } #ifndef __PRE_RAM__

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Patch set updated for coreboot: 50b7d14 CBMEM: Backup top_of_ram instead of cbmem_toc
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3557 -gerrit commit 50b7d1462523d660d1383cb55a0e6d60fbacda1b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:26:11 2013 +0300 CBMEM: Backup top_of_ram instead of cbmem_toc AMD northbridges have a complex way to resolve top_of_ram. Once it is resolved, it is stored in NVRAM to be used on resume. TODO: Redesign these get_top_of_ram() functions from scratch. Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 6 ++++++ src/cpu/amd/agesa/s3_resume.c | 3 ++- src/cpu/amd/car/post_cache_as_ram.c | 3 ++- src/include/cbmem.h | 2 +- src/lib/cbmem.c | 9 --------- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.c | 13 ++++++++----- src/southbridge/amd/cimx/sb700/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb800/cfg.c | 12 ++++++++---- src/southbridge/amd/sb700/early_setup.c | 8 +++++--- src/southbridge/amd/sb700/lpc.c | 4 ++-- src/southbridge/amd/sb800/early_setup.c | 8 +++++--- src/southbridge/via/k8t890/early_car.c | 9 +++++++-- src/southbridge/via/k8t890/host_ctrl.c | 9 ++------- src/southbridge/via/k8t890/k8t890.h | 2 +- 15 files changed, 53 insertions(+), 43 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 333ca55..991a3e6 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -40,12 +40,18 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) #endif #if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) +void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) +{ + /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ +} + /* This is for compatibility with old boards only. Any new chipset and board * must implement get_top_of_ram() for both romstage and ramstage to support * features like CAR_MIGRATION and CBMEM_CONSOLE. */ void set_top_of_ram(uint64_t ramtop) { + backup_top_of_ram(ramtop); cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } #endif diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6ba9212..fcc1604 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -120,7 +120,8 @@ inline void *backup_resume(void) * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); */ - cbmem_reinit((u64) high_ram_base); + if (!cbmem_reinit((u64)high_ram_base)) + return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (((u32) resume_backup_memory == 0) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 18c278e..d20c393 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -45,7 +45,8 @@ static inline void *backup_resume(void) { print_debug_pcar("CBMEM TOC is at: ", (uint32_t)high_ram_base); print_debug_pcar("CBMEM TOC 0-size: ",(uint32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); - cbmem_reinit((u64)high_ram_base); + if (!cbmem_reinit((u64)high_ram_base)) + return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 4ee0b2e..bbdfe38 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -132,8 +132,8 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); +void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); -void set_cbmem_toc(struct cbmem_entry *); int cbmem_base_check(void); #endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6db9cb5..5ee81ac 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -47,11 +47,6 @@ uint64_t high_tables_base = 0; uint64_t high_tables_size = 0; #endif -void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) -{ - /* do nothing, this should be called by chipset to save TOC in NVRAM */ -} - static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) { if (base && size && s) { @@ -113,10 +108,6 @@ void cbmem_init(u64 baseaddr, u64 size) for (;;) ; } - /* we don't need to call this in romstage, useful only from ramstage */ -#ifndef __PRE_RAM__ - set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr); -#endif memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); cbmem_toc[0] = (struct cbmem_entry) { diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..96861c9 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -95,7 +95,7 @@ int acpi_is_wakeup_early(void) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; @@ -105,7 +105,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } #endif diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index e4cbc07..dac0ede 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -40,9 +40,9 @@ int acpi_get_sleep_type(void) } #endif -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ for (i = 0; i<4; i++) { @@ -132,19 +132,22 @@ void hudson_enable(device_t dev) } } -struct cbmem_entry *get_cbmem_toc(void) +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; + if (!acpi_is_wakeup_early()) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } - +#endif struct chip_operations southbridge_amd_agesa_hudson_ops = { CHIP_NAME("ATI HUDSON") diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 826ac05..91d7d2f 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -27,9 +27,9 @@ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 90ad5a9..8520548 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -37,9 +37,9 @@ int acpi_get_sleep_type(void) #endif #ifndef __PRE_RAM__ -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ printk(BIOS_DEBUG, "dword=%x\n", dword); for (i = 0; i<4; i++) { @@ -51,18 +51,22 @@ void set_cbmem_toc(struct cbmem_entry *toc) } #endif -struct cbmem_entry *get_cbmem_toc(void) +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) { u32 xdata = 0; int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } +#endif /** * @brief South Bridge CIMx configuration diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index a16fc9f..ddba1a8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -729,19 +729,21 @@ int acpi_is_wakeup_early(void) printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); return (((tmp & (7 << 10)) >> 10) == 3); } -#endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; + if (!acpi_is_wakeup_early()) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 23775b0..a175210 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -84,9 +84,9 @@ static void lpc_init(device_t dev) rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 4f0c98a..b3d16bf 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -673,19 +673,21 @@ static int acpi_is_wakeup_early(void) printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); return (((tmp & (7 << 10)) >> 10) == 3); } -#endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; + if (!acpi_is_wakeup_early()) + return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); xdata &= ~(0xff << (xi * 8)); xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } +#endif #endif diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 000a532..d7049ae 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -183,6 +183,11 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +#if CONFIG_HAVE_ACPI_RESUME +unsigned long get_top_of_ram(void) +{ + if (!acpi_is_wakeup_early()) + return 0; + return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } +#endif diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 151a228..74351bc 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -113,13 +113,8 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) { pci_write_config8(dev, 0xa6, 0x83); } -#if 0 -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); -} -#endif -void set_cbmem_toc(struct cbmem_entry *toc) { - outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +void backup_top_of_ram(uint64_t ramtop) { + outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h index f0d0fe0..7f83ffa 100644 --- a/src/southbridge/via/k8t890/k8t890.h +++ b/src/southbridge/via/k8t890/k8t890.h @@ -31,7 +31,7 @@ /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 -#define K8T890_NVRAM_CBMEM_TOC 0xfc +#define K8T890_NVRAM_TOP_OF_RAM 0xfc #define K8T890_MMCONFIG_MBAR 0x61 #define K8T890_MULTIPLE_FN_EN 0x4f

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Patch merged into coreboot/master: 25dd247 libpayload: Set heap's header size to 64-bit
by gerrit＠coreboot.org 06 Sep '13

06 Sep '13

the following patch was just integrated into master: commit 25dd2479c1890d45935d7dbfc14599385e1893dd Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Jun 14 15:34:59 2013 +0200 libpayload: Set heap's header size to 64-bit For libpayload clients with larger memory needs (eg. FILO with integrated flashrom) the current configuration isn't enough. Change-Id: Ic82d6477c53da62a1325400f2e596d7d557d5d1e Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3889 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See http://review.coreboot.org/3889 for details. -gerrit

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Patch set updated for coreboot: 2a6ca04 libpayload: Set heap's header size to 64-bit
by Nico Huber 06 Sep '13

06 Sep '13

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3889 -gerrit commit 2a6ca04efc0260d3d37c6d73fe5496c41971fc8f Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Jun 14 15:34:59 2013 +0200 libpayload: Set heap's header size to 64-bit For libpayload clients with larger memory needs (eg. FILO with integrated flashrom) the current configuration isn't enough. Change-Id: Ic82d6477c53da62a1325400f2e596d7d557d5d1e Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/libc/malloc.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index c03cc73..851ef57 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -37,9 +37,6 @@ * We're also susceptible to the usual buffer overrun poisoning, though the * risk is within acceptable ranges for this implementation (don't overrun * your buffers, kids!). - * - * The header format (hdrtype_t) supports heaps of up to 32MiB (given that int - * is 32 bits long). */ #define IN_MALLOC_C @@ -50,7 +47,7 @@ extern char _heap, _eheap; /* Defined in the ldscript. */ static void *hstart = (void *)&_heap; static void *hend = (void *)&_eheap; -typedef unsigned int hdrtype_t; +typedef u64 hdrtype_t; #define HDRSIZE (sizeof(hdrtype_t)) #define SIZE_BITS ((HDRSIZE << 3) - 7)

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Patch merged into coreboot/master: 2d4b4ca libpayload: Make heap code independent of its header size
by gerrit＠coreboot.org 06 Sep '13

06 Sep '13

the following patch was just integrated into master: commit 2d4b4cafe62b43815806fa7145e647f9daca0d38 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Jun 14 15:26:49 2013 +0200 libpayload: Make heap code independent of its header size Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Change-Id: Ie69ceb343494b7dd309847b7d606cb47925f68b6 Reviewed-on: http://review.coreboot.org/3888 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3888 for details. -gerrit

1 0

Patch set updated for coreboot: 5ee885f CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3902 -gerrit commit 5ee885fa43973bc40fdd270f0670a1cc97bbc360 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:05:01 2013 +0300 CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base This helper function is for compatibility only for chipsets that do not implement get_top_of_ram() to support early CBMEM. Also remove references to globals high_tables_base and _size under arch/ and from two ARMv7 boards. Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/tables.c | 7 ------- src/arch/x86/boot/cbmem.c | 5 +---- src/arch/x86/boot/tables.c | 13 ++++++++++--- src/include/cbmem.h | 1 + src/lib/cbmem.c | 10 ++++++++++ src/mainboard/google/pit/mainboard.c | 17 +++++++++++------ src/mainboard/google/snow/mainboard.c | 17 +++++++++++------ 7 files changed, 44 insertions(+), 26 deletions(-) diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index 0fc7399..0f174d3 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -29,13 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -/* - * TODO: "High" tables are a convention used on x86. Maybe we can - * clean up that naming at some point. - */ -uint64_t high_tables_base = 0; -uint64_t high_tables_size; - void cbmem_arch_init(void) { } diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 3f738be..6ec005d 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -25,9 +25,6 @@ */ void set_top_of_ram(uint64_t ramtop) { - high_tables_base = ramtop - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", - high_tables_base, high_tables_size); + cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } #endif diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 67d7911..31d0fc7 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -32,8 +32,6 @@ #include <lib.h> #include <smbios.h> -uint64_t high_tables_base = 0; -uint64_t high_tables_size; void cbmem_arch_init(void) { @@ -227,9 +225,18 @@ struct lb_memory *write_tables(void) if (high_table_pointer) { unsigned long new_high_table_pointer; + /* FIXME: The high_table_base parameter is not reference when tables are high, + * or high_table_pointer >1 MB. + */ +#if CONFIG_DYNAMIC_CBMEM + u64 fixme_high_tables_base = 0; +#else + u64 fixme_high_tables_base = high_tables_base; +#endif + /* Also put a forwarder entry into 0-4K */ new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, - high_tables_base, high_table_pointer); + fixme_high_tables_base, high_table_pointer); if (new_high_table_pointer > (high_table_pointer + MAX_COREBOOT_TABLE_SIZE)) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 00d74d6..3d04763 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -137,6 +137,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); +void cbmem_late_set_table(uint64_t base, uint64_t size); void set_cbmem_toc(struct cbmem_entry *); #endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 9e2ce0d..206fdbf 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -42,6 +42,8 @@ struct cbmem_entry { } __attribute__((packed)); #ifndef __PRE_RAM__ +uint64_t high_tables_base = 0; +uint64_t high_tables_size = 0; static struct cbmem_entry *bss_cbmem_toc; struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) @@ -60,7 +62,15 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); return NULL; } +#endif +#if !defined(__PRE_RAM__) +void cbmem_late_set_table(uint64_t base, uint64_t size) +{ + printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", base, base+size-1, __FUNCTION__); + high_tables_base = base; + high_tables_size = size; +} #endif /** diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 54ea042..7dd8388 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -221,17 +221,22 @@ static void mainboard_init(device_t dev) // gpio_info(); } +static void setup_cbmem(void) +{ + u64 size = CONFIG_COREBOOT_TABLES_SIZE; + u64 base = CONFIG_SYS_SDRAM_BASE + + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + cbmem_late_set_table(base, size); + cbmem_init(base, size); +} + static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); + setup_cbmem(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 5aedac9..8805be5 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -262,17 +262,22 @@ static void mainboard_init(device_t dev) // gpio_info(); } +static void setup_cbmem(void) +{ + u64 size = CONFIG_COREBOOT_TABLES_SIZE; + u64 base = CONFIG_SYS_SDRAM_BASE + + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + cbmem_late_set_table(base, size); + cbmem_init(base, size); +} + static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); + setup_cbmem(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */

1 0

Patch set updated for coreboot: 80adbcc CBMEM tables: Remove references to global high_tables_base
by Kyösti Mälkki 06 Sep '13

06 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3559 -gerrit commit 80adbcc12ad89784e7f83a9645db01da195330d7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 14:11:08 2013 +0300 CBMEM tables: Remove references to global high_tables_base Unify checks and writing of CBMEM tables for x86 and ARMv7. Change-Id: I89c012bce1b86d0710748719a8840ec532ce6939 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/tables.c | 6 +----- src/arch/x86/boot/tables.c | 10 ++-------- src/include/cbmem.h | 9 ++++----- src/lib/cbmem.c | 17 +++++++++++++++++ src/lib/coreboot_table.c | 5 ----- 5 files changed, 24 insertions(+), 23 deletions(-) diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index 0f174d3..de6b6fa 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -37,11 +37,7 @@ struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer; - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); - } - - printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); + cbmem_base_check(); post_code(0x9d); diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 31d0fc7..eea9bf1 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -51,13 +51,7 @@ struct lb_memory *write_tables(void) unsigned long high_table_pointer; #if !CONFIG_DYNAMIC_CBMEM - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); - // Are there any boards without? - // Stepan thinks we should die() here! - } - - printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); + cbmem_base_check(); #endif rom_table_start = 0xf0000; @@ -231,7 +225,7 @@ struct lb_memory *write_tables(void) #if CONFIG_DYNAMIC_CBMEM u64 fixme_high_tables_base = 0; #else - u64 fixme_high_tables_base = high_tables_base; + u64 fixme_high_tables_base = (u32)get_cbmem_toc(); #endif /* Also put a forwarder entry into 0-4K */ diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 3d04763..d81335f 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -126,11 +126,6 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); -#ifndef __PRE_RAM__ -/* Add the cbmem memory used to the memory tables. */ -struct lb_memory; -void cbmem_add_lb_mem(struct lb_memory *mem); -#endif /* __PRE_RAM__ */ #else /* !CONFIG_DYNAMIC_CBMEM */ @@ -139,6 +134,7 @@ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); void set_cbmem_toc(struct cbmem_entry *); +int cbmem_base_check(void); #endif void cbmem_init(u64 baseaddr, u64 size); @@ -162,6 +158,9 @@ void *cbmem_find(u32 id); #ifndef __PRE_RAM__ /* Ramstage only functions. */ +/* Add the cbmem memory used to the memory tables. */ +struct lb_memory; +void cbmem_add_lb_mem(struct lb_memory *mem); void cbmem_list(void); void cbmem_arch_init(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 206fdbf..32a4614 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -21,6 +21,7 @@ #include <string.h> #include <bootstate.h> #include <cbmem.h> +#include <boot/coreboot_tables.h> #include <console/console.h> #include <cpu/x86/car.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) @@ -260,6 +261,22 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_post_device, NULL), }; +int cbmem_base_check(void) +{ + if (!high_tables_base) { + printk(BIOS_ERR, "ERROR: CBMEM Base is not set.\n"); + // Are there any boards without? + // Stepan thinks we should die() here! + } + printk(BIOS_DEBUG, "CBMEM Base is %llx.\n", high_tables_base); + return !!high_tables_base; +} + +void cbmem_add_lb_mem(struct lb_memory *mem) +{ + lb_add_memory_range(mem, LB_MEM_TABLE, high_tables_base, high_tables_size); +} + void cbmem_list(void) { struct cbmem_entry *cbmem_toc; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3fad4c7..e5729ba 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -539,12 +539,7 @@ unsigned long write_coreboot_table( lb_add_memory_range(mem, LB_MEM_TABLE, rom_table_start, rom_table_end - rom_table_start); -#if CONFIG_DYNAMIC_CBMEM cbmem_add_lb_mem(mem); -#else /* CONFIG_DYNAMIC_CBMEM */ - lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); -#endif /* CONFIG_DYNAMIC_CBMEM */ /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */

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coreboot-gerrit September 2013