coreboot-gerrit September 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 3691089 Add get_cbmem_table for x86
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3558 -gerrit commit 3691089f1fb61e6267c94cf97b670ed67b7ddf53 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:31:39 2013 +0300 Add get_cbmem_table for x86 For x86 CBMEM tables are located right below top of low ram and have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation. NOTE: Boards will need to have get_top_of_ram() added for ramstage. Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/ramtop.c | 15 +++++++++++++++ src/include/cbmem.h | 1 + src/lib/cbmem.c | 41 +++++++++++++++-------------------------- 3 files changed, 31 insertions(+), 26 deletions(-) diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c index 16faf48e..84bd6d9 100644 --- a/src/arch/x86/boot/ramtop.c +++ b/src/arch/x86/boot/ramtop.c @@ -24,6 +24,21 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) return 0; } +#if !CONFIG_DYNAMIC_CBMEM +void get_cbmem_table(uint64_t *base, uint64_t *size) +{ + uint64_t top_of_ram = get_top_of_ram(); + + if (top_of_ram >= HIGH_MEMORY_SIZE) { + *base = top_of_ram - HIGH_MEMORY_SIZE; + *size = HIGH_MEMORY_SIZE; + } else { + *base = 0; + *size = 0; + } +} +#endif + #if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) { diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b44a3fe..6c7b85c 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -145,6 +145,7 @@ int cbmem_reinit(u64 baseaddr); unsigned long get_top_of_ram(void); struct cbmem_entry *get_cbmem_toc(void); +void get_cbmem_table(uint64_t *base, uint64_t *size); #endif /* CONFIG_DYNAMIC_CBMEM */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6bc081e..3f8f243 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -41,22 +41,22 @@ struct cbmem_entry { u64 size; } __attribute__((packed)); -#ifndef __PRE_RAM__ -static struct cbmem_entry *bss_cbmem_toc; - -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +static void cbmem_locate_table(uint64_t *base, uint64_t *size) { - return bss_cbmem_toc; -} - +#ifdef __PRE_RAM__ + get_cbmem_table(base, size); #else + *base = high_tables_base; + *size = high_tables_size; +#endif +} -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +struct cbmem_entry *get_cbmem_toc(void) { - printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); - return NULL; + uint64_t base, size; + cbmem_locate_table(&base, &size); + return (struct cbmem_entry *)(unsigned long)base; } -#endif #if !defined(__PRE_RAM__) void set_cbmem_table(uint64_t base, uint64_t size) @@ -85,10 +85,6 @@ void cbmem_init(u64 baseaddr, u64 size) struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); @@ -115,10 +111,6 @@ int cbmem_reinit(u64 baseaddr) printk(BIOS_DEBUG, "Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - return (cbmem_toc[0].magic == CBMEM_MAGIC); } @@ -211,22 +203,19 @@ void *cbmem_find(u32 id) /* Returns True if it was not initialized before. */ int cbmem_initialize(void) { + uint64_t base = 0, size = 0; int rv = 0; -#ifdef __PRE_RAM__ - extern unsigned long get_top_of_ram(void); - uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - uint64_t high_tables_size = HIGH_MEMORY_SIZE; -#endif + cbmem_locate_table(&base, &size); /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit(high_tables_base)) { + if (!cbmem_reinit(base)) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) /* Something went wrong, our high memory area got wiped */ if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; #endif - cbmem_init(high_tables_base, high_tables_size); + cbmem_init(base, size); rv = 1; } #ifndef __PRE_RAM__

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Patch set updated for coreboot: 54468a7 Move high_tables globals from arch
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3559 -gerrit commit 54468a70d951ab0322a0ce52c7b165c261eb9b9e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 14:11:08 2013 +0300 Move high_tables globals from arch Change-Id: I89c012bce1b86d0710748719a8840ec532ce6939 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/tables.c | 13 +------------ src/arch/x86/boot/tables.c | 12 +++--------- src/include/cbmem.h | 10 ++++------ src/lib/cbmem.c | 38 +++++++++++++++++++++++++++++++++----- src/lib/coreboot_table.c | 5 ----- 5 files changed, 41 insertions(+), 37 deletions(-) diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index 0fc7399..de6b6fa 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -29,13 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -/* - * TODO: "High" tables are a convention used on x86. Maybe we can - * clean up that naming at some point. - */ -uint64_t high_tables_base = 0; -uint64_t high_tables_size; - void cbmem_arch_init(void) { } @@ -44,11 +37,7 @@ struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer; - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); - } - - printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); + cbmem_base_check(); post_code(0x9d); diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 67d7911..ca1b61b 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -32,8 +32,6 @@ #include <lib.h> #include <smbios.h> -uint64_t high_tables_base = 0; -uint64_t high_tables_size; void cbmem_arch_init(void) { @@ -45,6 +43,7 @@ struct lb_memory *write_tables(void) { unsigned long low_table_start, low_table_end; unsigned long rom_table_start, rom_table_end; + u64 high_tables_base = 0; /* Even if high tables are configured, some tables are copied both to * the low and the high area, so payloads and OSes don't need to know @@ -53,13 +52,8 @@ struct lb_memory *write_tables(void) unsigned long high_table_pointer; #if !CONFIG_DYNAMIC_CBMEM - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n"); - // Are there any boards without? - // Stepan thinks we should die() here! - } - - printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base); + cbmem_base_check(); + high_tables_base = (u32)get_cbmem_toc(); #endif rom_table_start = 0xf0000; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 8ba1d21..3eeb6a1 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -125,19 +125,14 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); -#ifndef __PRE_RAM__ -/* Add the cbmem memory used to the memory tables. */ -struct lb_memory; -void cbmem_add_lb_mem(struct lb_memory *mem); -#endif /* __PRE_RAM__ */ #else /* !CONFIG_DYNAMIC_CBMEM */ #ifndef __PRE_RAM__ -extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); void backup_top_of_ram(uint64_t ramtop); void set_cbmem_table(uint64_t base, uint64_t size); +int cbmem_base_check(void); #endif int cbmem_reinit(u64 baseaddr); @@ -162,6 +157,9 @@ void *cbmem_find(u32 id); #ifndef __PRE_RAM__ /* Ramstage only functions. */ +/* Add the cbmem memory used to the memory tables. */ +struct lb_memory; +void cbmem_add_lb_mem(struct lb_memory *mem); void cbmem_list(void); void cbmem_arch_init(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index eb18725..963ca4d 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -21,6 +21,7 @@ #include <string.h> #include <bootstate.h> #include <cbmem.h> +#include <boot/coreboot_tables.h> #include <console/console.h> #include <cpu/x86/car.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) @@ -41,13 +42,20 @@ struct cbmem_entry { u64 size; } __attribute__((packed)); +#ifndef __PRE_RAM__ +static uint64_t bss_cbmem_base = 0; +static uint64_t bss_cbmem_size = 0; +#endif + static void cbmem_locate_table(uint64_t *base, uint64_t *size) { #ifdef __PRE_RAM__ get_cbmem_table(base, size); #else - *base = high_tables_base; - *size = high_tables_size; + if (!(bss_cbmem_base && bss_cbmem_size)) + get_cbmem_table(&bss_cbmem_base, &bss_cbmem_size); + *base = bss_cbmem_base; + *size = bss_cbmem_size; #endif } @@ -61,12 +69,12 @@ struct cbmem_entry *get_cbmem_toc(void) #if !defined(__PRE_RAM__) void set_cbmem_table(uint64_t base, uint64_t size) { - if (base == high_tables_base && size == high_tables_size) + if (base == bss_cbmem_base && size == bss_cbmem_size) return; printk(BIOS_DEBUG, "CBMEM region %llx-%llx\n", base, base+size-1); - high_tables_base = base; - high_tables_size = size; + bss_cbmem_base = base; + bss_cbmem_size = size; } #endif @@ -244,6 +252,26 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_post_device, NULL), }; +int cbmem_base_check(void) +{ + uint64_t base, size; + cbmem_locate_table(&base, &size); + if (!base) { + printk(BIOS_ERR, "ERROR: CBMEM Base is not set.\n"); + // Are there any boards without? + // Stepan thinks we should die() here! + } + printk(BIOS_DEBUG, "CBMEM Base is %llx.\n", base); + return !!base; +} + +void cbmem_add_lb_mem(struct lb_memory *mem) +{ + uint64_t base, size; + cbmem_locate_table(&base, &size); + lb_add_memory_range(mem, LB_MEM_TABLE, base, size); +} + void cbmem_list(void) { struct cbmem_entry *cbmem_toc; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3fad4c7..e5729ba 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -539,12 +539,7 @@ unsigned long write_coreboot_table( lb_add_memory_range(mem, LB_MEM_TABLE, rom_table_start, rom_table_end - rom_table_start); -#if CONFIG_DYNAMIC_CBMEM cbmem_add_lb_mem(mem); -#else /* CONFIG_DYNAMIC_CBMEM */ - lb_add_memory_range(mem, LB_MEM_TABLE, - high_tables_base, high_tables_size); -#endif /* CONFIG_DYNAMIC_CBMEM */ /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */

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Patch set updated for coreboot: f27e615 Store top_of_ram instead of cbmem_toc
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3557 -gerrit commit f27e6159395d560d3a20afed4a64537c59f9f5a7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:26:11 2013 +0300 Store top_of_ram instead of cbmem_toc Functions now backup and restore top_of_ram value. Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/ramtop.c | 6 ++++++ src/include/cbmem.h | 2 +- src/lib/cbmem.c | 8 -------- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.c | 9 ++++----- src/southbridge/amd/cimx/sb700/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb800/cfg.c | 8 ++++---- src/southbridge/amd/sb700/early_setup.c | 4 ++-- src/southbridge/amd/sb700/lpc.c | 4 ++-- src/southbridge/amd/sb800/early_setup.c | 4 ++-- src/southbridge/via/k8t890/early_car.c | 4 ++-- src/southbridge/via/k8t890/host_ctrl.c | 9 ++------- src/southbridge/via/k8t890/k8t890.h | 2 +- 13 files changed, 30 insertions(+), 38 deletions(-) diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c index fbd98a3..16faf48e 100644 --- a/src/arch/x86/boot/ramtop.c +++ b/src/arch/x86/boot/ramtop.c @@ -25,8 +25,14 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) } #if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) +void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) +{ + /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ +} + void set_top_of_ram(uint64_t ramtop) { + backup_top_of_ram(ramtop); set_cbmem_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 6517b94..b44a3fe 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -136,8 +136,8 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); +void backup_top_of_ram(uint64_t ramtop); void set_cbmem_table(uint64_t base, uint64_t size); -void set_cbmem_toc(struct cbmem_entry *); #endif void cbmem_init(u64 baseaddr, u64 size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 1a7a4e5..6bc081e 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -49,10 +49,6 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) return bss_cbmem_toc; } -void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) -{ - /* do nothing, this should be called by chipset to save TOC in NVRAM */ -} #else struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) @@ -101,10 +97,6 @@ void cbmem_init(u64 baseaddr, u64 size) for (;;) ; } - /* we don't need to call this in romstage, useful only from ramstage */ -#ifndef __PRE_RAM__ - set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr); -#endif memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); cbmem_toc[0] = (struct cbmem_entry) { diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..96861c9 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -95,7 +95,7 @@ int acpi_is_wakeup_early(void) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; @@ -105,7 +105,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } #endif diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index e4cbc07..f78af1b 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -40,9 +40,9 @@ int acpi_get_sleep_type(void) } #endif -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ for (i = 0; i<4; i++) { @@ -132,7 +132,7 @@ void hudson_enable(device_t dev) } } -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; @@ -142,10 +142,9 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } - struct chip_operations southbridge_amd_agesa_hudson_ops = { CHIP_NAME("ATI HUDSON") .enable_dev = hudson_enable, diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 826ac05..91d7d2f 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -27,9 +27,9 @@ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 90ad5a9..0042974 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -37,9 +37,9 @@ int acpi_get_sleep_type(void) #endif #ifndef __PRE_RAM__ -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ printk(BIOS_DEBUG, "dword=%x\n", dword); for (i = 0; i<4; i++) { @@ -51,7 +51,7 @@ void set_cbmem_toc(struct cbmem_entry *toc) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { u32 xdata = 0; int xnvram_pos = 0xf8, xi; @@ -61,7 +61,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } /** diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index a16fc9f..f6612a2 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -731,7 +731,7 @@ int acpi_is_wakeup_early(void) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; @@ -741,7 +741,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 23775b0..a175210 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -84,9 +84,9 @@ static void lpc_init(device_t dev) rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 4f0c98a..b860096 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -675,7 +675,7 @@ static int acpi_is_wakeup_early(void) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; @@ -685,7 +685,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } #endif diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 000a532..8672801 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -183,6 +183,6 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +unsigned long get_top_of_ram(void) { + return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 151a228..74351bc 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -113,13 +113,8 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) { pci_write_config8(dev, 0xa6, 0x83); } -#if 0 -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); -} -#endif -void set_cbmem_toc(struct cbmem_entry *toc) { - outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +void backup_top_of_ram(uint64_t ramtop) { + outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h index f0d0fe0..7f83ffa 100644 --- a/src/southbridge/via/k8t890/k8t890.h +++ b/src/southbridge/via/k8t890/k8t890.h @@ -31,7 +31,7 @@ /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 -#define K8T890_NVRAM_CBMEM_TOC 0xfc +#define K8T890_NVRAM_TOP_OF_RAM 0xfc #define K8T890_MMCONFIG_MBAR 0x61 #define K8T890_MULTIPLE_FN_EN 0x4f

1 0

New patch to review for coreboot: 90d6964 Fix compile errors in AMD Fam16 AGESA code with gcc 4.5.
by Wei Hu 04 Sep '13

04 Sep '13

Wei Hu (wei(a)aristanetworks.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3899 -gerrit commit 90d6964901e3082ae78fc6face3a38048839dda8 Author: Wei Hu <wei(a)aristanetworks.com> Date: Wed Sep 4 03:01:45 2013 -0700 Fix compile errors in AMD Fam16 AGESA code with gcc 4.5. Change-Id: I27f5b8d5d0e5559e06bf8bddbeefe24bfe71c384 Signed-off-by: Wei Hu <wei(a)aristanetworks.com> --- src/include/usbdebug.h | 1 - src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h | 4 ++-- src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h | 4 ++-- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index 926d658..36fd9cf 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -24,7 +24,6 @@ #define EHCI_BAR_INDEX 0x10 #define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ -typedef u32 pci_devfn_t; pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx); unsigned long pci_ehci_base_regs(pci_devfn_t dev); void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h index 913802f..38d7d16 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuHtc.h @@ -114,12 +114,12 @@ typedef F_HTC_INIT *PF_HTC_INIT; * Each supported Family must provide an implementation for all methods in this interface, even if the * implementation is a CommonReturn(). */ -typedef struct _HTC_FAMILY_SERVICES { +struct _HTC_FAMILY_SERVICES { UINT16 Revision; ///< Interface version // Public Methods. PF_HTC_IS_SUPPORTED IsHtcSupported; ///< Method: Family specific call to check if HTC is supported. PF_HTC_INIT EnableHtcOnSocket; ///< Method: Family specific call to enable HTC. -} HTC_FAMILY_SERVICES; +}; /*---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h index ad2a5e5..44f3837 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuPsi.h @@ -114,12 +114,12 @@ typedef F_PSI_INIT *PF_PSI_INIT; * Each supported Family must provide an implementation for all methods in this interface, even if the * implementation is a CommonReturn(). */ -typedef struct _PSI_FAMILY_SERVICES { +struct _PSI_FAMILY_SERVICES { UINT16 Revision; ///< Interface version // Public Methods. PF_PSI_IS_SUPPORTED IsPsiSupported; ///< Method: Family specific call to check if PSI is supported. PF_PSI_INIT EnablePsiOnSocket; ///< Method: Family specific call to enable PSI. -} PSI_FAMILY_SERVICES; +}; /*----------------------------------------------------------------------------------------

1 0

Patch set updated for coreboot: 244fae5 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
by Andrew Wu 04 Sep '13

04 Sep '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3896 -gerrit commit 244fae51388f401f52f42a9f0b7ada557d6e3b85 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Sep 3 20:39:48 2013 +0800 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify the xcompile script to search for cpp program path, and pass it to SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler). This is needed, so the crossgcc toolchain to build the SeaBIOS payload under Mac OSX. OSX ships a cpp program, but it works differently from GNU CPP, so we need to override it. Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- Makefile | 1 + src/arch/x86/Makefile.inc | 1 + util/xcompile/xcompile | 1 + 3 files changed, 3 insertions(+) diff --git a/Makefile b/Makefile index dec32e5..b709d14 100644 --- a/Makefile +++ b/Makefile @@ -126,6 +126,7 @@ ARCH-$(CONFIG_ARCH_X86) := i386 ifneq ($(INNER_SCANBUILD),y) CC := $(CC_$(ARCH-y)) endif +CPP := $(CPP_$(ARCH-y)) AS := $(AS_$(ARCH-y)) LD := $(LD_$(ARCH-y)) NM := $(NM_$(ARCH-y)) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b3b82b9..dee56c5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -427,6 +427,7 @@ seabios: HOSTCC="$(HOSTCC)" \ CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ + AS="$(AS)" CPP="$(CPP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ OUT=$(abspath $(obj)) IASL="$(IASL)" diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index ff12217..c4b8f54 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -117,6 +117,7 @@ report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) CC_${TARCH}:=${GCCPREFIX}gcc ${CFLAGS} +CPP_${TARCH}:=${GCCPREFIX}cpp AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} NM_${TARCH}:=${GCCPREFIX}nm

1 0

Patch set updated for coreboot: ca5c653 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
by Paul Menzel 03 Sep '13

03 Sep '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3896 -gerrit commit ca5c65322594fac69a72fbcd6a3a04f456affa23 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Sep 3 20:39:48 2013 +0800 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify the xcompile script to search for cpp program path, and pass it to SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler). This is needed, so the crossgcc toolchain to build the SeaBIOS payload under Mac OSX. OSX ships a cpp program, but it works differently from GNU CPP, so we need to override it. Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- Makefile | 1 + src/arch/x86/Makefile.inc | 1 + util/xcompile/xcompile | 1 + 3 files changed, 3 insertions(+) diff --git a/Makefile b/Makefile index dec32e5..b709d14 100644 --- a/Makefile +++ b/Makefile @@ -126,6 +126,7 @@ ARCH-$(CONFIG_ARCH_X86) := i386 ifneq ($(INNER_SCANBUILD),y) CC := $(CC_$(ARCH-y)) endif +CPP := $(CPP_$(ARCH-y)) AS := $(AS_$(ARCH-y)) LD := $(LD_$(ARCH-y)) NM := $(NM_$(ARCH-y)) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b3b82b9..f8e9384 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -427,6 +427,7 @@ seabios: HOSTCC="$(HOSTCC)" \ CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ + AS=$(AS) CPP="$(CPP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ OUT=$(abspath $(obj)) IASL="$(IASL)" diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index ff12217..c4b8f54 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -117,6 +117,7 @@ report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) CC_${TARCH}:=${GCCPREFIX}gcc ${CFLAGS} +CPP_${TARCH}:=${GCCPREFIX}cpp AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} NM_${TARCH}:=${GCCPREFIX}nm

1 0

Patch merged into coreboot/master: 9a91ba1 libpayload: reduce libcbfs verbosity
by gerrit＠coreboot.org 03 Sep '13

03 Sep '13

the following patch was just integrated into master: commit 9a91ba199479b25f83bbf7691d8b6acf6eace34e Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Mar 14 15:11:34 2013 +0100 libpayload: reduce libcbfs verbosity Prettier in real-world payloads (ie. FILO) Change-Id: I9ed968fe527c5d46090e707e2d89b7406a43662e Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/3887 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3887 for details. -gerrit

1 0

New patch to review for coreboot: b99b1f0 Searching for cpp program path and pass it to SeaBIOS Makefile.
by Andrew Wu 03 Sep '13

03 Sep '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3896 -gerrit commit b99b1f054d9c704100479ccdfa6879994f195c00 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Tue Sep 3 20:39:48 2013 +0800 Searching for cpp program path and pass it to SeaBIOS Makefile. SeaBIOS Makefile requires cpp(C Preprocessor) to build. Modify xcompile script to search for cpp program path, and pass it to SeaBIOS Makefile.inc. Also pass as(GNU assembler) program path. This patch makes using crossgcc toolchain to build SeaBIOS payload under Mac OSX works. OSX has built-in cpp program, but it works differently from GNU CPP, so we need to override it. Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- Makefile | 1 + src/arch/x86/Makefile.inc | 1 + util/xcompile/xcompile | 1 + 3 files changed, 3 insertions(+) diff --git a/Makefile b/Makefile index dec32e5..b709d14 100644 --- a/Makefile +++ b/Makefile @@ -126,6 +126,7 @@ ARCH-$(CONFIG_ARCH_X86) := i386 ifneq ($(INNER_SCANBUILD),y) CC := $(CC_$(ARCH-y)) endif +CPP := $(CPP_$(ARCH-y)) AS := $(AS_$(ARCH-y)) LD := $(LD_$(ARCH-y)) NM := $(NM_$(ARCH-y)) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index b3b82b9..f8e9384 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -427,6 +427,7 @@ seabios: HOSTCC="$(HOSTCC)" \ CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \ OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ + AS=$(AS) CPP="$(CPP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ OUT=$(abspath $(obj)) IASL="$(IASL)" diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index ff12217..c4b8f54 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -117,6 +117,7 @@ report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) CC_${TARCH}:=${GCCPREFIX}gcc ${CFLAGS} +CPP_${TARCH}:=${GCCPREFIX}cpp AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} NM_${TARCH}:=${GCCPREFIX}nm

1 0

New patch to review for coreboot: 43dfe20 AMD: Fix to call set_top_of_ram just once
by Kyösti Mälkki 03 Sep '13

03 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3895 -gerrit commit 43dfe20722d73975b2247356c705fbfcf240cef2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Sep 3 05:25:57 2013 +0300 AMD: Fix to call set_top_of_ram just once Our set_top_of_ram_once() only sets a global variable, if it was not already set. We can postpone the call outside the loops and make just one call with correct parameter. As set_top_of_ram() now only gets called once, it is no longer necessary to check if high_tables_base was already set. Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/ramtop.c | 8 +++----- src/include/cbmem.h | 2 +- src/northbridge/amd/agesa/family10/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family12/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family14/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family15/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family15tn/northbridge.c | 18 ++++++++---------- src/northbridge/amd/agesa/family16kb/northbridge.c | 18 ++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 19 ++++++++----------- src/northbridge/amd/amdk8/northbridge.c | 18 ++++++++---------- 10 files changed, 68 insertions(+), 87 deletions(-) diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c index d433709..cbd43dc 100644 --- a/src/arch/x86/boot/ramtop.c +++ b/src/arch/x86/boot/ramtop.c @@ -19,12 +19,10 @@ #include <cbmem.h> #if !CONFIG_DYNAMIC_CBMEM -void set_top_of_ram_once(uint64_t ramtop) +void set_top_of_ram(uint64_t ramtop) { - if (high_tables_base == 0) { - high_tables_base = ramtop - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - } + high_tables_base = ramtop - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5e438f3..815c249 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -135,7 +135,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; -void set_top_of_ram_once(uint64_t ramtop); +void set_top_of_ram(uint64_t ramtop); void set_cbmem_toc(struct cbmem_entry *); #endif diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 602d473..1c7e547 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -914,6 +914,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1036,11 +1037,8 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -1057,15 +1055,15 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 4c230f1..42b4b3d 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -590,6 +590,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -722,11 +723,8 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -743,16 +741,16 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index fbf8e44..7cc812b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -575,6 +575,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -716,11 +717,8 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -737,16 +735,16 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for (link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index bdd6939..a8cc1cc 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -684,6 +684,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -807,11 +808,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -828,15 +826,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 736e634..b55d52b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -671,6 +671,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -793,11 +794,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -815,15 +813,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 266319c..b8bba50 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -677,6 +677,7 @@ static void domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -799,11 +800,8 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } basek = mmio_basek; } @@ -821,15 +819,15 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8dbb480..6bcab41 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -877,6 +877,7 @@ static void amdfam10_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1037,12 +1038,8 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1070,15 +1067,15 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif for(link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c7321a4..8f0a11b 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -874,6 +874,7 @@ static void amdk8_domain_set_resources(device_t dev) #endif unsigned long mmio_basek; u32 pci_tolm; + u64 ramtop = 0; int i, idx; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; @@ -1042,11 +1043,8 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(mmio_basek * 1024); -#endif + if (!ramtop) + ramtop = mmio_basek * 1024; } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) @@ -1071,15 +1069,15 @@ static void amdk8_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); -#if CONFIG_GFXUMA - set_top_of_ram_once(uma_memory_base); -#else - set_top_of_ram_once(limitk * 1024); -#endif + if (!ramtop) + ramtop = limitk * 1024; } #if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); #endif assign_resources(dev->link_list);

1 0

New patch to review for coreboot: da4cebc AMD: Remove references to global high_tables_base
by Kyösti Mälkki 03 Sep '13

03 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3894 -gerrit commit da4cebc5d3a5ce207773ad245b8430986d6d99ae Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 27 08:20:09 2013 +0300 AMD: Remove references to global high_tables_base Prepare for removal of globals high_tables_base and _size by replacing the references with a helper function. Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/Makefile.inc | 1 + src/arch/x86/boot/ramtop.c | 31 ++++++++++++++++++++++ src/include/cbmem.h | 1 + src/northbridge/amd/agesa/family10/northbridge.c | 18 +++---------- src/northbridge/amd/agesa/family12/northbridge.c | 23 +++------------- src/northbridge/amd/agesa/family14/northbridge.c | 22 +++------------ src/northbridge/amd/agesa/family15/northbridge.c | 18 +++---------- src/northbridge/amd/agesa/family15tn/northbridge.c | 18 +++---------- src/northbridge/amd/agesa/family16kb/northbridge.c | 18 +++---------- src/northbridge/amd/amdfam10/northbridge.c | 18 +++---------- src/northbridge/amd/amdk8/northbridge.c | 18 +++---------- 11 files changed, 65 insertions(+), 121 deletions(-) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 7b67e49..6778ad8 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += boot.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c ramstage-y += tables.c +ramstage-y += ramtop.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c new file mode 100644 index 0000000..d433709 --- /dev/null +++ b/src/arch/x86/boot/ramtop.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <console/console.h> +#include <cbmem.h> + +#if !CONFIG_DYNAMIC_CBMEM +void set_top_of_ram_once(uint64_t ramtop) +{ + if (high_tables_base == 0) { + high_tables_base = ramtop - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + } + printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", + high_tables_base, high_tables_size); +} +#endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 982a6d8..5e438f3 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -135,6 +135,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; +void set_top_of_ram_once(uint64_t ramtop); void set_cbmem_toc(struct cbmem_entry *); #endif diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index ceb1d50..602d473 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1036,17 +1036,11 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -1063,15 +1057,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 621246f..4c230f1 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -722,20 +722,12 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), - high_tables_base); - } } - basek = mmio_basek; } if ((basek + sizek) <= 4*1024*1024) { @@ -751,20 +743,13 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base); + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); - printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", - high_tables_size); #if CONFIG_GFXUMA uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e7de273..fbf8e44 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -716,19 +716,12 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base == 0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } - basek = mmio_basek; } if ((basek + sizek) <= 4 * 1024 * 1024) { @@ -744,20 +737,13 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); - if (high_tables_base == 0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base); + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); - printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", - high_tables_size); #if CONFIG_GFXUMA uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 78e9966..bdd6939 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -807,17 +807,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -834,15 +828,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 0a69ad8..736e634 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -793,17 +793,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -821,15 +815,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index c27a1b2..266319c 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -799,17 +799,11 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - (u32)(high_tables_size / 1024), high_tables_base); - } } basek = mmio_basek; } @@ -827,15 +821,11 @@ static void domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 3f7ca25..8dbb480 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1038,17 +1038,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_MEMORY_SIZE / 1024, high_tables_base); - } } #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1076,15 +1070,11 @@ static void amdfam10_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 9610587..c7321a4 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1042,17 +1042,11 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(mmio_basek * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_MEMORY_SIZE / 1024, high_tables_base); - } } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) @@ -1077,15 +1071,11 @@ static void amdk8_domain_set_resources(device_t dev) idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); - if (high_tables_base==0) { - /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA - high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; + set_top_of_ram_once(uma_memory_base); #else - high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; + set_top_of_ram_once(limitk * 1024); #endif - high_tables_size = HIGH_MEMORY_SIZE; - } } #if CONFIG_GFXUMA

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coreboot-gerrit September 2013