coreboot-gerrit September 2013

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Patch set updated for coreboot: 3e8c2d6 Unify get_top_of_ram and get_cbmem_toc
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3904 -gerrit commit 3e8c2d61bd93e515540e434e378b1d5ecebbeb09 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 01:11:16 2013 +0300 Unify get_top_of_ram and get_cbmem_toc Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/Makefile.inc | 2 ++ src/arch/x86/boot/ramtop.c | 8 +++++++- src/include/cbmem.h | 4 +++- src/lib/cbmem.c | 1 - src/mainboard/emulation/qemu-i440fx/memory.c | 8 +------- src/northbridge/amd/lx/northbridge.h | 1 - src/northbridge/amd/lx/northbridgeinit.c | 3 ++- src/northbridge/intel/e7505/raminit.c | 1 + src/northbridge/intel/e7505/raminit.h | 1 - src/northbridge/intel/gm45/gm45.h | 1 - src/northbridge/intel/gm45/ram_calc.c | 3 ++- src/northbridge/intel/haswell/raminit.h | 1 - src/northbridge/intel/i945/raminit.c | 5 ----- src/northbridge/intel/i945/raminit.h | 1 - src/northbridge/intel/sandybridge/northbridge.c | 10 +--------- src/northbridge/intel/sandybridge/raminit.c | 5 ----- src/northbridge/intel/sandybridge/raminit.h | 1 - src/northbridge/via/vx900/early_vx900.c | 5 ----- src/northbridge/via/vx900/early_vx900.h | 1 - 19 files changed, 19 insertions(+), 43 deletions(-) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 6778ad8..89faabe 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,3 +1,5 @@ +romstage-y += ramtop.c + ramstage-y += boot.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c index 7ac2ee2..fbd98a3 100644 --- a/src/arch/x86/boot/ramtop.c +++ b/src/arch/x86/boot/ramtop.c @@ -18,7 +18,13 @@ #include <console/console.h> #include <cbmem.h> -#if !CONFIG_DYNAMIC_CBMEM +unsigned long __attribute__((weak)) get_top_of_ram(void) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); + return 0; +} + +#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) void set_top_of_ram(uint64_t ramtop) { set_cbmem_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 46739de..f991168 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -143,12 +143,14 @@ void set_cbmem_toc(struct cbmem_entry *); void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); -extern struct cbmem_entry *get_cbmem_toc(void); +struct cbmem_entry *get_cbmem_toc(void); #endif /* CONFIG_DYNAMIC_CBMEM */ /* Common API between cbmem and dynamic cbmem. */ +unsigned long get_top_of_ram(void); + /* By default cbmem is attempted to be recovered. Returns 0 if cbmem was * recovered or 1 if cbmem had to be reinitialized. */ int cbmem_initialize(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 1a7a4e5..bf32be0 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -222,7 +222,6 @@ int cbmem_initialize(void) int rv = 0; #ifdef __PRE_RAM__ - extern unsigned long get_top_of_ram(void); uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; uint64_t high_tables_size = HIGH_MEMORY_SIZE; #endif diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 000a0f6..027deb9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -40,18 +40,12 @@ static unsigned long qemu_get_memory_size(void) return tomk; } -unsigned long get_top_of_ram(void); unsigned long get_top_of_ram(void) { return qemu_get_memory_size() * 1024; } -#if !CONFIG_DYNAMIC_CBMEM -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} -#else +#if CONFIG_DYNAMIC_CBMEM void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h index fd62184..25075bd 100644 --- a/src/northbridge/amd/lx/northbridge.h +++ b/src/northbridge/amd/lx/northbridge.h @@ -28,7 +28,6 @@ int sizeram(void); /* northbridgeinit.c */ void northbridge_init_early(void); -uint32_t get_top_of_ram(void); /* pll_reset.c */ unsigned int GeodeLinkSpeed(void); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 3768777..f4c13f7 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -30,6 +30,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> +#include <cbmem.h> struct gliutable { unsigned long desc_name; @@ -713,7 +714,7 @@ static void setup_lx_cache(void) wbinvd(); } -uint32_t get_top_of_ram(void) +unsigned long get_top_of_ram(void) { struct gliutable *gl = 0; uint32_t systop; diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index ae02a7c..3d4dfe2 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -25,6 +25,7 @@ #include <assert.h> #include <spd.h> #include <sdram_mode.h> +#include <cbmem.h> #include "raminit.h" #include "e7505.h" diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index f9ba796..8eb4990 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -20,7 +20,6 @@ void e7505_mch_scrub_ecc(unsigned long ret_addr); void e7505_mch_done(const struct mem_controller *memctrl); int e7505_mch_is_ready(void); -unsigned long get_top_of_ram(void); /* Mainboard exports this. */ int spd_read_byte(unsigned device, unsigned address); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 2dffcad..227baef 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -422,7 +422,6 @@ void gm45_late_init(stepping_t); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); -u32 get_top_of_ram(void); void init_iommu(void); #endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 28e947b..a029020 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -26,6 +26,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> +#include <cbmem.h> #include "gm45.h" /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ @@ -83,7 +84,7 @@ u32 decode_igd_gtt_size(const u32 gsm) } } -u32 get_top_of_ram(void) +unsigned long get_top_of_ram(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 46be570..706c286 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -23,7 +23,6 @@ #include "pei_data.h" void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_haswell_errata(void); /* save_mrc_data() must be called after cbmem has been initialized. */ void save_mrc_data(struct pei_data *pei_data); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1a0684..b50f1d8 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,11 +28,6 @@ #include "i945.h" #include <cbmem.h> -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2d8ef9e..9eb4193 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -69,7 +69,6 @@ struct sys_info { void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); -unsigned long get_top_of_ram(void); int fixup_i945_errata(void); void udelay(u32 us); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4cd86cd..a03b8a6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,21 +51,13 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -static unsigned long get_top_of_ram(void) +unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); return (unsigned long) tom; } -struct cbmem_entry *get_cbmem_toc(void) -{ - static struct cbmem_entry *toc = NULL; - if (!toc) - toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); - return toc; -} - /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3eb2fb3..3b321d7 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -305,11 +305,6 @@ void sdram_initialize(struct pei_data *pei_data) save_mrc_data(pei_data); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 23bdbd9..2e9b1f3 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -30,7 +30,6 @@ struct sys_info { } __attribute__ ((packed)); void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_sandybridge_errata(void); #endif /* RAMINIT_H */ diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 2439c8d..2896680 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -27,11 +27,6 @@ unsigned long get_top_of_ram(void) return (((unsigned long)reg_tom) << 24) - (256 << 20); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /** * \brief Enable accessing of PCI configuration space for all devices. * diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h index dcb24b5..46e3023 100644 --- a/src/northbridge/via/vx900/early_vx900.h +++ b/src/northbridge/via/vx900/early_vx900.h @@ -61,7 +61,6 @@ #define RAMINIT_USE_HW_RXCR_CALIB 0 #define RAMINIT_USE_HW_MRS_SEQ 0 -unsigned long get_top_of_ram(void); void enable_smbus(void); void dump_spd_data(spd_raw_data spd);

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Patch set updated for coreboot: 5597188 Add get_cbmem_table for x86
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3558 -gerrit commit 5597188fd6e0e6807fb6935893356acb560fae09 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:31:39 2013 +0300 Add get_cbmem_table for x86 For x86 CBMEM tables are located right below top of low ram and have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation. NOTE: Boards will need to have get_top_of_ram() added for ramstage. Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/ramtop.c | 15 +++++++++++++++ src/include/cbmem.h | 1 + src/lib/cbmem.c | 40 +++++++++++++++------------------------- 3 files changed, 31 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c index 16faf48e..84bd6d9 100644 --- a/src/arch/x86/boot/ramtop.c +++ b/src/arch/x86/boot/ramtop.c @@ -24,6 +24,21 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) return 0; } +#if !CONFIG_DYNAMIC_CBMEM +void get_cbmem_table(uint64_t *base, uint64_t *size) +{ + uint64_t top_of_ram = get_top_of_ram(); + + if (top_of_ram >= HIGH_MEMORY_SIZE) { + *base = top_of_ram - HIGH_MEMORY_SIZE; + *size = HIGH_MEMORY_SIZE; + } else { + *base = 0; + *size = 0; + } +} +#endif + #if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) { diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 87b7e9b..9638a03 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -144,6 +144,7 @@ void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); struct cbmem_entry *get_cbmem_toc(void); +void get_cbmem_table(uint64_t *base, uint64_t *size); #endif /* CONFIG_DYNAMIC_CBMEM */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 27c1a27..3f8f243 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -41,22 +41,22 @@ struct cbmem_entry { u64 size; } __attribute__((packed)); -#ifndef __PRE_RAM__ -static struct cbmem_entry *bss_cbmem_toc; - -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +static void cbmem_locate_table(uint64_t *base, uint64_t *size) { - return bss_cbmem_toc; -} - +#ifdef __PRE_RAM__ + get_cbmem_table(base, size); #else + *base = high_tables_base; + *size = high_tables_size; +#endif +} -struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +struct cbmem_entry *get_cbmem_toc(void) { - printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); - return NULL; + uint64_t base, size; + cbmem_locate_table(&base, &size); + return (struct cbmem_entry *)(unsigned long)base; } -#endif #if !defined(__PRE_RAM__) void set_cbmem_table(uint64_t base, uint64_t size) @@ -85,10 +85,6 @@ void cbmem_init(u64 baseaddr, u64 size) struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); @@ -115,10 +111,6 @@ int cbmem_reinit(u64 baseaddr) printk(BIOS_DEBUG, "Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); -#ifndef __PRE_RAM__ - bss_cbmem_toc = cbmem_toc; -#endif - return (cbmem_toc[0].magic == CBMEM_MAGIC); } @@ -211,21 +203,19 @@ void *cbmem_find(u32 id) /* Returns True if it was not initialized before. */ int cbmem_initialize(void) { + uint64_t base = 0, size = 0; int rv = 0; -#ifdef __PRE_RAM__ - uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - uint64_t high_tables_size = HIGH_MEMORY_SIZE; -#endif + cbmem_locate_table(&base, &size); /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit(high_tables_base)) { + if (!cbmem_reinit(base)) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) /* Something went wrong, our high memory area got wiped */ if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; #endif - cbmem_init(high_tables_base, high_tables_size); + cbmem_init(base, size); rv = 1; } #ifndef __PRE_RAM__

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Patch set updated for coreboot: 8429dff Store top_of_ram instead of cbmem_toc
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3557 -gerrit commit 8429dffde5778b1ebb4df88165471b1dde63f052 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:26:11 2013 +0300 Store top_of_ram instead of cbmem_toc Functions now backup and restore top_of_ram value. Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/ramtop.c | 6 ++++++ src/include/cbmem.h | 2 +- src/lib/cbmem.c | 8 -------- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.c | 9 ++++----- src/southbridge/amd/cimx/sb700/lpc.c | 4 ++-- src/southbridge/amd/cimx/sb800/cfg.c | 8 ++++---- src/southbridge/amd/sb700/early_setup.c | 4 ++-- src/southbridge/amd/sb700/lpc.c | 4 ++-- src/southbridge/amd/sb800/early_setup.c | 4 ++-- src/southbridge/via/k8t890/early_car.c | 4 ++-- src/southbridge/via/k8t890/host_ctrl.c | 9 ++------- src/southbridge/via/k8t890/k8t890.h | 2 +- 13 files changed, 30 insertions(+), 38 deletions(-) diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c index fbd98a3..16faf48e 100644 --- a/src/arch/x86/boot/ramtop.c +++ b/src/arch/x86/boot/ramtop.c @@ -25,8 +25,14 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) } #if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) +void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) +{ + /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ +} + void set_top_of_ram(uint64_t ramtop) { + backup_top_of_ram(ramtop); set_cbmem_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index f991168..87b7e9b 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -136,8 +136,8 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); +void backup_top_of_ram(uint64_t ramtop); void set_cbmem_table(uint64_t base, uint64_t size); -void set_cbmem_toc(struct cbmem_entry *); #endif void cbmem_init(u64 baseaddr, u64 size); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index bf32be0..27c1a27 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -49,10 +49,6 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) return bss_cbmem_toc; } -void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) -{ - /* do nothing, this should be called by chipset to save TOC in NVRAM */ -} #else struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) @@ -101,10 +97,6 @@ void cbmem_init(u64 baseaddr, u64 size) for (;;) ; } - /* we don't need to call this in romstage, useful only from ramstage */ -#ifndef __PRE_RAM__ - set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr); -#endif memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); cbmem_toc[0] = (struct cbmem_entry) { diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..96861c9 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -95,7 +95,7 @@ int acpi_is_wakeup_early(void) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; @@ -105,7 +105,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } #endif diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index e4cbc07..f78af1b 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -40,9 +40,9 @@ int acpi_get_sleep_type(void) } #endif -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ for (i = 0; i<4; i++) { @@ -132,7 +132,7 @@ void hudson_enable(device_t dev) } } -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xf8, xi; @@ -142,10 +142,9 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } - struct chip_operations southbridge_amd_agesa_hudson_ops = { CHIP_NAME("ATI HUDSON") .enable_dev = hudson_enable, diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 826ac05..91d7d2f 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -27,9 +27,9 @@ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 90ad5a9..0042974 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -37,9 +37,9 @@ int acpi_get_sleep_type(void) #endif #ifndef __PRE_RAM__ -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ printk(BIOS_DEBUG, "dword=%x\n", dword); for (i = 0; i<4; i++) { @@ -51,7 +51,7 @@ void set_cbmem_toc(struct cbmem_entry *toc) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { u32 xdata = 0; int xnvram_pos = 0xf8, xi; @@ -61,7 +61,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } /** diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index a16fc9f..f6612a2 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -731,7 +731,7 @@ int acpi_is_wakeup_early(void) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; @@ -741,7 +741,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 23775b0..a175210 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -84,9 +84,9 @@ static void lpc_init(device_t dev) rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); } -void set_cbmem_toc(struct cbmem_entry *toc) +void backup_top_of_ram(uint64_t ramtop) { - u32 dword = (u32) toc; + u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; for (i = 0; i<4; i++) { outb(nvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 4f0c98a..b860096 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -675,7 +675,7 @@ static int acpi_is_wakeup_early(void) } #endif -struct cbmem_entry *get_cbmem_toc(void) +unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; @@ -685,7 +685,7 @@ struct cbmem_entry *get_cbmem_toc(void) xdata |= inb(BIOSRAM_DATA) << (xi *8); xnvram_pos++; } - return (struct cbmem_entry *) xdata; + return (unsigned long) xdata; } #endif diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index 000a532..8672801 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -183,6 +183,6 @@ static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +unsigned long get_top_of_ram(void) { + return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 151a228..74351bc 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -113,13 +113,8 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) { pci_write_config8(dev, 0xa6, 0x83); } -#if 0 -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); -} -#endif -void set_cbmem_toc(struct cbmem_entry *toc) { - outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +void backup_top_of_ram(uint64_t ramtop) { + outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h index f0d0fe0..7f83ffa 100644 --- a/src/southbridge/via/k8t890/k8t890.h +++ b/src/southbridge/via/k8t890/k8t890.h @@ -31,7 +31,7 @@ /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 -#define K8T890_NVRAM_CBMEM_TOC 0xfc +#define K8T890_NVRAM_TOP_OF_RAM 0xfc #define K8T890_MMCONFIG_MBAR 0x61 #define K8T890_MULTIPLE_FN_EN 0x4f

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New patch to review for coreboot: 0b014d0 Makefile: Check $CC variable returned from xcompile is not empty.
by Andrew Wu 04 Sep '13

04 Sep '13

Andrew Wu (arw(a)dmp.com.tw) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3905 -gerrit commit 0b014d0cdea2acd5a2dd4174bbbdfb6cf4107294 Author: Andrew Wu <arw(a)dmp.com.tw> Date: Thu Sep 5 00:21:11 2013 +0800 Makefile: Check $CC variable returned from xcompile is not empty. If xcompile can't find out suitable GCC compiler for i386/armv7, it will not set $CC_i386/$CC_armv7 variable. Makefile sets $CC variable from xcompile, and will print strange error messages when executing $CC program if $CC is empty. Add checking to avoid this problem. Change-Id: Ia8d481d76ca52f3351cb99f05779d06947161c5d Signed-off-by: Andrew Wu <arw(a)dmp.com.tw> --- Makefile | 5 +++++ payloads/libpayload/Makefile | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/Makefile b/Makefile index dec32e5..3b4d931 100644 --- a/Makefile +++ b/Makefile @@ -137,6 +137,11 @@ AR := $(AR_$(ARCH-y)) CFLAGS += $(CFLAGS_$(ARCH-y)) +ifeq ($(CC),) +$(shell rm .xcompile) +$(error no suitable GCC for $(ARCH-y)) +endif + LIBGCC_FILE_NAME := $(shell test -r `$(CC) -print-libgcc-file-name` && \ $(CC) -print-libgcc-file-name) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index bfa1abf..b319840 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -115,6 +115,11 @@ AR := $(AR_$(ARCH-y)) CFLAGS += $(CFLAGS_$(ARCH-y)) +ifeq ($(CC),) +$(shell rm .xcompile) +$(error no suitable GCC for $(ARCH-y)) +endif + LIBGCC_FILE_NAME := $(shell test -r `$(CC) -print-libgcc-file-name` && \ $(CC) -print-libgcc-file-name)

1 0

New patch to review for coreboot: 7852806 Unify get_top_of_ram and get_cbmem_toc
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3904 -gerrit commit 7852806c410bb3605740333ef0d6598696f23925 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 01:11:16 2013 +0300 Unify get_top_of_ram and get_cbmem_toc Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/Makefile.inc | 2 ++ src/arch/x86/boot/ramtop.c | 8 +++++++- src/include/cbmem.h | 3 ++- src/mainboard/emulation/qemu-i440fx/memory.c | 8 +------- src/northbridge/amd/lx/northbridge.h | 1 - src/northbridge/amd/lx/northbridgeinit.c | 2 +- src/northbridge/intel/e7505/raminit.h | 1 - src/northbridge/intel/gm45/gm45.h | 1 - src/northbridge/intel/gm45/ram_calc.c | 2 +- src/northbridge/intel/haswell/raminit.h | 1 - src/northbridge/intel/i945/raminit.c | 5 ----- src/northbridge/intel/i945/raminit.h | 1 - src/northbridge/intel/sandybridge/northbridge.c | 10 +--------- src/northbridge/intel/sandybridge/raminit.c | 5 ----- src/northbridge/intel/sandybridge/raminit.h | 1 - src/northbridge/via/vx900/early_vx900.c | 5 ----- src/northbridge/via/vx900/early_vx900.h | 1 - 17 files changed, 15 insertions(+), 42 deletions(-) diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 6778ad8..89faabe 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,3 +1,5 @@ +romstage-y += ramtop.c + ramstage-y += boot.c ramstage-$(CONFIG_MULTIBOOT) += multiboot.c ramstage-y += gdt.c diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c index 7ac2ee2..fbd98a3 100644 --- a/src/arch/x86/boot/ramtop.c +++ b/src/arch/x86/boot/ramtop.c @@ -18,7 +18,13 @@ #include <console/console.h> #include <cbmem.h> -#if !CONFIG_DYNAMIC_CBMEM +unsigned long __attribute__((weak)) get_top_of_ram(void) +{ + printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); + return 0; +} + +#if !CONFIG_DYNAMIC_CBMEM && !defined(__PRE_RAM__) void set_top_of_ram(uint64_t ramtop) { set_cbmem_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 46739de..6517b94 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -143,7 +143,8 @@ void set_cbmem_toc(struct cbmem_entry *); void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); -extern struct cbmem_entry *get_cbmem_toc(void); +unsigned long get_top_of_ram(void); +struct cbmem_entry *get_cbmem_toc(void); #endif /* CONFIG_DYNAMIC_CBMEM */ diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index 000a0f6..027deb9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -40,18 +40,12 @@ static unsigned long qemu_get_memory_size(void) return tomk; } -unsigned long get_top_of_ram(void); unsigned long get_top_of_ram(void) { return qemu_get_memory_size() * 1024; } -#if !CONFIG_DYNAMIC_CBMEM -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} -#else +#if CONFIG_DYNAMIC_CBMEM void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h index fd62184..25075bd 100644 --- a/src/northbridge/amd/lx/northbridge.h +++ b/src/northbridge/amd/lx/northbridge.h @@ -28,7 +28,6 @@ int sizeram(void); /* northbridgeinit.c */ void northbridge_init_early(void); -uint32_t get_top_of_ram(void); /* pll_reset.c */ unsigned int GeodeLinkSpeed(void); diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 3768777..ba9db2b 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -713,7 +713,7 @@ static void setup_lx_cache(void) wbinvd(); } -uint32_t get_top_of_ram(void) +unsigned long get_top_of_ram(void) { struct gliutable *gl = 0; uint32_t systop; diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index f9ba796..8eb4990 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -20,7 +20,6 @@ void e7505_mch_scrub_ecc(unsigned long ret_addr); void e7505_mch_done(const struct mem_controller *memctrl); int e7505_mch_is_ready(void); -unsigned long get_top_of_ram(void); /* Mainboard exports this. */ int spd_read_byte(unsigned device, unsigned address); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 2dffcad..227baef 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -422,7 +422,6 @@ void gm45_late_init(stepping_t); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); -u32 get_top_of_ram(void); void init_iommu(void); #endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 28e947b..5585822 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -83,7 +83,7 @@ u32 decode_igd_gtt_size(const u32 gsm) } } -u32 get_top_of_ram(void) +unsigned long get_top_of_ram(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 46be570..706c286 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -23,7 +23,6 @@ #include "pei_data.h" void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_haswell_errata(void); /* save_mrc_data() must be called after cbmem has been initialized. */ void save_mrc_data(struct pei_data *pei_data); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index b1a0684..b50f1d8 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,11 +28,6 @@ #include "i945.h" #include <cbmem.h> -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 2d8ef9e..9eb4193 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -69,7 +69,6 @@ struct sys_info { void receive_enable_adjust(struct sys_info *sysinfo); void sdram_initialize(int boot_path, const u8 *sdram_addresses); -unsigned long get_top_of_ram(void); int fixup_i945_errata(void); void udelay(u32 us); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4cd86cd..a03b8a6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,21 +51,13 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -static unsigned long get_top_of_ram(void) +unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); return (unsigned long) tom; } -struct cbmem_entry *get_cbmem_toc(void) -{ - static struct cbmem_entry *toc = NULL; - if (!toc) - toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); - return toc; -} - /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3eb2fb3..3b321d7 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -305,11 +305,6 @@ void sdram_initialize(struct pei_data *pei_data) save_mrc_data(pei_data); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - unsigned long get_top_of_ram(void) { /* Base of TSEG is top of usable DRAM */ diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 23bdbd9..2e9b1f3 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -30,7 +30,6 @@ struct sys_info { } __attribute__ ((packed)); void sdram_initialize(struct pei_data *pei_data); -unsigned long get_top_of_ram(void); int fixup_sandybridge_errata(void); #endif /* RAMINIT_H */ diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 2439c8d..2896680 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -27,11 +27,6 @@ unsigned long get_top_of_ram(void) return (((unsigned long)reg_tom) << 24) - (256 << 20); } -struct cbmem_entry *get_cbmem_toc(void) -{ - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); -} - /** * \brief Enable accessing of PCI configuration space for all devices. * diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h index dcb24b5..46e3023 100644 --- a/src/northbridge/via/vx900/early_vx900.h +++ b/src/northbridge/via/vx900/early_vx900.h @@ -61,7 +61,6 @@ #define RAMINIT_USE_HW_RXCR_CALIB 0 #define RAMINIT_USE_HW_MRS_SEQ 0 -unsigned long get_top_of_ram(void); void enable_smbus(void); void dump_spd_data(spd_raw_data spd);

1 0

New patch to review for coreboot: 2bce7a2 AMD: Drop no-op cbmem_reinit() in romstage
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3903 -gerrit commit 2bce7a2155d0f1c390981bcafedb54dbae9fcc80 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 24 17:42:59 2013 +0300 AMD: Drop no-op cbmem_reinit() in romstage Change-Id: I40d151bd7bc91058243be4562ba12505aa81496b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 11 ----------- src/cpu/amd/car/post_cache_as_ram.c | 9 --------- 2 files changed, 20 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6ba9212..115275e 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -109,19 +109,8 @@ void restore_mtrr(void) inline void *backup_resume(void) { - unsigned long high_ram_base; void *resume_backup_memory; - /* Start address of high memory tables */ - high_ram_base = (u32) get_cbmem_toc(); - - /* - * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); - * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); - */ - - cbmem_reinit((u64) high_ram_base); - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (((u32) resume_backup_memory == 0) || ((u32) resume_backup_memory == -1)) { diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 18c278e..49eb3a6 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -32,21 +32,12 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi #if CONFIG_HAVE_ACPI_RESUME static inline void *backup_resume(void) { - unsigned long high_ram_base; void *resume_backup_memory; int suspend = acpi_is_wakeup_early(); if (!suspend) return NULL; - /* Start address of high memory tables */ - high_ram_base = (u32) get_cbmem_toc(); - - print_debug_pcar("CBMEM TOC is at: ", (uint32_t)high_ram_base); - print_debug_pcar("CBMEM TOC 0-size: ",(uint32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); - - cbmem_reinit((u64)high_ram_base); - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

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New patch to review for coreboot: 3e718d2 Add set_cbmem_table
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3902 -gerrit commit 3e718d21107f3b5e450f0df229c0fd7ac6cfbee2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 13:05:01 2013 +0300 Add set_cbmem_table Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/ramtop.c | 5 +---- src/include/cbmem.h | 1 + src/lib/cbmem.c | 11 +++++++++++ 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/boot/ramtop.c b/src/arch/x86/boot/ramtop.c index cbd43dc..7ac2ee2 100644 --- a/src/arch/x86/boot/ramtop.c +++ b/src/arch/x86/boot/ramtop.c @@ -21,9 +21,6 @@ #if !CONFIG_DYNAMIC_CBMEM void set_top_of_ram(uint64_t ramtop) { - high_tables_base = ramtop - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; - printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", - high_tables_base, high_tables_size); + set_cbmem_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); } #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 815c249..46739de 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -136,6 +136,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem); #ifndef __PRE_RAM__ extern uint64_t high_tables_base, high_tables_size; void set_top_of_ram(uint64_t ramtop); +void set_cbmem_table(uint64_t base, uint64_t size); void set_cbmem_toc(struct cbmem_entry *); #endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 9e2ce0d..1a7a4e5 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -60,7 +60,18 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n"); return NULL; } +#endif +#if !defined(__PRE_RAM__) +void set_cbmem_table(uint64_t base, uint64_t size) +{ + if (base == high_tables_base && size == high_tables_size) + return; + + printk(BIOS_DEBUG, "CBMEM region %llx-%llx\n", base, base+size-1); + high_tables_base = base; + high_tables_size = size; +} #endif /**

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Patch set updated for coreboot: f32bf84 google/snow google/pit: Prepare for CBMEM fix
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3560 -gerrit commit f32bf843031c20864f74059460b435fb4f38c0ce Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 22 14:05:28 2013 +0300 google/snow google/pit: Prepare for CBMEM fix Follow-up will remove globals but there is circular dependency in patches. Patch "Use get_cbmem_toc in ramstage" will recover correct operation for these two boards. Change-Id: I973f3a84dd9aaa2839959df5dda22909fdb9edeb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 1 - src/lib/cbmem.c | 4 +++- src/mainboard/google/pit/mainboard.c | 15 +++++++++------ src/mainboard/google/snow/mainboard.c | 15 +++++++++------ 4 files changed, 21 insertions(+), 14 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 6c7b85c..8ba1d21 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -140,7 +140,6 @@ void backup_top_of_ram(uint64_t ramtop); void set_cbmem_table(uint64_t base, uint64_t size); #endif -void cbmem_init(u64 baseaddr, u64 size); int cbmem_reinit(u64 baseaddr); unsigned long get_top_of_ram(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 3f8f243..eb18725 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -80,7 +80,8 @@ void set_cbmem_table(uint64_t base, uint64_t size) * - suspend/resume backup memory */ -void cbmem_init(u64 baseaddr, u64 size) +#if !defined(__PRE_RAM__) +static void cbmem_init(u64 baseaddr, u64 size) { struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; @@ -102,6 +103,7 @@ void cbmem_init(u64 baseaddr, u64 size) .size = size - CBMEM_TOC_RESERVED }; } +#endif int cbmem_reinit(u64 baseaddr) { diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 54ea042..5c88be5 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -221,17 +221,20 @@ static void mainboard_init(device_t dev) // gpio_info(); } +void get_cbmem_table(uint64_t *base, uint64_t *size) +{ + *base = CONFIG_SYS_SDRAM_BASE + + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + *size = CONFIG_COREBOOT_TABLES_SIZE; +} + static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); + cbmem_initialize(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 5aedac9..8e6b7c8 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -262,17 +262,20 @@ static void mainboard_init(device_t dev) // gpio_info(); } +void get_cbmem_table(uint64_t *base, uint64_t *size) +{ + *base = CONFIG_SYS_SDRAM_BASE + + ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - + CONFIG_COREBOOT_TABLES_SIZE; + *size = CONFIG_COREBOOT_TABLES_SIZE; +} + static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; /* set up coreboot tables */ - /* FIXME: this should happen somewhere else */ - high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; - high_tables_base = CONFIG_SYS_SDRAM_BASE + - ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - - CONFIG_COREBOOT_TABLES_SIZE; - cbmem_init(high_tables_base, high_tables_size); + cbmem_initialize(); /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */

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Patch set updated for coreboot: 8ce66a7 Drop parameter from cbmem_reinit()
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3564 -gerrit commit 8ce66a725fdab3b65cd6d091f72fe464f32c17f4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 23 17:01:29 2013 +0300 Drop parameter from cbmem_reinit() Function is always called with high_tables_base() so there is no need to pass it as a parameter. Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 2 +- src/lib/cbmem.c | 9 ++++----- src/mainboard/getac/p470/romstage.c | 5 +---- src/mainboard/google/stout/romstage.c | 3 +-- src/mainboard/ibase/mb899/romstage.c | 5 +---- src/mainboard/intel/d945gclf/romstage.c | 5 +---- src/mainboard/kontron/986lcd-m/romstage.c | 5 +---- src/mainboard/roda/rk886ex/romstage.c | 5 +---- src/mainboard/roda/rk9/romstage.c | 5 +---- 9 files changed, 12 insertions(+), 32 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 3eeb6a1..b965fd6 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -135,7 +135,7 @@ void set_cbmem_table(uint64_t base, uint64_t size); int cbmem_base_check(void); #endif -int cbmem_reinit(u64 baseaddr); +int cbmem_reinit(void); unsigned long get_top_of_ram(void); struct cbmem_entry *get_cbmem_toc(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 963ca4d..656b46d 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -113,13 +113,12 @@ static void cbmem_init(u64 baseaddr, u64 size) } #endif -int cbmem_reinit(u64 baseaddr) +int cbmem_reinit(void) { - struct cbmem_entry *cbmem_toc; - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; + struct cbmem_entry *cbmem_toc = get_cbmem_toc(); printk(BIOS_DEBUG, "Re-Initializing CBMEM area to 0x%lx\n", - (unsigned long)baseaddr); + (unsigned long)cbmem_toc); return (cbmem_toc[0].magic == CBMEM_MAGIC); } @@ -219,7 +218,7 @@ int cbmem_initialize(void) cbmem_locate_table(&base, &size); /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit(base)) { + if (!cbmem_reinit()) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) /* Something went wrong, our high memory area got wiped */ if (acpi_slp_type == 3 || acpi_slp_type == 2) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 90d38eb..f4e43e5 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -358,13 +358,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 14820dd..83be94e 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -313,8 +313,7 @@ void main(unsigned long bist) #if CONFIG_EARLY_CBMEM_INIT cbmem_was_initted = !cbmem_initialize(); #else - cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() - - HIGH_MEMORY_SIZE)); + cbmem_was_initted = cbmem_reinit(); #endif #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 79eaa0b..b059a57 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -312,13 +312,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index a37f605..248aa3b 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -270,13 +270,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 03b24d8..324f442 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -411,13 +411,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index ab200d2..cb141f9 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -347,13 +347,10 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + if ((boot_mode == 2) && cbmem_reinit()) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 56eea84..075790d 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -184,13 +184,10 @@ void main(unsigned long bist) init_iommu(); #if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_reinit((u64)high_ram_base)) { + if (s3resume && cbmem_reinit() { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

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Patch set updated for coreboot: 5a204ba Drop parameters from cbmem_init()
by Kyösti Mälkki 04 Sep '13

04 Sep '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3565 -gerrit commit 5a204ba82dabb2247306f5722d734600859ffaad Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Sep 4 14:36:31 2013 +0300 Drop parameters from cbmem_init() Change-Id: Ia40350a5232dcbf30aca7b5998e7995114c44551 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/cbmem.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 656b46d..df5a4a1 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -89,11 +89,12 @@ void set_cbmem_table(uint64_t base, uint64_t size) */ #if !defined(__PRE_RAM__) -static void cbmem_init(u64 baseaddr, u64 size) +static void cbmem_init(void) { + uint64_t baseaddr, size; struct cbmem_entry *cbmem_toc; - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; + cbmem_locate_table(&baseaddr, &size); printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); @@ -102,6 +103,7 @@ static void cbmem_init(u64 baseaddr, u64 size) for (;;) ; } + cbmem_toc = get_cbmem_toc(); memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); cbmem_toc[0] = (struct cbmem_entry) { @@ -212,11 +214,8 @@ void *cbmem_find(u32 id) /* Returns True if it was not initialized before. */ int cbmem_initialize(void) { - uint64_t base = 0, size = 0; int rv = 0; - cbmem_locate_table(&base, &size); - /* We expect the romstage to always initialize it. */ if (!cbmem_reinit()) { #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) @@ -224,7 +223,7 @@ int cbmem_initialize(void) if (acpi_slp_type == 3 || acpi_slp_type == 2) acpi_slp_type = 0; #endif - cbmem_init(base, size); + cbmem_init(); rv = 1; } #ifndef __PRE_RAM__

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coreboot-gerrit September 2013