coreboot-gerrit July 2013

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New patch to review for coreboot: b2e4581 intel/i945 intel/i82801gx: remove explicit pcie config accesses
by Kyösti Mälkki 26 Jul '13

26 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3811 -gerrit commit b2e4581a03e2413fcf6231ceefb82274650b2ff9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:52:10 2013 +0300 intel/i945 intel/i82801gx: remove explicit pcie config accesses Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/i945/early_init.c | 140 ++++++++++++++-------------- src/southbridge/intel/i82801gx/azalia.c | 24 ++--- src/southbridge/intel/i82801gx/i82801gx.c | 4 + src/southbridge/intel/i82801gx/pcie.c | 13 +-- src/southbridge/intel/i82801gx/smihandler.c | 10 +- 5 files changed, 94 insertions(+), 97 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 946f7aa..57232af 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -529,9 +529,9 @@ static void i945_setup_pci_express_x16(void) reg16 |= DEVEN_D1F0; pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x208); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x208); reg32 &= ~(1 << 8); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32); /* We have no success with querying the usual PCIe registers * for link setup success on the i945. Hence we assign a temporary @@ -560,33 +560,33 @@ static void i945_setup_pci_express_x16(void) pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a); pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); reg32 &= ~(1 << 8); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) ); /* Initialze PEG_CAP */ - reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xa2); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2); reg16 |= (1 << 8); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16); /* Setup SLOTCAP */ /* TODO: These values are mainboard dependent and should * be set from devicetree.cb. */ /* NOTE: SLOTCAP becomes RO after the first write! */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); reg32 &= 0x0007ffff; reg32 &= 0xfffe007f; - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32); /* Wait for training to succeed */ printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -597,21 +597,21 @@ static void i945_setup_pci_express_x16(void) printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214); reg32 &= ~(0xf << 1); reg32 |=1; - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32); - reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); reg16 |= (1 << 6); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); reg16 &= ~(1 << 6); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -624,22 +624,22 @@ static void i945_setup_pci_express_x16(void) } } - reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); reg16 >>= 4; reg16 &= 0x3f; /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204); reg32 &= 0xfffffc00; /* clear [9:0] */ if (reg16 == 1) { reg32 |= 0x32b; // TODO - /* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ + /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ } else if (reg16 == 16) { reg32 |= 0x0f4; // TODO - /* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ + /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ } reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); @@ -661,82 +661,82 @@ static void i945_setup_pci_express_x16(void) } /* Enable GPEs */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xec); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec); reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x114); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114); reg32 &= 0xffffff01; - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); /* Extended VC count */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x104); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x104); reg32 &= ~(7 << 0); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32); /* Active State Power Management ASPM */ /* TODO */ /* Clear error bits */ - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff); - pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff); + pci_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); /* Program R/WO registers */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x308); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x308); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x314); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x314); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x324); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x324); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x328); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); - reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), 0xb4); - pcie_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), 0xb4); + pci_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8); /* Additional PCIe graphics setup */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 26); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 24); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (1 << 5); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x200); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x200); reg32 &= ~(3 << 26); reg32 |= (2 << 26); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); if (i945_silicon_revision() >= 2) { reg32 |= (1 << 12); } else { reg32 &= ~(1 << 12); } - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); reg32 &= ~(1 << 31); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); reg32 |= (1 << 31); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); if (i945_silicon_revision() >= 3) { static const u32 reglist[] = { @@ -747,21 +747,21 @@ static void i945_setup_pci_express_x16(void) int i; for (i=0; i<ARRAY_SIZE(reglist); i++) { - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); reg32 &= 0x0fffffff; reg32 |= (2 << 28); - pcie_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); } } if (i945_silicon_revision() <= 2 ) { /* Set voltage specific parameters */ - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); reg32 &= (0xf << 4); /* Default case 1.05V */ if ((MCHBAR32(0xe08) & (1 << 20)) == 0) { /* 1.50V */ reg32 |= (7 << 4); } - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); } return; @@ -772,21 +772,21 @@ disable_pciexpress_x16_link: MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); - reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 |= (1 << 6); - pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); reg32 |= (1 << 8); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); - reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 &= ~(1 << 6); - pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; - for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214); + for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214); (reg32 & 0x000f0000) && --timeout;) ; if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); @@ -836,10 +836,10 @@ static void i945_setup_root_complex_topology(void) /* PCI Express x16 Port Root Topology */ if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR); - reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x150); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x150); reg32 |= (1 << 0); - pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); } } diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 26859c5..cb1a37d 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -224,39 +224,35 @@ static void azalia_init(struct device *dev) u8 reg8; u32 reg32; -#if CONFIG_MMCONF_SUPPORT // ESD - reg32 = pci_mmio_read_config32(dev, 0x134); + reg32 = pci_read_config32(dev, 0x134); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x134, reg32); + pci_write_config32(dev, 0x134, reg32); // Link1 description - reg32 = pci_mmio_read_config32(dev, 0x140); + reg32 = pci_read_config32(dev, 0x140); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x140, reg32); + pci_write_config32(dev, 0x140, reg32); // Port VC0 Resource Control Register - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); // VCi traffic class - reg8 = pci_mmio_read_config8(dev, 0x44); + reg8 = pci_read_config8(dev, 0x44); reg8 |= (7 << 0); // TC7 - pci_mmio_write_config8(dev, 0x44, reg8); + pci_write_config8(dev, 0x44, reg8); // VCi Resource Control - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); reg32 |= (1 << 24); // VCi ID reg32 |= (0x80 << 0); // VCi map - pci_mmio_write_config32(dev, 0x120, reg32); -#else -#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT -#endif + pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 7fe14bd..ed5921b 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -23,6 +23,10 @@ #include <device/pci.h> #include "i82801gx.h" +#if !CONFIG_MMCONF_SUPPORT_DEFAULT +#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT +#endif + void i82801gx_enable(device_t dev) { u32 reg32; diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 1bc1bed..0825dec 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -55,20 +55,17 @@ static void pci_init(struct device *dev) reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); pci_write_config32(dev, 0xe1, reg32); -#if CONFIG_MMCONF_SUPPORT /* Set VC0 transaction class */ - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); /* Mask completion timeouts */ - reg32 = pci_mmio_read_config32(dev, 0x148); + reg32 = pci_read_config32(dev, 0x148); reg32 |= (1 << 14); - pci_mmio_write_config32(dev, 0x148, reg32); -#else -#error "MMIO needed for ICH7 PCIe" -#endif + pci_write_config32(dev, 0x148, reg32); + /* Enable common clock configuration */ // Are there cases when we don't want that? reg16 = pci_read_config16(dev, 0x50); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 03c5d09..ba4d014 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -319,13 +319,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) { reg8 &= ~1; } else { reg8 |= 1; } - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -494,7 +494,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -508,7 +508,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -635,7 +635,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav u32 smi_sts; /* Update global variable pmbase */ - pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls.

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New patch to review for coreboot: df51dc8 intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses
by Kyösti Mälkki 26 Jul '13

26 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3810 -gerrit commit df51dc89bb88a981c3d7229b72fc4e1d71e821f9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:50:53 2013 +0300 intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/stout/mainboard_smi.c | 4 ++-- src/northbridge/intel/sandybridge/finalize.c | 22 ++++++++--------- src/southbridge/intel/bd82x6x/azalia.c | 16 ++++++------- src/southbridge/intel/bd82x6x/finalize.c | 8 +++---- src/southbridge/intel/bd82x6x/me.c | 10 ++++---- src/southbridge/intel/bd82x6x/me_8.x.c | 8 +++---- src/southbridge/intel/bd82x6x/pcie.c | 18 +++++++------- src/southbridge/intel/bd82x6x/smihandler.c | 36 ++++++++++++++-------------- src/southbridge/intel/bd82x6x/spi.c | 12 +++++----- 9 files changed, 67 insertions(+), 67 deletions(-) diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 8b37da3..0f2ecd5 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -102,10 +102,10 @@ void mainboard_smi_sleep(u8 slp_typ) * after the transition into suspend. */ if (smm_get_gnvs()->xhci) { - u32 reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74); + u32 reg32 = pci_read_config32(PCH_XHCI_DEV, 0x74); reg32 &= ~(1 << 8); /* disable PME */ reg32 |= (1 << 15); /* clear PME status */ - pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32); + pci_write_config32(PCH_XHCI_DEV, 0x74, reg32); } } diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 9b41cfa..b0a8d6a 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -26,17 +26,17 @@ void intel_sandybridge_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 2d854a4..9fcb770 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -250,26 +250,26 @@ static void azalia_init(struct device *dev) printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); if (RCBA32(0x2030) & (1 << 31)) { - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 24); // 2 << 24 for server reg32 |= RCBA32(0x2030) & 0xfe; - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32); - reg16 = pci_mmio_read_config16(dev, 0x78); + reg16 = pci_read_config16(dev, 0x78); reg16 |= (1 << 11); - pci_mmio_write_config16(dev, 0x78, reg16); + pci_write_config16(dev, 0x78, reg16); } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= ~0xfe; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); // Set VCi enable bit - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32); // Enable HDMI codec: reg32 = pci_read_config32(dev, 0xc4); diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 76e75c8..ad2586c 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -57,15 +57,15 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); - pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, - pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); + pci_write_config32(PCI_DEV(0, 27, 0), 0x74, + pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 626e61a..17be63b 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -502,14 +502,14 @@ static void intel_me7_finalize_smm(void) u32 reg32; mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == 0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, &reg32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ @@ -522,10 +522,10 @@ static void intel_me7_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -533,7 +533,7 @@ static void intel_me7_finalize_smm(void) void intel_me_finalize_smm(void) { - u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { case 0x1c3a8086: intel_me7_finalize_smm(); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 72175d8..92f132d 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -497,14 +497,14 @@ void intel_me8_finalize_smm(void) u32 reg32; mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == 0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, &reg32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ @@ -517,10 +517,10 @@ void intel_me8_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 2e3e465..fadb43f 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -139,30 +139,30 @@ static void pch_pcie_pm_late(struct device *dev) u32 reg32; /* Set 0x314 = 0x743a361b */ - pci_mmio_write_config32(dev, 0x314, 0x743a361b); + pci_write_config32(dev, 0x314, 0x743a361b); /* Set 0x318[31:16] = 0x1414 */ - reg32 = pci_mmio_read_config32(dev, 0x318); + reg32 = pci_read_config32(dev, 0x318); reg32 &= 0x0000ffff; reg32 |= 0x14140000; - pci_mmio_write_config32(dev, 0x318, reg32); + pci_write_config32(dev, 0x318, reg32); /* Set 0x324[5] = 1 */ - reg32 = pci_mmio_read_config32(dev, 0x324); + reg32 = pci_read_config32(dev, 0x324); reg32 |= (1 << 5); - pci_mmio_write_config32(dev, 0x324, reg32); + pci_write_config32(dev, 0x324, reg32); /* Set 0x330[7:0] = 0x40 */ - reg32 = pci_mmio_read_config32(dev, 0x330); + reg32 = pci_read_config32(dev, 0x330); reg32 &= ~(0xff); reg32 |= 0x40; - pci_mmio_write_config32(dev, 0x330, reg32); + pci_write_config32(dev, 0x330, reg32); /* Set 0x33C[24:0] = 0x854c74 */ - reg32 = pci_mmio_read_config32(dev, 0x33c); + reg32 = pci_read_config32(dev, 0x33c); reg32 &= 0xff000000; reg32 |= 0x00854c74; - pci_mmio_write_config32(dev, 0x33c, reg32); + pci_write_config32(dev, 0x33c, reg32); /* No IO-APIC, Disable EOI forwarding */ reg32 = pci_read_config32(dev, 0xd4); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 9588703..491f997 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -64,7 +64,7 @@ static u32 tseg_base = 0; u32 smi_get_tseg_base(void) { if (!tseg_base) - tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; + tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; return tseg_base; } void tseg_relocate(void **ptr) @@ -301,7 +301,7 @@ static void southbridge_gate_memory_reset(void) u32 reg32; u16 gpiobase; - gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; + gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; if (!gpiobase) return; @@ -333,15 +333,15 @@ static void xhci_sleep(u8 slp_typ) switch (slp_typ) { case SLP_TYP_S3: case SLP_TYP_S4: - reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 &= ~0x03UL; - pcie_write_config32(PCH_XHCI_DEV, 0x74, reg16); + pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); - reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); - xhci_bar = pcie_read_config32(PCH_XHCI_DEV, + xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL; if ((xhci_bar + 0x4C0) & 1) @@ -353,19 +353,19 @@ static void xhci_sleep(u8 slp_typ) if ((xhci_bar + 0x4F0) & 1) pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); - reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); - reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 |= 0x03; - pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16); + pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); break; case SLP_TYP_S5: - reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 |= ((1 << 8) | 0x03); - pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16); + pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); break; } } @@ -436,13 +436,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) { reg8 &= ~1; } else { reg8 |= 1; } - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -672,7 +672,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -686,7 +686,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -813,7 +813,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav u32 smi_sts; /* Update global variable pmbase */ - pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 320cf8c..ec5d7de 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -36,17 +36,17 @@ #ifdef __SMM__ #include <arch/pci_mmio_cfg.h> #define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pcie_read_config8(dev, reg) + *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ - *(targ) = pcie_read_config16(dev, reg) + *(targ) = pci_read_config16(dev, reg) #define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pcie_read_config32(dev, reg) + *(targ) = pci_read_config32(dev, reg) #define pci_write_config_byte(dev, reg, val)\ - pcie_write_config8(dev, reg, val) + pci_write_config8(dev, reg, val) #define pci_write_config_word(dev, reg, val)\ - pcie_write_config16(dev, reg, val) + pci_write_config16(dev, reg, val) #define pci_write_config_dword(dev, reg, val)\ - pcie_write_config32(dev, reg, val) + pci_write_config32(dev, reg, val) #else /* !__SMM__ */ #include <device/device.h> #include <device/pci.h>

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New patch to review for coreboot: fd309f9 intel/i82801ix: remove explicit pcie config accesses
by Kyösti Mälkki 26 Jul '13

26 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3809 -gerrit commit fd309f94cf85cf910910420b23157bc40094901b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:35:09 2013 +0300 intel/i82801ix: remove explicit pcie config accesses Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801ix/hdaudio.c | 24 ++++++++++-------------- src/southbridge/intel/i82801ix/i82801ix.c | 22 +++++++++------------- src/southbridge/intel/i82801ix/pcie.c | 14 +++++--------- src/southbridge/intel/i82801ix/smihandler.c | 6 +++--- 4 files changed, 27 insertions(+), 39 deletions(-) diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 2d75d11..d950596 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -237,39 +237,35 @@ static void azalia_init(struct device *dev) u8 reg8; u32 reg32; -#if CONFIG_MMCONF_SUPPORT // ESD - reg32 = pci_mmio_read_config32(dev, 0x134); + reg32 = pci_read_config32(dev, 0x134); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x134, reg32); + pci_write_config32(dev, 0x134, reg32); // Link1 description - reg32 = pci_mmio_read_config32(dev, 0x140); + reg32 = pci_read_config32(dev, 0x140); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x140, reg32); + pci_write_config32(dev, 0x140, reg32); // Port VC0 Resource Control Register - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); // VCi traffic class - reg8 = pci_mmio_read_config8(dev, 0x44); + reg8 = pci_read_config8(dev, 0x44); reg8 |= (7 << 0); // TC7 - pci_mmio_write_config8(dev, 0x44, reg8); + pci_write_config8(dev, 0x44, reg8); // VCi Resource Control - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); reg32 |= (1 << 24); // VCi ID reg32 |= (0x80 << 0); // VCi map - pci_mmio_write_config32(dev, 0x120, reg32); -#else -#error ICH9 Azalia required CONFIG_MMCONF_SUPPORT -#endif + pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index e35487f..0fe7d20 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -27,6 +27,10 @@ #include <console/console.h> #include "i82801ix.h" +#if !CONFIG_MMCONF_SUPPORT_DEFAULT +#error ICH9 requires CONFIG_MMCONF_SUPPORT_DEFAULT +#endif + typedef struct southbridge_intel_i82801ix_config config_t; static void i82801ix_enable_device(device_t dev) @@ -66,13 +70,9 @@ static void i82801ix_pcie_init(const config_t *const info) printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); } -#if CONFIG_MMCONF_SUPPORT - reg32 = pci_mmio_read_config32(pciePort[i], 0x300); - pci_mmio_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); - pci_mmio_write_config8(pciePort[i], 0x324, 0x40); -#else -#error "MMIO needed for ICH9 PCIe" -#endif + reg32 = pci_read_config32(pciePort[i], 0x300); + pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_write_config8(pciePort[i], 0x324, 0x40); } if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { @@ -87,13 +87,9 @@ static void i82801ix_pcie_init(const config_t *const info) for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { /* Only for the top disabled ports. */ -#if CONFIG_MMCONF_SUPPORT - reg32 = pci_mmio_read_config32(pciePort[i], 0x300); + reg32 = pci_read_config32(pciePort[i], 0x300); reg32 |= 0x3 << 16; - pci_mmio_write_config32(pciePort[i], 0x300, reg32); -#else -#error "MMIO needed for ICH9 PCIe" -#endif + pci_write_config32(pciePort[i], 0x300, reg32); } /* Set slot implemented, slot number and slot power limits. */ diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index ce5d265..f53519d 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -56,23 +56,19 @@ static void pci_init(struct device *dev) reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); pci_write_config32(dev, 0xe1, reg32); -#if CONFIG_MMCONF_SUPPORT /* Set VC0 transaction class */ - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); /* Mask completion timeouts */ - reg32 = pci_mmio_read_config32(dev, 0x148); + reg32 = pci_read_config32(dev, 0x148); reg32 |= (1 << 14); - pci_mmio_write_config32(dev, 0x148, reg32); + pci_write_config32(dev, 0x148, reg32); /* Lock R/WO Correctable Error Mask. */ - pci_mmio_write_config32(dev, 0x154, pci_mmio_read_config32(dev, 0x154)); -#else -#error "MMIO needed for ICH9 PCIe" -#endif + pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154)); /* Clear errors in status registers */ reg16 = pci_read_config16(dev, 0x06); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 5b6eafa..6d17621 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -344,7 +344,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -358,7 +358,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_mmio_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -501,7 +501,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav u32 smi_sts; /* Update global variable pmbase */ - pmbase = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc; /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls.

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Patch set updated for coreboot: 3718cf9 intel/gm45: Use MMCONF_SUPPORT_DEFAULT
by Kyösti Mälkki 26 Jul '13

26 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3600 -gerrit commit 3718cf9d5d95fac194f8192d75847833f77d4ebe Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 1 11:21:53 2013 +0300 intel/gm45: Use MMCONF_SUPPORT_DEFAULT Change all PCI configuration accesses to MMIO for all boards with gm45 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: Id1c839b7d669946e0ca8b6837e5152ebcb9cd334 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/gm45/Kconfig | 4 ++++ src/northbridge/intel/gm45/bootblock.c | 27 +++++++++++++++++++++++++++ src/northbridge/intel/gm45/early_init.c | 5 ----- 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 16a0bf1..adf1c1b 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,4 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select IOMMU +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/gm45/bootblock.c" + endif diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c new file mode 100644 index 0000000..fb40b94 --- /dev/null +++ b/src/northbridge/intel/gm45/bootblock.c @@ -0,0 +1,27 @@ +#include <arch/io.h> + +/* Just re-define these instead of including gm45.h. It blows up romcc. */ +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); +} diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 052c517..ed5bf99 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -25,11 +25,6 @@ void gm45_early_init(void) { const device_t d0f0 = PCI_DEV(0, 0, 0); - /* Setup PCIEXBAR. */ - pci_io_write_config32(d0f0, D0F0_PCIEXBAR_LO, - /* 64MB, enable */ - DEFAULT_PCIEXBAR | (2 << 1) | 1); - /* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);

1 0

Patch merged into coreboot/master: 933b5df AMD Parmer: Fix file permissions on asl files in mainboard
by gerrit＠coreboot.org 26 Jul '13

26 Jul '13

the following patch was just integrated into master: commit 933b5df6a84d0eaf25b035aef83351f1506c3aa1 Author: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Date: Wed Jul 24 09:56:03 2013 -0600 AMD Parmer: Fix file permissions on asl files in mainboard Removed the execute bit on all files in mainboard/amd/parmer/acpi Change-Id: I85ffa66e0beb9c4bfe826b72968f7f633c224487 Signed-off-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3807 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3807 for details. -gerrit

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Patch set updated for coreboot: 081a3a3 intel/gm45: Use MMCONF_SUPPORT_DEFAULT
by Kyösti Mälkki 26 Jul '13

26 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3600 -gerrit commit 081a3a3f2742a8ccf33b3085dedad5deb37e714b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 1 11:21:53 2013 +0300 intel/gm45: Use MMCONF_SUPPORT_DEFAULT Change all PCI configuration accesses to MMIO for all boards with gm45 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: Id1c839b7d669946e0ca8b6837e5152ebcb9cd334 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/gm45/Kconfig | 4 ++++ src/northbridge/intel/gm45/bootblock.c | 27 +++++++++++++++++++++++++++ src/northbridge/intel/gm45/early_init.c | 5 ----- 3 files changed, 31 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 16a0bf1..adf1c1b 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,4 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select IOMMU +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/gm45/bootblock.c" + endif diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c new file mode 100644 index 0000000..fb40b94 --- /dev/null +++ b/src/northbridge/intel/gm45/bootblock.c @@ -0,0 +1,27 @@ +#include <arch/io.h> + +/* Just re-define these instead of including gm45.h. It blows up romcc. */ +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); +} diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 052c517..ed5bf99 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -25,11 +25,6 @@ void gm45_early_init(void) { const device_t d0f0 = PCI_DEV(0, 0, 0); - /* Setup PCIEXBAR. */ - pci_io_write_config32(d0f0, D0F0_PCIEXBAR_LO, - /* 64MB, enable */ - DEFAULT_PCIEXBAR | (2 << 1) | 1); - /* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);

1 0

Patch merged into coreboot/master: b9646a2 emulation/qemu-q35: Use MMCONF_SUPPORT_DEFAULT
by gerrit＠coreboot.org 26 Jul '13

26 Jul '13

the following patch was just integrated into master: commit b9646a2bdc1c29961a326fc7f657433067d53ff0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jul 3 08:06:32 2013 +0300 emulation/qemu-q35: Use MMCONF_SUPPORT_DEFAULT Change all PCI configuration accesses to MMIO in qemu-q35 emulation To enable MMIO style access, add (move) explicit PCI IO config write in the bootblock. As there is no northbridge/x/x/bootblock.c file, a mainboard/x/x/bootblock.c file is added for this purpose. Change-Id: I979efb3d9b2f359a9ccbd1b4f6c05f83bab43007 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3599 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3599 for details. -gerrit

1 0

Patch merged into coreboot/master: aad0747 Redefine pci_bus_default_ops as function
by gerrit＠coreboot.org 25 Jul '13

25 Jul '13

the following patch was just integrated into master: commit aad0747216cab56a8cee5c1401c094543ed8be2d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 4 17:17:45 2013 +0300 Redefine pci_bus_default_ops as function Taking device_t as a parameter, this allows to alter the PCI config access handlers. This is useful to add tracing of PCI config writes for devices having problems to initialise correctly. On older AMD platform PCI MMIO may not be able to fully configure all PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due to its atomic nature. So those can be forced to IO config instead. Change-Id: I2162884185bbfe461b036caf737980b45a51e522 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3608 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3608 for details. -gerrit

1 0

Patch set updated for coreboot: 630741b AMD Kabini: Modify Hudson southbridge to support new AMD processor
by Bruce Griffith 25 Jul '13

25 Jul '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3783 -gerrit commit 630741b6a179e89249c751ecf8fa0d926d7047e1 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Tue Jul 9 17:32:42 2013 +0800 AMD Kabini: Modify Hudson southbridge to support new AMD processor Yangtze uses Hudson AGESA wrapper code but has some changes. The changes are necessary and have no effects on Hudson. Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/southbridge/amd/Makefile.inc | 1 + src/southbridge/amd/agesa/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/Kconfig | 25 ++++++++++++++++++++----- src/southbridge/amd/agesa/hudson/early_setup.c | 3 +++ src/southbridge/amd/agesa/hudson/sata.c | 6 ++++++ src/southbridge/amd/agesa/hudson/sm.c | 1 + src/southbridge/amd/agesa/hudson/spi.c | 9 +++++++++ 7 files changed, 41 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index cce4702..9ec0171 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -15,6 +15,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y) diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index 822c6fd..fdd5d80 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -17,3 +17,4 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index af305ee..5cb1722 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -23,7 +23,13 @@ config SOUTHBRIDGE_AMD_AGESA_HUDSON select HAVE_USBDEBUG select HAVE_HARD_RESET -if SOUTHBRIDGE_AMD_AGESA_HUDSON +config SOUTHBRIDGE_AMD_AGESA_YANGTZE + bool + select IOAPIC + select HAVE_USBDEBUG + select HAVE_HARD_RESET + +if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE config BOOTBLOCK_SOUTHBRIDGE_INIT string @@ -72,17 +78,20 @@ config HUDSON_GEC_FWM config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" - default "3rdparty/southbridge/amd/hudson/xhci.bin" + default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/imc.bin" + default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_IMC_FWM config HUDSON_GEC_FWM_FILE string "GEC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/gec.bin" + default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_GEC_FWM config HUDSON_FWM @@ -232,4 +241,10 @@ config HUDSON_LEGACY_FREE Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI. -endif # SOUTHBRIDGE_AMD_AGESA_HUDSON +endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE + +if SOUTHBRIDGE_AMD_AGESA_YANGTZE + config AMD_SB_SPI_TX_LEN + int + default 64 +endif diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a0319ab..af5bcbd 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -46,6 +46,9 @@ void hudson_lpc_port80(void) byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); + byte = pci_read_config8(dev, 0x48); + byte |= 3 << 0; /* enable Super I/O port 2E/2F, 4E/4F */ + pci_write_config8(dev, 0x48, byte); } int s3_save_nvram_early(u32 dword, int size, int nvram_pos) diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index cc8bf95..bc1cd92 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -49,3 +49,9 @@ static const struct pci_driver sata0_driver __pci_driver = { .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_ATI_SB900_SATA, }; + +static const struct pci_driver sata0_driver_ahci __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, +}; diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 3b727b9..d6ca215 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -82,6 +82,7 @@ static void sm_init(device_t dev) { + setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS); } static int lsmbus_recv_byte(device_t dev) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 1a63ce2..b89ea5d 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -61,7 +61,9 @@ int spi_xfer(struct spi_slave *slave, const void *dout, /* First byte is cmd which can not being sent through FIFO. */ u8 cmd = *(u8 *)dout++; u8 readoffby1; +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE u8 readwrite; +#endif u8 bytesout, bytesin; u8 count; @@ -71,8 +73,15 @@ int spi_xfer(struct spi_slave *slave, const void *dout, readoffby1 = bytesout ? 0 : 1; +#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE + write8(spibar + 0x1E, 5); + write8(spibar + 0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ + write8(spibar + 0x1E, 6); + write8(spibar + 0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ +#else readwrite = (bytesin + readoffby1) << 4 | bytesout; write8(spibar + 1, readwrite); +#endif write8(spibar + 0, cmd); reset_internal_fifo_pointer();

1 0

Patch set updated for coreboot: 495a071 AMD Hudson/Yangtze: Enable support for SATA port multipliers
by Bruce Griffith 25 Jul '13

25 Jul '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3808 -gerrit commit 495a071a10c1cfbdbcb00e60b48e6fc2a8c1ba22 Author: Bruce Griffith <bruce.griffith(a)se-eng.com> Date: Tue Jul 23 11:50:12 2013 -0600 AMD Hudson/Yangtze: Enable support for SATA port multipliers Change-Id: Ie87873b093f3e2a6a5c83b96ccb6c898d3e25f72 Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> --- src/southbridge/amd/agesa/hudson/sata.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index cc8bf95..883deeb 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -29,7 +29,33 @@ static void sata_init(struct device *dev) { -} + /************************************** + * Configure the SATA port multiplier * + **************************************/ + #define BYTE_TO_DWORD_OFFSET(x) (x/4) + #define AHCI_BASE_ADDRESS_REG 0x24 + #define MISC_CONTROL_REG 0x40 + #define UNLOCK_BIT (1<<0) + #define SATA_CAPABILITIES_REG 0xFC + #define CFG_CAP_SPM (1<<12) + + volatile u32 *ahci_ptr = + (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); + u32 temp; + + /* unlock the write-protect */ + temp = pci_read_config32(dev, MISC_CONTROL_REG); + temp |= UNLOCK_BIT; + pci_write_config32(dev, MISC_CONTROL_REG, temp); + + /* set the SATA AHCI mode to allow port expanders */ + *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM; + + /* lock the write-protect */ + temp = pci_read_config32(dev, MISC_CONTROL_REG); + temp &= ~UNLOCK_BIT; + pci_write_config32(dev, MISC_CONTROL_REG, temp); +}; static struct pci_operations lops_pci = { /* .set_subsystem = pci_dev_set_subsystem, */

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coreboot-gerrit July 2013