New patch to review for coreboot: adf5eea AMD OliveHill: update the CODEC verb data
by Bruce Griffith 26 Jul '13
by Bruce Griffith 26 Jul '13
26 Jul '13
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3820
-gerrit
commit adf5eea80ce65d79a33ffbbc1f07d385a19d4668
Author: Dave Frodin <dave.frodin(a)se-eng.com>
Date: Tue Jun 18 18:09:07 2013 -0600
AMD OliveHill: update the CODEC verb data
Change-Id: Ia302120e7bf9150a20f1c448b5cba6075e0e9da1
Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com>
---
src/mainboard/amd/olivehill/BiosCallOuts.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c
index 3efaa2b..f86242d 100644
--- a/src/mainboard/amd/olivehill/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehill/BiosCallOuts.c
@@ -66,20 +66,20 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
* AMD Olivehill Platform ALC272 Verb Table
*/
static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = {
- {0x11, 0x411111F0},
- {0x12, 0x411111F0},
- {0x13, 0x411111F0},
- {0x14, 0x411111F0},
- {0x15, 0x411111F0},
- {0x16, 0x411111F0},
- {0x17, 0x411111F0},
- {0x18, 0x01a19840},
- {0x19, 0x411111F0},
- {0x1a, 0x01813030},
- {0x1b, 0x411111F0},
- {0x1d, 0x40130605},
- {0x1e, 0x01441120},
- {0x21, 0x01211010},
+ {0x11, 0x411111F0}, // - SPDIF_OUT2
+ {0x12, 0x411111F0}, // - DMIC_1/2
+ {0x13, 0x411111F0}, // - DMIC_3/4
+ {0x14, 0x411111F0}, // Port D - LOUT1
+ {0x15, 0x411111F0}, // Port A - LOUT2
+ {0x16, 0x411111F0}, //
+ {0x17, 0x411111F0}, // Port H - MONO
+ {0x18, 0x01a19840}, // Port B - MIC1
+ {0x19, 0x411111F0}, // Port F - MIC2
+ {0x1a, 0x01813030}, // Port C - LINE1
+ {0x1b, 0x411111F0}, // Port E - LINE2
+ {0x1d, 0x40130605}, // - PCBEEP
+ {0x1e, 0x01441120}, // - SPDIF_OUT1
+ {0x21, 0x01214010}, // Port I - HPOUT
{0xff, 0xffffffff}
};
1
0
New patch to review for coreboot: c4b5a1d AMD OliveHill: Enable WARNINGS_ARE_ERRORS (remove override)
by Bruce Griffith 26 Jul '13
by Bruce Griffith 26 Jul '13
26 Jul '13
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3819
-gerrit
commit c4b5a1dc83203263379f888a267ef0c67fd9f8f1
Author: Bruce Griffith <bruce.griffith(a)se-eng.com>
Date: Tue Jul 23 21:43:52 2013 -0600
AMD OliveHill: Enable WARNINGS_ARE_ERRORS (remove override)
Change-Id: Idf26eb3fb541355bd9553c1897f647738c347eb5
Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com>
---
src/mainboard/amd/olivehill/Kconfig | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
index adb5d81..cacc0f4 100644
--- a/src/mainboard/amd/olivehill/Kconfig
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -97,8 +97,4 @@ config HUDSON_LEGACY_FREE
bool
default y
-config WARNINGS_ARE_ERRORS
- bool
- default n
-
endif # BOARD_AMD_OLIVEHILL
1
0
New patch to review for coreboot: f03b129 AMD OliveHill: Eliminate unnecessary memory copy
by Bruce Griffith 26 Jul '13
by Bruce Griffith 26 Jul '13
26 Jul '13
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3818
-gerrit
commit f03b1298c6b3828445e9060f8863b5078fc4f501
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Wed Jul 10 22:24:47 2013 -0600
AMD OliveHill: Eliminate unnecessary memory copy
Eliminate an unnecessary copy of the DDI descriptor list and
the PCIe port descriptor list. As descriptor tables, these
tables do not need dynamic updating and should be used from
ROM without runtime copying.
There will be a corresponding patch for AGESA that adds CONST
modifiers to function parameters that are pass-by-reference
"IN" values (read-only pointers).
Change-Id: I7ab78e58041e9247db22d0f97a6f76d45f338db0
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com>
---
src/mainboard/amd/olivehill/PlatformGnbPcie.c | 58 +++++++--------------------
1 file changed, 14 insertions(+), 44 deletions(-)
diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcie.c b/src/mainboard/amd/olivehill/PlatformGnbPcie.c
index 1131718..3e1c327 100644
--- a/src/mainboard/amd/olivehill/PlatformGnbPcie.c
+++ b/src/mainboard/amd/olivehill/PlatformGnbPcie.c
@@ -26,7 +26,7 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
-PCIe_PORT_DESCRIPTOR PortList [] = {
+static PCIe_PORT_DESCRIPTOR PortList [] = {
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
@@ -78,7 +78,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
}
};
-PCIe_DDI_DESCRIPTOR DdiList [] = {
+static PCIe_DDI_DESCRIPTOR DdiList [] = {
/* DP0 to HDMI0/DP */
{
0,
@@ -99,11 +99,11 @@ PCIe_DDI_DESCRIPTOR DdiList [] = {
},
};
-PCIe_COMPLEX_DESCRIPTOR Kabini = {
- DESCRIPTOR_TERMINATE_LIST,
- 0,
- PortList,
- DdiList
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+ DESCRIPTOR_TERMINATE_LIST,
+ 0,
+ PortList,
+ DdiList
};
/*---------------------------------------------------------------------------------------*/
@@ -127,10 +127,8 @@ OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
)
{
- AGESA_STATUS Status;
- VOID *KabiniPcieComplexListPtr;
- VOID *KabiniPciePortPtr;
- VOID *KabiniPcieDdiPtr;
+ AGESA_STATUS Status;
+ PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
@@ -139,46 +137,18 @@ OemCustomizeInitEarly (
/* */
/* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
/* */
- AllocHeapParams.RequestedBufferSize = sizeof(Kabini) + sizeof(PortList) + sizeof(DdiList);
+ AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
if ( Status!= AGESA_SUCCESS) {
- /* Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
+ /* Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR */
ASSERT(FALSE);
return;
}
- KabiniPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
- AllocHeapParams.BufferPtr += sizeof(Kabini);
- KabiniPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
- AllocHeapParams.BufferPtr += sizeof(PortList);
- KabiniPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
- LibAmdMemFill (KabiniPcieComplexListPtr,
- 0,
- sizeof (Kabini),
- &InitEarly->StdHeader);
-
- LibAmdMemFill (KabiniPciePortPtr,
- 0,
- sizeof (PortList),
- &InitEarly->StdHeader);
-
- LibAmdMemFill (KabiniPcieDdiPtr,
- 0,
- sizeof (DdiList),
- &InitEarly->StdHeader);
-
- LibAmdMemCopy (KabiniPcieComplexListPtr, &Kabini, sizeof (Kabini), &InitEarly->StdHeader);
- LibAmdMemCopy (KabiniPciePortPtr, &PortList[0], sizeof (PortList), &InitEarly->StdHeader);
- LibAmdMemCopy (KabiniPcieDdiPtr, &DdiList[0], sizeof (DdiList), &InitEarly->StdHeader);
-
- ((PCIe_COMPLEX_DESCRIPTOR*)KabiniPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)KabiniPciePortPtr;
- ((PCIe_COMPLEX_DESCRIPTOR*)KabiniPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)KabiniPcieDdiPtr;
-
- InitEarly->GnbConfig.PcieComplexList = KabiniPcieComplexListPtr;
+ PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+ LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
+ InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
}
1
0
New patch to review for coreboot: 849a8e5 AMD Olive Hill: Update ACPI routing & devicetree.cb
by Bruce Griffith 26 Jul '13
by Bruce Griffith 26 Jul '13
26 Jul '13
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3817
-gerrit
commit 849a8e50270223185986433484064d5665f8c49e
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Wed Mar 27 11:10:26 2013 -0600
AMD Olive Hill: Update ACPI routing & devicetree.cb
Update the ACPI DSDT.asl and routing.asl files to just include the
devices on kabini. Update comments and copyright dates.
Update the devicetree.cb file to just include hardware on the
kabini chip.
Change-Id: I83f7221c7b3b7aec3678db1fc33c0987477a3d71
Reviewed-by: Steven Sherk <steven.sherk(a)se-eng.com>
Reviewed-by: Kimarie Hoot <kimarie.hoot(a)se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com>
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/mainboard/amd/olivehill/acpi/routing.asl | 198 +++------------------------
src/mainboard/amd/olivehill/devicetree.cb | 9 +-
src/mainboard/amd/olivehill/dsdt.asl | 138 +++++++------------
3 files changed, 79 insertions(+), 266 deletions(-)
diff --git a/src/mainboard/amd/olivehill/acpi/routing.asl b/src/mainboard/amd/olivehill/acpi/routing.asl
index 1d54c0f..4ce45c9 100644
--- a/src/mainboard/amd/olivehill/acpi/routing.asl
+++ b/src/mainboard/amd/olivehill/acpi/routing.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,58 +29,29 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
Scope(\_SB) {
Name(PR0, Package(){
/* NB devices */
- /* Bus 0, Dev 0 - F15 Host Controller */
+ /* Bus 0, Dev 0 - F16 Host Controller */
+
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
Package(){0x0001FFFF, 0, INTB, 0 },
Package(){0x0001FFFF, 1, INTC, 0 },
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+
+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, INTD, 0 },
- Package(){0x0003FFFF, 1, INTA, 0 },
- Package(){0x0003FFFF, 2, INTB, 0 },
- Package(){0x0003FFFF, 3, INTC, 0 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, INTA, 0 },
- Package(){0x0004FFFF, 1, INTB, 0 },
- Package(){0x0004FFFF, 2, INTC, 0 },
- Package(){0x0004FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, INTB, 0 },
- Package(){0x0005FFFF, 1, INTC, 0 },
- Package(){0x0005FFFF, 2, INTD, 0 },
- Package(){0x0005FFFF, 3, INTA, 0 },
-
- /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
- Package(){0x0006FFFF, 0, INTC, 0 },
- Package(){0x0006FFFF, 1, INTD, 0 },
- Package(){0x0006FFFF, 2, INTA, 0 },
- Package(){0x0006FFFF, 3, INTB, 0 },
-
- /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
- Package(){0x0007FFFF, 0, INTD, 0 },
- Package(){0x0007FFFF, 1, INTA, 0 },
- Package(){0x0007FFFF, 2, INTB, 0 },
- Package(){0x0007FFFF, 3, INTC, 0 },
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
- /* SB devices */
- /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ /* FCH devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
Package(){0x0014FFFF, 3, INTD, 0 },
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
Package(){0x0012FFFF, 0, INTC, 0 },
Package(){0x0012FFFF, 1, INTB, 0 },
@@ -97,11 +68,6 @@ Scope(\_SB) {
/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, INTD, 0 },
- /* Bus 0, Dev 21 Pcie Bridge */
- Package(){0x0015FFFF, 0, INTA, 0 },
- Package(){0x0015FFFF, 1, INTB, 0 },
- Package(){0x0015FFFF, 2, INTC, 0 },
- Package(){0x0015FFFF, 3, INTD, 0 },
})
Name(APR0, Package(){
@@ -112,53 +78,22 @@ Scope(\_SB) {
Package(){0x0001FFFF, 0, 0, 17 },
Package(){0x0001FFFF, 1, 0, 18 },
- /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ /* Bus 0, Dev 2 - PCIe Bridges */
Package(){0x0002FFFF, 0, 0, 18 },
Package(){0x0002FFFF, 1, 0, 19 },
Package(){0x0002FFFF, 2, 0, 16 },
Package(){0x0002FFFF, 3, 0, 17 },
- /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
- Package(){0x0003FFFF, 0, 0, 19 },
- Package(){0x0003FFFF, 1, 0, 16 },
- Package(){0x0003FFFF, 2, 0, 17 },
- Package(){0x0003FFFF, 3, 0, 18 },
-
- /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
- Package(){0x0004FFFF, 0, 0, 16 },
- Package(){0x0004FFFF, 1, 0, 17 },
- Package(){0x0004FFFF, 2, 0, 18 },
- Package(){0x0004FFFF, 3, 0, 19 },
-
- /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
- Package(){0x0005FFFF, 0, 0, 17 },
- Package(){0x0005FFFF, 1, 0, 18 },
- Package(){0x0005FFFF, 2, 0, 19 },
- Package(){0x0005FFFF, 3, 0, 16 },
-
- /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
- Package(){0x0006FFFF, 0, 0, 18 },
- Package(){0x0006FFFF, 1, 0, 19 },
- Package(){0x0006FFFF, 2, 0, 16 },
- Package(){0x0006FFFF, 3, 0, 17 },
-
- /* Bus 0, Dev 7 - PCIe Bridge for network card */
- Package(){0x0007FFFF, 0, 0, 19 },
- Package(){0x0007FFFF, 1, 0, 16 },
- Package(){0x0007FFFF, 2, 0, 17 },
- Package(){0x0007FFFF, 3, 0, 18 },
-
- /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices in APIC mode */
- /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 },
- /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
- * EHCI, dev 18, 19 func 2 */
+ /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
+ /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
Package(){0x0012FFFF, 0, 0, 18 },
Package(){0x0012FFFF, 1, 0, 17 },
@@ -175,47 +110,23 @@ Scope(\_SB) {
/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, 0, 19 },
- /* Bus0, Dev 21 PCIE Bridge */
- Package(){0x0015FFFF, 0, 0, 16 },
- Package(){0x0015FFFF, 1, 0, 17 },
- Package(){0x0015FFFF, 2, 0, 18 },
- Package(){0x0015FFFF, 3, 0, 19 },
})
Name(PS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS2, Package(){
- /* The external GFX - Hooked to PCIe slot 2 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
-#if 1
- Name(PS3, Package(){
- /* The external GFX - Hooked to PCIe slot 3 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
- Name(APS3, Package(){
- /* The external GFX - Hooked to PCIe slot 3 */
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
- Package(){0x0000FFFF, 3, 0, 18 },
- })
-#endif
-
+ /* GFX */
Name(PS4, Package(){
- /* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
@@ -229,128 +140,61 @@ Scope(\_SB) {
Package(){0x0000FFFF, 3, 0, 19 },
})
+ /* GPP 0 */
Name(PS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(APS5, Package(){
- /* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, 0, 17 },
Package(){0x0000FFFF, 1, 0, 18 },
Package(){0x0000FFFF, 2, 0, 19 },
Package(){0x0000FFFF, 3, 0, 16 },
})
+ /* GPP 1 */
Name(PS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS6, Package(){
- /* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
+ /* GPP 2 */
Name(PS7, Package(){
- /* The onboard Ethernet chip - Dev 7 Olivehill Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS7, Package(){
- /* The onboard Ethernet chip - Dev 7 Olivehill Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
Package(){0x0000FFFF, 0, 0, 19 },
Package(){0x0000FFFF, 1, 0, 16 },
Package(){0x0000FFFF, 2, 0, 17 },
Package(){0x0000FFFF, 3, 0, 18 },
})
- Name(PE0, Package(){
- /* PCIe slot - Hooked to PCIe Bridge 0*/
+ /* GPP 3 */
+ Name(PS8, Package(){
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
- Name(APE0, Package(){
- /* PCIe slot - Hooked to PCIe Bridge 0*/
+ Name(APS8, Package(){
Package(){0x0000FFFF, 0, 0, 16 },
Package(){0x0000FFFF, 1, 0, 17 },
Package(){0x0000FFFF, 2, 0, 18 },
- Package(){0x0000FFFF, 3, 0, 19 },
- })
-
- Name(PE1, Package(){
- /* PCIe slot - Hooked to PCIe Bridge 1*/
- Package(){0x0000FFFF, 0, INTB, 0 },
- Package(){0x0000FFFF, 1, INTC, 0 },
- Package(){0x0000FFFF, 2, INTD, 0 },
- Package(){0x0000FFFF, 3, INTA, 0 },
- })
- Name(APE1, Package(){
- /* PCIe slot - Hooked to PCIe Bridge 1*/
- Package(){0x0000FFFF, 0, 0, 17 },
- Package(){0x0000FFFF, 1, 0, 18 },
- Package(){0x0000FFFF, 2, 0, 19 },
- Package(){0x0000FFFF, 3, 0, 16 },
- })
-
- Name(PE2, Package(){
- /* PCIe slot - Hooked to PCIe Bridge 2*/
- Package(){0x0000FFFF, 0, INTC, 0 },
- Package(){0x0000FFFF, 1, INTD, 0 },
- Package(){0x0000FFFF, 2, INTA, 0 },
- Package(){0x0000FFFF, 3, INTB, 0 },
- })
- Name(APE2, Package(){
- /* PCIe slot - Hooked to PCIe Bridge 2*/
- Package(){0x0000FFFF, 0, 0, 18 },
- Package(){0x0000FFFF, 1, 0, 19 },
- Package(){0x0000FFFF, 2, 0, 16 },
- Package(){0x0000FFFF, 3, 0, 17 },
- })
-
- Name(PE3, Package(){
- /* PCIe slot - Hooked to PCIe Bridge 3 */
- Package(){0x0000FFFF, 0, INTD, 0 },
- Package(){0x0000FFFF, 1, INTA, 0 },
- Package(){0x0000FFFF, 2, INTB, 0 },
- Package(){0x0000FFFF, 3, INTC, 0 },
- })
- Name(APE3, Package(){
- /* PCIe slot - Hooked to PCIe Bridge 3*/
- Package(){0x0000FFFF, 0, 0, 19 },
- Package(){0x0000FFFF, 1, 0, 16 },
- Package(){0x0000FFFF, 2, 0, 17 },
Package(){0x0000FFFF, 3, 0, 18 },
})
- /* SB PCI Bridge J21, J22 */
- Name(PCIB, Package(){
- /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
- Package(){0x0005FFFF, 0, 0, 0x14 },
- Package(){0x0005FFFF, 1, 0, 0x15 },
- Package(){0x0005FFFF, 2, 0, 0x16 },
- Package(){0x0005FFFF, 3, 0, 0x17 },
- Package(){0x0006FFFF, 0, 0, 0x15 },
- Package(){0x0006FFFF, 1, 0, 0x16 },
- Package(){0x0006FFFF, 2, 0, 0x17 },
- Package(){0x0006FFFF, 3, 0, 0x14 },
-/*
- Package(){0x0007FFFF, 0, 0, 0x16 },
- Package(){0x0007FFFF, 1, 0, 0x17 },
- Package(){0x0007FFFF, 2, 0, 0x14 },
- Package(){0x0007FFFF, 3, 0, 0x15 },
-*/
- })
}
diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb
index dc489d3..075d661 100644
--- a/src/mainboard/amd/olivehill/devicetree.cb
+++ b/src/mainboard/amd/olivehill/devicetree.cb
@@ -1,7 +1,7 @@
#
# This file is part of the coreboot project.
#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2013 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -18,6 +18,7 @@
#
chip northbridge/amd/agesa/family16kb/root_complex
+
device cpu_cluster 0 on
chip cpu/amd/agesa/family16kb
device lapic 0 on end
@@ -32,7 +33,7 @@ chip northbridge/amd/agesa/family16kb/root_complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge
- device pci 2.1 on end # x4 PCIe slot
+ device pci 2.1 on end # x4 PCIe slot
device pci 2.2 on end # mPCIe slot
device pci 2.3 on end # Realtek NIC
device pci 2.4 on end # Edge Connector
@@ -46,7 +47,7 @@ chip northbridge/amd/agesa/family16kb/root_complex
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.2 on end # USB
- device pci 14.0 on # SM
+ device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
@@ -73,4 +74,4 @@ chip northbridge/amd/agesa/family16kb/root_complex
end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
end #domain
-end #northbridge/amd/agesa/family16kb/root_complex
\ No newline at end of file
+end #northbridge/amd/agesa/family16kb/root_complex
diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl
index 2ab0a8c..20a74af 100644
--- a/src/mainboard/amd/olivehill/dsdt.asl
+++ b/src/mainboard/amd/olivehill/dsdt.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -922,7 +922,6 @@ DefinitionBlock (
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
@@ -1069,12 +1068,12 @@ DefinitionBlock (
}
Method(_STA, 0) {
/* DBGO("\\_SB\\PCI0\\_STA\n") */
- Return(0x0B) /* Status is visible */
+ Return(0x0B) /* Status is visible */
}
Method(_PRT,0) {
- If(PMOD){ Return(APR0) } /* APIC mode */
- Return (PR0) /* PIC Mode */
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
} /* end _PRT */
/* Describe the Northbridge devices Dev0 ,Func0*/
@@ -1082,126 +1081,103 @@ DefinitionBlock (
Name(_ADR, 0x00000000)
} /* end AMRT */
-#if 1
- /* Dev3 is also an external GFX bridge */
- Device(PBR3) {
- Name(_ADR, 0x00020000)
- Name(_PRW, Package() {0x18, 4})
- Method(_PRT,0) {
- If(PMOD){ Return(APS3) } /* APIC mode */
- Return (PS3) /* PIC Mode */
- } /* end _PRT */
- } /* end PBR3 */
-#endif
-
+ /* Gpp 0 */
Device(PBR4) {
Name(_ADR, 0x00020001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS4) } /* APIC mode */
- Return (PS4) /* PIC Mode */
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
+ /* Gpp 1 */
Device(PBR5) {
Name(_ADR, 0x00020002)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
+ /* Gpp 2 */
Device(PBR6) {
Name(_ADR, 0x00020003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS6) } /* APIC mode */
- Return (PS6) /* PIC Mode */
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
} /* end _PRT */
} /* end PBR6 */
- /* The onboard EtherNet chip */
+ /* Gpp 3 */
Device(PBR7) {
Name(_ADR, 0x00020004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
- If(PMOD){ Return(APS7) } /* APIC mode */
- Return (PS7) /* PIC Mode */
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
} /* end _PRT */
} /* end PBR7 */
- /* PCI slot 1, 2, 3 */
- Device(PIBR) {
- Name(_ADR, 0x00140004)
+ /* Gpp 4 */
+ Device(PBR8) {
+ Name(_ADR, 0x00020004)
Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS8) } /* APIC mode */
+ Return (PS8) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR8 */
- Method(_PRT, 0) {
- Return (PCIB)
- }
- }
/* Describe the Southbridge devices */
- Device(STCR) {
+ Device(STCR) { /* 0:11.0 - SATA */
Name(_ADR, 0x00110000)
//#include "acpi/sata.asl"
} /* end STCR */
- Device(UOH1) {
+ Device(UOH1) { /* 0:12.0 - OHCI */
Name(_ADR, 0x00120000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH1 */
- Device(UOH2) {
+ Device(UOH2) { /* 0:12.2 - EHCI */
Name(_ADR, 0x00120002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH2 */
- Device(UOH3) {
+ Device(UOH3) { /* 0:13.0 - OHCI */
Name(_ADR, 0x00130000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH3 */
- Device(UOH4) {
+ Device(UOH4) { /* 0:13.2 - EHCI */
Name(_ADR, 0x00130002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH4 */
- Device(UOH5) {
+ Device(UOH5) { /* 0:16.0 - OHCI */
Name(_ADR, 0x00160000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
- Device(UOH6) {
+ Device(UOH6) { /* 0:16.2 - EHCI */
Name(_ADR, 0x00160002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */
- Device(UEH1) {
- Name(_ADR, 0x00140005)
- Name(_PRW, Package() {0x0B, 3})
- } /* end UEH1 */
-
- Device(XHC0) {
+ Device(XHC0) { /* 0:10.0 - XHCI */
Name(_ADR, 0x00100000)
Name(_PRW, Package() {0x0B, 4})
} /* end XHC0 */
- Device(XHC1) {
- Name(_ADR, 0x00100001)
- Name(_PRW, Package() {0x0B, 4})
- } /* end XHC1 */
- Device(SBUS) {
+ Device(SBUS) { /* 0:14.0 - SMBUS */
Name(_ADR, 0x00140000)
} /* end SBUS */
- /* Primary (and only) IDE channel */
- Device(IDEC) {
- Name(_ADR, 0x00140001)
- //#include "acpi/ide.asl"
- } /* end IDEC */
-
- Device(AZHD) {
+ Device(AZHD) { /* 0:14.2 - HD Audio */
Name(_ADR, 0x00140002)
OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
Field(AZPD, AnyAcc, NoLock, Preserve) {
@@ -1236,7 +1212,7 @@ DefinitionBlock (
}
} /* end AZHD */
- Device(LIBR) {
+ Device(LIBR) { /* 0:14.3 - LPC */
Name(_ADR, 0x00140003)
/* Method(_INI) {
* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
@@ -1328,17 +1304,9 @@ DefinitionBlock (
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
} /* end LIBR */
- Device(HPBR) {
- Name(_ADR, 0x00140004)
- } /* end HostPciBr */
-
- Device(ACAD) {
- Name(_ADR, 0x00140005)
- } /* end Ac97audio */
-
- Device(ACMD) {
- Name(_ADR, 0x00140006)
- } /* end Ac97modem */
+ Device(SDCN) { /* 0:14.7 - SD Controller */
+ Name(_ADR, 0x00140007)
+ } /* end SDCN */
Name(CRES, ResourceTemplate() {
IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
@@ -1368,26 +1336,26 @@ DefinitionBlock (
Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
- /* memory space for PCI BARs below 4GB */
- Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+ /* memory space for PCI BARs below 4GB */
+ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
}) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) {
/* DBGO("\\_SB\\PCI0\\_CRS\n") */
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
- CreateDWordField(CRES, ^MMIO._LEN, MM1L)
- /*
- * Declare memory between TOM1 and 4GB as available
- * for PCI MMIO.
- * Use ShiftLeft to avoid 64bit constant (for XP).
- * This will work even if the OS does 32bit arithmetic, as
- * 32bit (0x00000000 - TOM1) will wrap and give the same
- * result as 64bit (0x100000000 - TOM1).
- */
- Store(TOM1, MM1B)
- ShiftLeft(0x10000000, 4, Local0)
- Subtract(Local0, TOM1, Local0)
- Store(Local0, MM1L)
+ CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+ /*
+ * Declare memory between TOM1 and 4GB as available
+ * for PCI MMIO.
+ * Use ShiftLeft to avoid 64bit constant (for XP).
+ * This will work even if the OS does 32bit arithmetic, as
+ * 32bit (0x00000000 - TOM1) will wrap and give the same
+ * result as 64bit (0x100000000 - TOM1).
+ */
+ Store(TOM1, MM1B)
+ ShiftLeft(0x10000000, 4, Local0)
+ Subtract(Local0, TOM1, Local0)
+ Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */
1
0
New patch to review for coreboot: 972b0e3 AMD OliveHill: Remove default VBIOS vendor/device ID
by Bruce Griffith 26 Jul '13
by Bruce Griffith 26 Jul '13
26 Jul '13
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3816
-gerrit
commit 972b0e323dc1519a1ff1433de0e16232534391cc
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Mon Jul 8 11:33:45 2013 -0600
AMD OliveHill: Remove default VBIOS vendor/device ID
The VBIOS device ID is set by processor family using the
map_oprom_vendev() function in the northbridge code. There
is rarely a reason why this should be overridden by the mainboard.
Since Kabini includes a default VBIOS vendor/device ID in the
northbridge Kconfig code, remove the setting from the Olive Hill
mainboard settings.
Change-Id: Icd69155f5b51105d564dd82c89e4bb54a6118a82
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/mainboard/amd/olivehill/Kconfig | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
index 085dc7a..adb5d81 100644
--- a/src/mainboard/amd/olivehill/Kconfig
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -93,10 +93,6 @@ config ONBOARD_VGA_IS_PRIMARY
bool
default y
-config VGA_BIOS_ID
- string
- default "1002,9832"
-
config HUDSON_LEGACY_FREE
bool
default y
1
0
New patch to review for coreboot: 8e5cfa8 AMD OliveHill: Change SB800 references to Yangtze
by Bruce Griffith 26 Jul '13
by Bruce Griffith 26 Jul '13
26 Jul '13
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3815
-gerrit
commit 8e5cfa89afeb379f1e0cf23972c50d6d645f653b
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Sun Jul 7 02:04:16 2013 -0600
AMD OliveHill: Change SB800 references to Yangtze
Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/mainboard/amd/olivehill/Kconfig | 4 +++
src/mainboard/amd/olivehill/get_bus_conf.c | 30 +++++++++----------
src/mainboard/amd/olivehill/irq_tables.c | 10 +++----
src/mainboard/amd/olivehill/mptable.c | 48 +++++++++++++++---------------
src/mainboard/amd/olivehill/romstage.c | 2 +-
5 files changed, 49 insertions(+), 45 deletions(-)
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
index 141da33..085dc7a 100644
--- a/src/mainboard/amd/olivehill/Kconfig
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -97,6 +97,10 @@ config VGA_BIOS_ID
string
default "1002,9832"
+config HUDSON_LEGACY_FREE
+ bool
+ default y
+
config WARNINGS_ARE_ERRORS
bool
default n
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
index fca2625..0d379d5 100644
--- a/src/mainboard/amd/olivehill/get_bus_conf.c
+++ b/src/mainboard/amd/olivehill/get_bus_conf.c
@@ -30,8 +30,8 @@
* and acpi_tables busnum is default.
*/
u8 bus_isa;
-u8 bus_sb800[3];
-u32 apicid_sb800;
+u8 bus_yangtze[3];
+u32 apicid_yangtze;
/*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
@@ -43,7 +43,7 @@ u32 pci1234x[] = {
};
u32 bus_type[256];
-u32 sbdn_sb800;
+u32 sbdn_yangtze;
static u32 get_bus_conf_done = 0;
@@ -98,10 +98,10 @@ void get_bus_conf(void)
pci_write_config32(dev, 0xF8, 0);
pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
- sbdn_sb800 = 0;
+ sbdn_yangtze = 0;
for (i = 0; i < 3; i++) {
- bus_sb800[i] = 0;
+ bus_yangtze[i] = 0;
}
for (i = 0; i < 256; i++) {
@@ -110,34 +110,34 @@ void get_bus_conf(void)
bus_type[0] = 1; /* pci */
- // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
+ // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff;
- /* sb800 */
- dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+ /* yangtze */
+ dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4));
if (dev) {
- bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
- for (j = bus_sb800[1]; j < bus_isa; j++)
+ for (j = bus_yangtze[1]; j < bus_isa; j++)
bus_type[j] = 1;
}
for (i = 0; i < 4; i++) {
- dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
+ dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i));
if (dev) {
- bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
}
- for (j = bus_sb800[2]; j < bus_isa; j++)
+ for (j = bus_yangtze[2]; j < bus_isa; j++)
bus_type[j] = 1;
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS;
- apicid_sb800 = apicid_base;
+ apicid_yangtze = apicid_base;
}
diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c
index 3bcd3fb..c7f2cce 100644
--- a/src/mainboard/amd/olivehill/irq_tables.c
+++ b/src/mainboard/amd/olivehill/irq_tables.c
@@ -44,8 +44,8 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
}
extern u8 bus_isa;
-extern u8 bus_sb800[2];
-extern unsigned long sbdn_sb800;
+extern u8 bus_yangtze[2];
+extern unsigned long sbdn_yangtze;
unsigned long write_pirq_routing_table(unsigned long addr)
{
@@ -72,8 +72,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_sb800[0];
- pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
+ pirq->rtr_bus = bus_yangtze[0];
+ pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4;
pirq->exclusive_irqs = 0;
@@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
- write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
+ write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
index 7db7160..118f860 100644
--- a/src/mainboard/amd/olivehill/mptable.c
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -30,11 +30,11 @@
//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_sb800[3];
+extern u8 bus_yangtze[3];
extern u32 bus_type[256];
-extern u32 sbdn_sb800;
-extern u32 apicid_sb800;
+extern u32 sbdn_yangtze;
+extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -103,10 +103,10 @@ static void *smp_write_config_table(void *v)
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);
- apicid_sb800 = IO_APIC_ID;
- smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
+ apicid_yangtze = IO_APIC_ID;
+ smp_write_ioapic(mc, apicid_yangtze, 0x21, dword);
- smp_write_ioapic(mc, apicid_sb800+1, 0x21, 0xFEC20000);
+ smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
@@ -160,13 +160,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
@@ -195,26 +195,26 @@ static void *smp_write_config_table(void *v)
/* PCI slots */
/* PCI_SLOT 0. */
- PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+ PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
+ PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
+ PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
+ PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
- PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+ PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
+ PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
+ PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
+ PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
- PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+ PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
+ PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
+ PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
+ PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
+
+ PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
+ PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
+ PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index e74c7f2..f4906da 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
post_code(0x38);
- printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+ printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
post_code(0x39);
1
0
New patch to review for coreboot: f887ad2 AMD OliveHill: Enable HDMI audio setting in build options
by Bruce Griffith 26 Jul '13
by Bruce Griffith 26 Jul '13
26 Jul '13
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3814
-gerrit
commit f887ad262b6f224ee8dbdea3751ad27472b1a5b5
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Wed Jul 10 01:26:26 2013 -0600
AMD OliveHill: Enable HDMI audio setting in build options
Change-Id: Ifc180e6fcd594dbedc2512ea5bef283a3ad689d3
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/mainboard/amd/olivehill/buildOpts.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
index df5e35a..fff0a45 100644
--- a/src/mainboard/amd/olivehill/buildOpts.c
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -163,7 +163,7 @@
//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
#define BLDCFG_CFG_ABM_SUPPORT TRUE
-
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
1
0
Patch set updated for coreboot: 5ca3cb6 AMD OliveHill: Add new AMD mainboard using Kabini processor
by Bruce Griffith 26 Jul '13
by Bruce Griffith 26 Jul '13
26 Jul '13
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3784
-gerrit
commit 5ca3cb6e767ded05938ac5b6a289147e260cbeff
Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com>
Date: Tue Jul 9 17:42:43 2013 +0800
AMD OliveHill: Add new AMD mainboard using Kabini processor
Change-Id: I1f252b67c039d28df96e8dfd458a1ca6a7dbc816
Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com>
---
src/mainboard/amd/Kconfig | 3 +
src/mainboard/amd/olivehill/BiosCallOuts.c | 308 +++++
src/mainboard/amd/olivehill/BiosCallOuts.h | 31 +
src/mainboard/amd/olivehill/Kconfig | 104 ++
src/mainboard/amd/olivehill/Makefile.inc | 28 +
src/mainboard/amd/olivehill/OptionsIds.h | 67 +
src/mainboard/amd/olivehill/PlatformGnbPcie.c | 184 +++
.../amd/olivehill/PlatformGnbPcieComplex.h | 32 +
src/mainboard/amd/olivehill/acpi/AmdImc.asl | 114 ++
src/mainboard/amd/olivehill/acpi/ide.asl | 244 ++++
src/mainboard/amd/olivehill/acpi/routing.asl | 356 +++++
src/mainboard/amd/olivehill/acpi/sata.asl | 148 ++
src/mainboard/amd/olivehill/acpi/usb.asl | 114 ++
src/mainboard/amd/olivehill/acpi_tables.c | 333 +++++
src/mainboard/amd/olivehill/agesawrapper.c | 771 +++++++++++
src/mainboard/amd/olivehill/agesawrapper.h | 97 ++
src/mainboard/amd/olivehill/buildOpts.c | 507 +++++++
src/mainboard/amd/olivehill/cmos.layout | 114 ++
src/mainboard/amd/olivehill/devicetree.cb | 76 +
src/mainboard/amd/olivehill/dsdt.asl | 1448 ++++++++++++++++++++
src/mainboard/amd/olivehill/get_bus_conf.c | 143 ++
src/mainboard/amd/olivehill/irq_tables.c | 112 ++
src/mainboard/amd/olivehill/mainboard.c | 51 +
src/mainboard/amd/olivehill/mptable.c | 245 ++++
src/mainboard/amd/olivehill/romstage.c | 192 +++
25 files changed, 5822 insertions(+)
diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig
index 2276129..80bd2b1 100644
--- a/src/mainboard/amd/Kconfig
+++ b/src/mainboard/amd/Kconfig
@@ -41,6 +41,8 @@ config BOARD_AMD_PARMER
bool "Parmer"
config BOARD_AMD_THATCHER
bool "Thatcher"
+config BOARD_AMD_OLIVEHILL
+ bool "Olive Hill"
endchoice
source "src/mainboard/amd/db800/Kconfig"
@@ -62,6 +64,7 @@ source "src/mainboard/amd/torpedo/Kconfig"
source "src/mainboard/amd/union_station/Kconfig"
source "src/mainboard/amd/parmer/Kconfig"
source "src/mainboard/amd/thatcher/Kconfig"
+source "src/mainboard/amd/olivehill/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c
new file mode 100644
index 0000000..3efaa2b
--- /dev/null
+++ b/src/mainboard/amd/olivehill/BiosCallOuts.c
@@ -0,0 +1,308 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "BiosCallOuts.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "cbfs.h"
+
+STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_ALLOCATE_BUFFER, fam16kb_AllocateBuffer },
+ {AGESA_DEALLOCATE_BUFFER, fam16kb_DeallocateBuffer },
+ {AGESA_DO_RESET, fam16kb_Reset },
+ {AGESA_LOCATE_BUFFER, fam16kb_LocateBuffer },
+ {AGESA_READ_SPD, fam16kb_ReadSpd },
+ {AGESA_READ_SPD_RECOVERY, fam16kb_DefaultRet },
+ {AGESA_RUNFUNC_ONAP, fam16kb_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA, fam16kb_GetIdsInitData },
+ {AGESA_HOOKBEFORE_DQS_TRAINING, fam16kb_HookBeforeDQSTraining },
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam16kb_HookBeforeExitSelfRefresh },
+ {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam16kb_HookGfxGetVbiosImage }
+};
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ AGESA_STATUS CalloutStatus;
+ UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
+
+ for (i = 0; i < CallOutCount; i++)
+ {
+ if (BiosCallouts[i].CalloutName == Func)
+ break;
+ }
+
+ if(i >= CallOutCount)
+ return AGESA_UNSUPPORTED;
+
+ CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+
+ return CalloutStatus;
+}
+
+/**
+ * AMD Olivehill Platform ALC272 Verb Table
+ */
+static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = {
+ {0x11, 0x411111F0},
+ {0x12, 0x411111F0},
+ {0x13, 0x411111F0},
+ {0x14, 0x411111F0},
+ {0x15, 0x411111F0},
+ {0x16, 0x411111F0},
+ {0x17, 0x411111F0},
+ {0x18, 0x01a19840},
+ {0x19, 0x411111F0},
+ {0x1a, 0x01813030},
+ {0x1b, 0x411111F0},
+ {0x1d, 0x40130605},
+ {0x1e, 0x01441120},
+ {0x21, 0x01211010},
+ {0xff, 0xffffffff}
+};
+
+static const CODEC_TBL_LIST OlivehillCodecTableList[] =
+{
+ {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+#define FAN_INPUT_INTERNAL_DIODE 0
+#define FAN_INPUT_TEMP0 1
+#define FAN_INPUT_TEMP1 2
+#define FAN_INPUT_TEMP2 3
+#define FAN_INPUT_TEMP3 4
+#define FAN_INPUT_TEMP0_FILTER 5
+#define FAN_INPUT_ZERO 6
+#define FAN_INPUT_DISABLED 7
+
+#define FAN_AUTOMODE (1 << 0)
+#define FAN_LINEARMODE (1 << 1)
+#define FAN_STEPMODE ~(1 << 1)
+#define FAN_POLARITY_HIGH (1 << 2)
+#define FAN_POLARITY_LOW ~(1 << 2)
+
+/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
+#define FREQ_28KHZ 0x0
+#define FREQ_25KHZ 0x1
+#define FREQ_23KHZ 0x2
+#define FREQ_21KHZ 0x3
+#define FREQ_29KHZ 0x4
+#define FREQ_18KHZ 0x5
+#define FREQ_100HZ 0xF7
+#define FREQ_87HZ 0xF8
+#define FREQ_58HZ 0xF9
+#define FREQ_44HZ 0xFA
+#define FREQ_35HZ 0xFB
+#define FREQ_29HZ 0xFC
+#define FREQ_22HZ 0xFD
+#define FREQ_14HZ 0xFE
+#define FREQ_11HZ 0xFF
+
+/* Olivehill Hardware Monitor Fan Control
+ * Hardware limitation:
+ * HWM failed to read the input temperture vi I2C,
+ * if other software switch the I2C switch by mistake or intention.
+ * We recommend to using IMC to control Fans, instead of HWM.
+ */
+#if 0
+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+ FCH_HWM_FAN_CTR oem_factl[5] = {
+ /*temperatuer input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */
+ /* Olivehill FanOUT0 Fan header J32 */
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ /* Olivehill FanOUT1 Fan header J31*/
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ };
+ LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
+
+ /* Enable IMC fan control. the recommand way */
+#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1)
+ /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
+ FchParams->Hwm.HwMonitorEnable = TRUE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
+
+ FchParams->Imc.ImcEnable = TRUE;
+ FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+
+ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
+
+ /* Thermal Zone Parameter */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0;
+
+ /* IMC Fan Policy temperature thresholds */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
+
+ /* IMC Fan Policy PWM Settings */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */
+
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
+
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
+
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */
+
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0;
+
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
+
+ /* IMC Function */
+ FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8;
+
+ /* NOTE:
+ * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
+ * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
+ * so we remove it from AGESA code. Please Seee FchInitLateHwm.
+ */
+
+#else /* HWM fan control, the way not recommand */
+ FchParams->Imc.ImcEnable = FALSE;
+ FchParams->Hwm.HwMonitorEnable = TRUE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
+
+#endif /* CONFIG_HUDSON_IMC_FWM */
+}
+#endif
+
+/**
+ * Fch Oem setting callback
+ *
+ * Configure platform specific Hudson device,
+ * such Azalia, SATA, IMC etc.
+ */
+AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
+{
+ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData;
+
+ if (FchParams->StdHeader->Func == AMD_INIT_RESET) {
+ //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) {
+ FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->F1.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]);
+ /* Azalia Controller Front Panel OEM Table Pointer */
+
+ /* Fan Control */
+ //oem_fan_control(FchParams_env);
+
+ /* XHCI configuration */
+#if CONFIG_HUDSON_XHCI_ENABLE
+ FchParams_env->Usb.Xhci0Enable = TRUE;
+#else
+ FchParams_env->Usb.Xhci0Enable = FALSE;
+#endif
+ FchParams_env->Usb.Xhci1Enable = FALSE;
+
+ /* sata configuration */
+ }
+ printk(BIOS_DEBUG, "Done\n");
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.h b/src/mainboard/amd/olivehill/BiosCallOuts.h
new file mode 100644
index 0000000..186cad5
--- /dev/null
+++ b/src/mainboard/amd/olivehill/BiosCallOuts.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BIOS_CALLOUT_H_
+#define _BIOS_CALLOUT_H_
+
+#include <northbridge/amd/agesa/family16kb/fam16kb_callouts.h>
+
+/* CALLOUT Initialization */
+AGESA_STATUS GetBiosCallout(UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* FCH OEM Config*/
+AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+
+#endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig
new file mode 100644
index 0000000..141da33
--- /dev/null
+++ b/src/mainboard/amd/olivehill/Kconfig
@@ -0,0 +1,104 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+if BOARD_AMD_OLIVEHILL
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_AGESA_FAMILY16_KB
+ select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
+ select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_RESUME
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ select LIFT_BSP_APIC_ID
+ select SERIAL_CPU_INIT
+ select AMDMCT
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_4096
+ select GFXUMA
+
+config MAINBOARD_DIR
+ string
+ default amd/olivehill
+
+config APIC_ID_OFFSET
+ hex
+ default 0x0
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "OliveHill"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config MEM_TRAIN_SEQ
+ int
+ default 2
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
+config ACPI_SSDTX_NUM
+ int
+ default 0
+
+config RAMBASE
+ hex
+ default 0x200000
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,9832"
+
+config WARNINGS_ARE_ERRORS
+ bool
+ default n
+
+endif # BOARD_AMD_OLIVEHILL
diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc
new file mode 100644
index 0000000..a83297a
--- /dev/null
+++ b/src/mainboard/amd/olivehill/Makefile.inc
@@ -0,0 +1,28 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h
new file mode 100644
index 0000000..0a1d328
--- /dev/null
+++ b/src/mainboard/amd/olivehill/OptionsIds.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcie.c b/src/mainboard/amd/olivehill/PlatformGnbPcie.c
new file mode 100644
index 0000000..1131718
--- /dev/null
+++ b/src/mainboard/amd/olivehill/PlatformGnbPcie.c
@@ -0,0 +1,184 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+PCIe_PORT_DESCRIPTOR PortList [] = {
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
+ HotplugEnhanced, /* HotplugDisabled */
+ PcieGen2, /* PcieGenMaxSupported */
+ PcieGen2, /* PcieGenMaxSupported */
+ AspmDisabled, 0x01, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+ HotplugEnhanced, /* HotplugDisabled */
+ PcieGen2, /* PcieGenMaxSupported */
+ PcieGen2, /* PcieGenMaxSupported */
+ AspmDisabled, 0x02, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+ {
+ 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+ HotplugEnhanced, /* HotplugDisabled */
+ PcieGen2, /* PcieGenMaxSupported */
+ PcieGen2, /* PcieGenMaxSupported */
+ AspmDisabled, 0x03, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
+ HotplugEnhanced, /* HotplugDisabled */
+ PcieGen2, /* PcieGenMaxSupported */
+ PcieGen2, /* PcieGenMaxSupported */
+ AspmDisabled, 0x04, 0)
+ },
+ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+ {
+ DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+ HotplugEnhanced, /* HotplugDisabled */
+ PcieGen2, /* PcieGenMaxSupported */
+ PcieGen2, /* PcieGenMaxSupported */
+ AspmDisabled, 0x05, 0)
+ }
+};
+
+PCIe_DDI_DESCRIPTOR DdiList [] = {
+ /* DP0 to HDMI0/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+ },
+ /* DP1 to FCH */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+ },
+ /* DP2 to HDMI1/DP */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
+ },
+};
+
+PCIe_COMPLEX_DESCRIPTOR Kabini = {
+ DESCRIPTOR_TERMINATE_LIST,
+ 0,
+ PortList,
+ DdiList
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This is the stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ AGESA_STATUS Status;
+ VOID *KabiniPcieComplexListPtr;
+ VOID *KabiniPciePortPtr;
+ VOID *KabiniPcieDdiPtr;
+
+ ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+ /* GNB PCIe topology Porting */
+
+ /* */
+ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
+ /* */
+ AllocHeapParams.RequestedBufferSize = sizeof(Kabini) + sizeof(PortList) + sizeof(DdiList);
+
+ AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+ AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+ Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+ if ( Status!= AGESA_SUCCESS) {
+ /* Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
+ ASSERT(FALSE);
+ return;
+ }
+
+ KabiniPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof(Kabini);
+ KabiniPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof(PortList);
+ KabiniPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ LibAmdMemFill (KabiniPcieComplexListPtr,
+ 0,
+ sizeof (Kabini),
+ &InitEarly->StdHeader);
+
+ LibAmdMemFill (KabiniPciePortPtr,
+ 0,
+ sizeof (PortList),
+ &InitEarly->StdHeader);
+
+ LibAmdMemFill (KabiniPcieDdiPtr,
+ 0,
+ sizeof (DdiList),
+ &InitEarly->StdHeader);
+
+ LibAmdMemCopy (KabiniPcieComplexListPtr, &Kabini, sizeof (Kabini), &InitEarly->StdHeader);
+ LibAmdMemCopy (KabiniPciePortPtr, &PortList[0], sizeof (PortList), &InitEarly->StdHeader);
+ LibAmdMemCopy (KabiniPcieDdiPtr, &DdiList[0], sizeof (DdiList), &InitEarly->StdHeader);
+
+ ((PCIe_COMPLEX_DESCRIPTOR*)KabiniPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)KabiniPciePortPtr;
+ ((PCIe_COMPLEX_DESCRIPTOR*)KabiniPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)KabiniPcieDdiPtr;
+
+ InitEarly->GnbConfig.PcieComplexList = KabiniPcieComplexListPtr;
+}
diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h b/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h
new file mode 100644
index 0000000..1db8b2d
--- /dev/null
+++ b/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ );
+
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/olivehill/acpi/AmdImc.asl b/src/mainboard/amd/olivehill/acpi/AmdImc.asl
new file mode 100644
index 0000000..074dd7c
--- /dev/null
+++ b/src/mainboard/amd/olivehill/acpi/AmdImc.asl
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+//BTDC Due to IMC Fan, ACPI control codes
+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
+Field(IMIO , ByteAcc, NoLock, Preserve) {
+ IMCX,8,
+ IMCA,8
+}
+
+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
+ Offset(0x80),
+ MSTI, 8,
+ MITS, 8,
+ MRG0, 8,
+ MRG1, 8,
+ MRG2, 8,
+ MRG3, 8,
+}
+
+Method(WACK, 0)
+{
+ Store(0, Local0)
+ While (LNotEqual(Local0, 0xFA)) {
+ Store(MRG0, Local0)
+ Sleep(10)
+ }
+}
+
+//Init
+Method (ITZE, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
+
+//Sleep
+Method (IMSP, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(1, MRG1)
+ Store(0, MRG2)
+ Store(0x98, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0xB4, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+}
+
+//Wake
+Method (IMWK, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
diff --git a/src/mainboard/amd/olivehill/acpi/ide.asl b/src/mainboard/amd/olivehill/acpi/ide.asl
new file mode 100644
index 0000000..765a67e
--- /dev/null
+++ b/src/mainboard/amd/olivehill/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "ide.asl"
+ }
+ }
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+ 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+ 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+ 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+ 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+ Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+ PPTS, 8, /* Primary PIO Slave Timing */
+ PPTM, 8, /* Primary PIO Master Timing */
+ OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
+ PMTM, 8, /* Primary MWDMA Master Timing */
+ OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
+ OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
+ PPSM, 4, /* Primary PIO slave Mode */
+ OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
+ OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
+ PDSM, 4, /* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+ Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
+ Increment(Local0)
+ Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
+ Increment(Local1)
+ Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+ Name (_ADR, Zero)
+ Method(_GTM, 0)
+ {
+ NAME(OTBF, Buffer(20) { /* out buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
+ CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+ /* Just return if the channel is disabled */
+ If(And(PPCR, 0x01)) { /* primary PIO control */
+ Return(OTBF)
+ }
+
+ /* Always tell them independent timing available and IOChannelReady used on both drives */
+ Or(BFFG, 0x1A, BFFG)
+
+ Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
+ Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
+
+ If(And(PDCR, 0x01)) { /* It's under UDMA mode */
+ Or(BFFG, 0x01, BFFG)
+ Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+ }
+ Else {
+ Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
+ }
+
+ If(And(PDCR, 0x02)) { /* It's under UDMA mode */
+ Or(BFFG, 0x04, BFFG)
+ Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+ }
+ Else {
+ Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
+ }
+
+ Return(OTBF) /* out buffer */
+ } /* End Method(_GTM) */
+
+ Method(_STM, 3, NotSerialized)
+ {
+ NAME(INBF, Buffer(20) { /* in buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+ Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+ Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+ Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+ If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDMM,)
+ Or(PDCR, 0x01, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTM)
+ }
+ }
+
+ If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDSM,)
+ Or(PDCR, 0x02, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTS)
+ }
+ }
+ /* Return(INBF) */
+ } /*End Method(_STM) */
+ Device(MST)
+ {
+ Name(_ADR, 0)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xA0, CMDA)
+ Store(0xA0, CMDB)
+ Store(0xA0, CMDC)
+
+ Or(PPMM, 0x08, POMD)
+
+ If(And(PDCR, 0x01)) {
+ Or(PDMM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTM),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(MST) */
+
+ Device(SLAV)
+ {
+ Name(_ADR, 1)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xB0, CMDA)
+ Store(0xB0, CMDB)
+ Store(0xB0, CMDC)
+
+ Or(PPSM, 0x08, POMD)
+
+ If(And(PDCR, 0x02)) {
+ Or(PDSM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTS),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(SLAV) */
+}
diff --git a/src/mainboard/amd/olivehill/acpi/routing.asl b/src/mainboard/amd/olivehill/acpi/routing.asl
new file mode 100644
index 0000000..1d54c0f
--- /dev/null
+++ b/src/mainboard/amd/olivehill/acpi/routing.asl
@@ -0,0 +1,356 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, INTD, 0 },
+ Package(){0x0003FFFF, 1, INTA, 0 },
+ Package(){0x0003FFFF, 2, INTB, 0 },
+ Package(){0x0003FFFF, 3, INTC, 0 },
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, INTB, 0 },
+ Package(){0x0005FFFF, 1, INTC, 0 },
+ Package(){0x0005FFFF, 2, INTD, 0 },
+ Package(){0x0005FFFF, 3, INTA, 0 },
+
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ Package(){0x0006FFFF, 0, INTC, 0 },
+ Package(){0x0006FFFF, 1, INTD, 0 },
+ Package(){0x0006FFFF, 2, INTA, 0 },
+ Package(){0x0006FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ Package(){0x0007FFFF, 0, INTD, 0 },
+ Package(){0x0007FFFF, 1, INTA, 0 },
+ Package(){0x0007FFFF, 2, INTB, 0 },
+ Package(){0x0007FFFF, 3, INTC, 0 },
+
+ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+ /* SB devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, 0, 19 },
+ Package(){0x0003FFFF, 1, 0, 16 },
+ Package(){0x0003FFFF, 2, 0, 17 },
+ Package(){0x0003FFFF, 3, 0, 18 },
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, 0, 17 },
+ Package(){0x0005FFFF, 1, 0, 18 },
+ Package(){0x0005FFFF, 2, 0, 19 },
+ Package(){0x0005FFFF, 3, 0, 16 },
+
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ Package(){0x0006FFFF, 0, 0, 18 },
+ Package(){0x0006FFFF, 1, 0, 19 },
+ Package(){0x0006FFFF, 2, 0, 16 },
+ Package(){0x0006FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ Package(){0x0007FFFF, 0, 0, 19 },
+ Package(){0x0007FFFF, 1, 0, 16 },
+ Package(){0x0007FFFF, 2, 0, 17 },
+ Package(){0x0007FFFF, 3, 0, 18 },
+
+ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 16 },
+ Package(){0x0015FFFF, 1, 0, 17 },
+ Package(){0x0015FFFF, 2, 0, 18 },
+ Package(){0x0015FFFF, 3, 0, 19 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+#if 1
+ Name(PS3, Package(){
+ /* The external GFX - Hooked to PCIe slot 3 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS3, Package(){
+ /* The external GFX - Hooked to PCIe slot 3 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+#endif
+
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Dev 7 Olivehill Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Dev 7 Olivehill Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PE0, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 0*/
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APE0, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 0*/
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PE1, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 1*/
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APE1, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 1*/
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PE2, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 2*/
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APE2, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 2*/
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PE3, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 3 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APE3, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 3*/
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ /* SB PCI Bridge J21, J22 */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+
+ Package(){0x0006FFFF, 0, 0, 0x15 },
+ Package(){0x0006FFFF, 1, 0, 0x16 },
+ Package(){0x0006FFFF, 2, 0, 0x17 },
+ Package(){0x0006FFFF, 3, 0, 0x14 },
+/*
+ Package(){0x0007FFFF, 0, 0, 0x16 },
+ Package(){0x0007FFFF, 1, 0, 0x17 },
+ Package(){0x0007FFFF, 2, 0, 0x14 },
+ Package(){0x0007FFFF, 3, 0, 0x15 },
+*/
+ })
+}
diff --git a/src/mainboard/amd/olivehill/acpi/sata.asl b/src/mainboard/amd/olivehill/acpi/sata.asl
new file mode 100644
index 0000000..8fd9e9b
--- /dev/null
+++ b/src/mainboard/amd/olivehill/acpi/sata.asl
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(SATA) {
+ Name(_ADR, 0x00110000)
+ #include "sata.asl"
+ }
+ }
+}
+*/
+
+Name(STTM, Buffer(20) {
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+ \_GPE._L1F()
+}
+
+Device(PMRY)
+{
+ Name(_ADR, 0)
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(PMST) {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P0IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ }/* end of PMST */
+
+ Device(PSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P1IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of PSLA */
+} /* end of PMRY */
+
+Device(SEDY)
+{
+ Name(_ADR, 1) /* IDE Scondary Channel */
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(SMST)
+ {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P2IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SMST */
+
+ Device(SSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P3IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SSLA */
+} /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+ Method(_L1F,0x0,NotSerialized) {
+ if (\_SB.P0PR) {
+ if (LGreater(\_SB.P0IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P0PR)
+ }
+
+ if (\_SB.P1PR) {
+ if (LGreater(\_SB.P1IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P1PR)
+ }
+
+ if (\_SB.P2PR) {
+ if (LGreater(\_SB.P2IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P2PR)
+ }
+
+ if (\_SB.P3PR) {
+ if (LGreater(\_SB.P3IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P3PR)
+ }
+ }
+}
diff --git a/src/mainboard/amd/olivehill/acpi/usb.asl b/src/mainboard/amd/olivehill/acpi/usb.asl
new file mode 100644
index 0000000..7780a15
--- /dev/null
+++ b/src/mainboard/amd/olivehill/acpi/usb.asl
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+Method(UCOC, 0) {
+ Sleep(20)
+ Store(0x13,CMTI)
+ Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+ Scope (\_GPE) {
+ Method (_L13) {
+ }
+ }
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+ Scope (\_GPE) {
+ Method (_L14) {
+ }
+ }
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+ Scope (\_GPE) {
+ Method (_L15) {
+ }
+ }
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+ Scope (\_GPE) {
+ Method (_L16) {
+ }
+ }
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+ Scope (\_GPE) {
+ Method (_L19) {
+ }
+ }
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+ Scope (\_GPE) {
+ Method (_L1A) {
+ }
+ }
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1C) { */
+ Method (_L06) {
+ }
+ }
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1D) { */
+ Method (_L07) {
+ }
+ }
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+ Scope (\_GPE) {
+ Method (_L17) {
+ }
+ }
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+ Scope (\_GPE) {
+ Method (_L0E) {
+ }
+ }
+}
diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c
new file mode 100644
index 0000000..b5ae758
--- /dev/null
+++ b/src/mainboard/amd/olivehill/acpi_tables.c
@@ -0,0 +1,333 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include "agesawrapper.h"
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam16.h>
+
+#include "agesawrapper.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+
+static void dump_mem(u32 start, u32 end)
+{
+ u32 i;
+ print_debug("dump_mem:");
+ for (i = start; i < end; i++) {
+ if ((i & 0xf) == 0) {
+ printk(BIOS_DEBUG, "\n%08x:", i);
+ }
+ printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+ }
+ print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB800 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ /* TODO: Remove the hardcode */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
+ 0xFEC20000, 24);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edige-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
+
+unsigned long acpi_fill_hest(acpi_hest_t *hest)
+{
+ void *addr, *current;
+
+ /* Skip the HEST header. */
+ current = (void *)(hest + 1);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ return (unsigned long)current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ /* Not implemented */
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ int lens;
+ msr_t msr;
+ char pscope[] = "\\_SB.PCI0";
+
+ lens = acpigen_write_scope(pscope);
+ msr = rdmsr(TOP_MEM);
+ lens += acpigen_write_name_dword("TOM1", msr.lo);
+ msr = rdmsr(TOP_MEM2);
+ /*
+ * Since XP only implements parts of ACPI 2.0, we can't use a qword
+ * here.
+ * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+ * slide 22ff.
+ * Shift value right by 20 bit to make it fit into 32bit,
+ * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+ */
+ lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+ acpigen_patch_len(lens - 1);
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+ acpi_header_t *alib;
+ acpi_header_t *ivrs;
+ acpi_hest_t *hest;
+
+ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+ /* Align ACPI tables to 16 bytes */
+ start = ALIGN(start, 16);
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* DSDT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
+ dsdt = (acpi_header_t *)current; /* it will used by fadt */
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+ /* FACS */ /* it needs 64 bit alignment */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+ facs = (acpi_facs_t *) current; /* it will be used by fadt */
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* FADT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+ /* HEST */
+ current = ALIGN(current, 8);
+ hest = (acpi_hest_t *)current;
+ acpi_write_hest((void *)current);
+ acpi_add_table(rsdp, (void *)current);
+ current += ((acpi_header_t *)current)->length;
+
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
+ ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
+ if (ivrs != NULL) {
+ memcpy((void *)current, ivrs, ivrs->length);
+ ivrs = (acpi_header_t *) current;
+ current += ivrs->length;
+ acpi_add_table(rsdp, ivrs);
+ } else {
+ printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
+ }
+
+ /* SRAT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
+ srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+ if (srat != NULL) {
+ memcpy((void *)current, srat, srat->header.length);
+ srat = (acpi_srat_t *) current;
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
+ }
+
+ /* SLIT */
+ current = ALIGN(current, 8);
+ printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
+ slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+ if (slit != NULL) {
+ memcpy((void *)current, slit, slit->header.length);
+ slit = (acpi_slit_t *) current;
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
+ }
+
+ /* ALIB */
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
+ alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+ if (alib != NULL) {
+ memcpy((void *)current, alib, alib->length);
+ alib = (acpi_header_t *) current;
+ current += alib->length;
+ acpi_add_table(rsdp, (void *)alib);
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
+ }
+
+ /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */
+ /* SSDT */
+ current = ALIGN(current, 16);
+ printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
+ ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+ if (ssdt != NULL) {
+ memcpy((void *)current, ssdt, ssdt->length);
+ ssdt = (acpi_header_t *) current;
+ current += ssdt->length;
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
+ }
+ acpi_add_table(rsdp,ssdt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+
+#if DUMP_ACPI_TABLES == 1
+ printk(BIOS_DEBUG, "rsdp\n");
+ dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+ printk(BIOS_DEBUG, "rsdt\n");
+ dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+ printk(BIOS_DEBUG, "madt\n");
+ dump_mem(madt, ((void *)madt) + madt->header.length);
+
+ printk(BIOS_DEBUG, "srat\n");
+ dump_mem(srat, ((void *)srat) + srat->header.length);
+
+ printk(BIOS_DEBUG, "slit\n");
+ dump_mem(slit, ((void *)slit) + slit->header.length);
+
+ printk(BIOS_DEBUG, "ssdt\n");
+ dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+ printk(BIOS_DEBUG, "fadt\n");
+ dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+
+ printk(BIOS_DEBUG, "hest\n");
+ dump_mem(hest, ((void *)hest) + hest->header.length);
+#endif
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c
new file mode 100644
index 0000000..9618ff5
--- /dev/null
+++ b/src/mainboard/amd/olivehill/agesawrapper.c
@@ -0,0 +1,771 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "Fch.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cbmem.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+
+VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable = NULL;
+VOID *AcpiPstate = NULL;
+VOID *AcpiSrat = NULL;
+VOID *AcpiSlit = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+VOID *AcpiAlib = NULL;
+VOID *AcpiIvrs = NULL;
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+UINT32
+agesawrapper_amdinitcpuio (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /* Enable legacy video routing: D18F1xF4 VGA Enable */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+ PciData = 1;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+ * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+ * set to non-posted regions.
+ */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+ PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
+ PciData |= 1 << 7; /* set NP (non-posted) bit */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+ PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Map the remaining PCI hole as posted MMIO */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+ PciData = 0x00FECF00; /* last address before non-posted range */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ MsrReg = (MsrReg >> 8) | 3;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+ PciData = (UINT32)MsrReg;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Send all IO (0000-FFFF) to southbridge. */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+ PciData = 0x0000F000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+ PciData = 0x00000003;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitmmio (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+ Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+ LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | 0x0000400000000000;
+ LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+ /* For serial port */
+ PciData = 0xFF03FFD5;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+ LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitreset (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESET_PARAMS AmdResetParams;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ LibAmdMemFill (&AmdResetParams,
+ 0,
+ sizeof (AMD_RESET_PARAMS),
+ &(AmdResetParams.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+ AmdParamStruct.AllocationMethod = ByHost;
+ AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+ AmdParamStruct.NewStructPtr = &AmdResetParams;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+ AmdResetParams.HtConfig.Depth = 0;
+#if !CONFIG_HUDSON_XHCI_ENABLE
+ AmdResetParams.FchInterface.Xhci0Enable = FALSE;
+#endif
+ AmdResetParams.FchInterface.Xhci1Enable = FALSE;
+
+ status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+ return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitearly (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+
+ AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+ OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+ status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32 GetHeapBase(
+ AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 heap;
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* Both romstage and ramstage has this S3 detect. */
+ if (acpi_get_sleep_type() == 3)
+ heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */
+ else
+#endif
+ heap = BIOS_HEAP_START_ADDRESS; /* Low mem */
+
+ return heap;
+}
+
+UINT32
+agesawrapper_amdinitpost (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ UINT16 i;
+ UINT32 *HeadPtr;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_POST_PARAMS *PostParams;
+ BIOS_HEAP_MANAGER *BiosManagerPtr;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+ PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+ status = AmdInitPost (PostParams);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+ /* Initialize heap space */
+ BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader);
+
+ HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+ for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+ {
+ *HeadPtr = 0x00000000;
+ HeadPtr++;
+ }
+ BiosManagerPtr->StartOfAllocatedNodes = 0;
+ BiosManagerPtr->StartOfFreedNodes = 0;
+
+ return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitenv (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_ENV_PARAMS *EnvParam;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ status = AmdCreateStruct (&AmdParamStruct);
+ EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
+
+ status = AmdInitEnv (EnvParam);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus);
+ /* Initialize Subordinate Bus Number and Secondary Bus Number
+ * In platform BIOS this address is allocated by PCI enumeration code
+ Modify D1F0x18
+ */
+
+ return (UINT32)status;
+}
+
+VOID *
+agesawrapper_getlateinitptr (
+ int pick
+ )
+{
+ switch (pick) {
+ case PICK_DMI:
+ return DmiTable;
+ case PICK_PSTATE:
+ return AcpiPstate;
+ case PICK_SRAT:
+ return AcpiSrat;
+ case PICK_SLIT:
+ return AcpiSlit;
+ case PICK_WHEA_MCE:
+ return AcpiWheaMce;
+ case PICK_WHEA_CMC:
+ return AcpiWheaCmc;
+ case PICK_ALIB:
+ return AcpiAlib;
+ case PICK_IVRS:
+ return AcpiIvrs;
+ default:
+ return NULL;
+ }
+}
+
+UINT32
+agesawrapper_amdinitmid (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ /* Enable MMIO on AMD CPU Address Map Controller */
+ agesawrapper_amdinitcpuio ();
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+
+ ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitlate (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_LATE_PARAMS *AmdLateParams;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
+ AmdCreateStruct(&AmdParamStruct);
+ AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+ Status = AmdInitLate(AmdLateParams);
+ /* CDIT table is not created. */
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ DmiTable = AmdLateParams->DmiTable;
+ AcpiPstate = AmdLateParams->AcpiPState;
+ AcpiSrat = AmdLateParams->AcpiSrat;
+ AcpiSlit = AmdLateParams->AcpiSlit;
+
+ AcpiWheaMce = AmdLateParams->AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
+ AcpiAlib = AmdLateParams->AcpiAlib;
+ AcpiIvrs = AmdLateParams->AcpiIvrs;
+
+ printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
+ "AcpiSlit:%x, Mce:%x, Cmc:%x,"
+ "Alib:%x, AcpiIvrs:%x in %s\n",
+ (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,
+ (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
+ (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
+
+ /* AmdReleaseStruct (&AmdParamStruct); */
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdlaterunaptask (
+ UINT32 Func,
+ UINT32 Data,
+ VOID *ConfigPtr
+ )
+{
+ AGESA_STATUS Status;
+ AP_EXE_PARAMS ApExeParams;
+
+ LibAmdMemFill (&ApExeParams,
+ 0,
+ sizeof (AP_EXE_PARAMS),
+ &(ApExeParams.StdHeader));
+
+ ApExeParams.StdHeader.AltImageBasePtr = 0;
+ ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ ApExeParams.StdHeader.Func = 0;
+ ApExeParams.StdHeader.ImageBasePtr = 0;
+ ApExeParams.FunctionNumber = Func;
+ ApExeParams.RelatedDataBlock = ConfigPtr;
+
+ Status = AmdLateRunApTask (&ApExeParams);
+ if (Status != AGESA_SUCCESS) {
+ /* agesawrapper_amdreadeventlog(); */
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ return (UINT32)Status;
+}
+
+#if CONFIG_HAVE_ACPI_RESUME
+
+UINT32 agesawrapper_amdinitresume(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESUME_PARAMS *AmdResumeParamsPtr;
+ S3_DATA_TYPE S3DataType;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+
+ AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
+
+ AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
+ AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
+ S3DataType = S3DataTypeNonVolatile;
+ OemAgesaGetS3Info (S3DataType,
+ (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
+ (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
+
+ status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
+
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+#ifndef __PRE_RAM__
+
+extern FCH_DATA_BLOCK InitEnvCfgDefault;
+STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
+{
+ FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
+ FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
+ FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
+ FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
+ FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
+ FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
+ FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
+ FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
+ FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
+ FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */
+ FchParams->Gpp.GppPhyPllPowerDown = TRUE;
+ FchParams->Gpp.GppDynamicPowerSaving = TRUE;
+ FchParams->Gpp.UmiPhyPllPowerDown = TRUE;
+ FchParams->Gpp.NewGppAlgorithm = TRUE;
+ FchParams->Gpp.GppPortMinPollingTime = 40;
+
+ FchParams->Spi.SpiSpeed = 2;
+ FchParams->Ir.IrConfig = 3;
+
+ FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
+ FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
+ FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
+ FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
+ FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
+ FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
+ FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
+ FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
+ FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
+ FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
+ FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
+ FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
+ FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
+ FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
+ FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
+ FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
+ FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
+ FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
+ FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
+ FchParams->F1.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
+ FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
+ FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
+ FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
+ FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
+ FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
+ FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
+ FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
+}
+
+UINT32 agesawrapper_fchs3earlyrestore (VOID)
+{
+ AGESA_STATUS status = AGESA_SUCCESS;
+
+ FCH_DATA_BLOCK FchParams;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
+ StdHeader.AltImageBasePtr = 0;
+ StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ StdHeader.Func = 0;
+ StdHeader.ImageBasePtr = 0;
+
+ FchParams = InitEnvCfgDefault;
+ FchParams.StdHeader = &StdHeader;
+ s3_resume_init_data(&FchParams);
+
+ FchInitS3EarlyRestore(&FchParams);
+
+ return status;
+}
+#endif
+
+UINT32 agesawrapper_amds3laterestore (VOID)
+{
+ AGESA_STATUS Status;
+ AMD_INTERFACE_PARAMS AmdInterfaceParams;
+ AMD_S3LATE_PARAMS AmdS3LateParams;
+ AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
+ S3_DATA_TYPE S3DataType;
+
+ agesawrapper_amdinitcpuio();
+ LibAmdMemFill (&AmdS3LateParams,
+ 0,
+ sizeof (AMD_S3LATE_PARAMS),
+ &(AmdS3LateParams.StdHeader));
+ AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
+ AmdInterfaceParams.AllocationMethod = ByHost;
+ AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
+ AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
+ AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdS3LateParamsPtr = &AmdS3LateParams;
+ AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
+
+ AmdCreateStruct (&AmdInterfaceParams);
+
+ AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
+ S3DataType = S3DataTypeVolatile;
+
+ OemAgesaGetS3Info (S3DataType,
+ (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
+ (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
+
+ Status = AmdS3LateRestore (AmdS3LateParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ return (UINT32)Status;
+}
+
+#ifndef __PRE_RAM__
+
+extern UINT8 picr_data[0x54], intr_data[0x54];
+
+UINT32 agesawrapper_fchs3laterestore (VOID)
+{
+ AGESA_STATUS status = AGESA_SUCCESS;
+
+ FCH_DATA_BLOCK FchParams;
+ AMD_CONFIG_PARAMS StdHeader;
+ UINT8 byte;
+
+ StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
+ StdHeader.AltImageBasePtr = 0;
+ StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ StdHeader.Func = 0;
+ StdHeader.ImageBasePtr = 0;
+
+ FchParams = InitEnvCfgDefault;
+ FchParams.StdHeader = &StdHeader;
+ s3_resume_init_data(&FchParams);
+ FchInitS3LateRestore(&FchParams);
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ return status;
+}
+#endif
+
+#ifndef __PRE_RAM__
+
+UINT32 agesawrapper_amdS3Save(VOID)
+{
+ AGESA_STATUS Status;
+ AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
+ AMD_INTERFACE_PARAMS AmdInterfaceParams;
+ S3_DATA_TYPE S3DataType;
+
+ LibAmdMemFill (&AmdInterfaceParams,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdInterfaceParams.StdHeader));
+
+ AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
+ AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdInterfaceParams.AllocationMethod = PostMemDram;
+ AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
+ AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
+ AmdInterfaceParams.StdHeader.Func = 0;
+
+ AmdCreateStruct(&AmdInterfaceParams);
+ AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
+ AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
+
+ Status = AmdS3Save(AmdS3SaveParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ S3DataType = S3DataTypeNonVolatile;
+ printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
+
+ Status = OemAgesaSaveS3Info (
+ S3DataType,
+ AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
+ AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
+
+ printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
+
+ if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
+ S3DataType = S3DataTypeVolatile;
+
+ Status = OemAgesaSaveS3Info (
+ S3DataType,
+ AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
+ AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
+ }
+ OemAgesaSaveMtrr();
+
+ AmdReleaseStruct (&AmdInterfaceParams);
+
+ return (UINT32)Status;
+}
+
+#endif /* #ifndef __PRE_RAM__ */
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+
+UINT32
+agesawrapper_amdreadeventlog (
+ UINT8 HeapStatus
+ )
+{
+ AGESA_STATUS Status;
+ EVENT_PARAMS AmdEventParams;
+
+ LibAmdMemFill (&AmdEventParams,
+ 0,
+ sizeof (EVENT_PARAMS),
+ &(AmdEventParams.StdHeader));
+
+ AmdEventParams.StdHeader.AltImageBasePtr = 0;
+ AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdEventParams.StdHeader.Func = 0;
+ AmdEventParams.StdHeader.ImageBasePtr = 0;
+ AmdEventParams.StdHeader.HeapStatus = HeapStatus;
+ Status = AmdReadEventLog (&AmdEventParams);
+ while (AmdEventParams.EventClass != 0) {
+ printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
+ Status = AmdReadEventLog (&AmdEventParams);
+ }
+
+ return (UINT32)Status;
+}
diff --git a/src/mainboard/amd/olivehill/agesawrapper.h b/src/mainboard/amd/olivehill/agesawrapper.h
new file mode 100644
index 0000000..db893cd
--- /dev/null
+++ b/src/mainboard/amd/olivehill/agesawrapper.h
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/* Define AMD Ontario APPU SSID/SVID */
+#define AMD_APU_SVID 0x1022
+#define AMD_APU_SSID 0x1234
+#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+
+enum {
+ PICK_DMI, /* DMI Interface */
+ PICK_PSTATE, /* Acpi Pstate SSDT Table */
+ PICK_SRAT, /* SRAT Table */
+ PICK_SLIT, /* SLIT Table */
+ PICK_WHEA_MCE, /* WHEA MCE table */
+ PICK_WHEA_CMC, /* WHEA CMV table */
+ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+ PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */
+};
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+ UINT32 CalloutName;
+ AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+UINT32 agesawrapper_amdinitreset (void);
+UINT32 agesawrapper_amdinitearly (void);
+UINT32 agesawrapper_amdinitenv (void);
+UINT32 agesawrapper_amdinitlate (void);
+UINT32 agesawrapper_amdinitpost (void);
+UINT32 agesawrapper_amdinitmid (void);
+UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus);
+UINT32 agesawrapper_amdinitmmio (void);
+UINT32 agesawrapper_amdinitcpuio (void);
+void *agesawrapper_getlateinitptr (int pick);
+UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr);
+UINT32 agesawrapper_amdS3Save(VOID);
+UINT32 agesawrapper_amdinitresume(VOID);
+UINT32 agesawrapper_amds3laterestore (VOID);
+
+UINT32 agesawrapper_fchs3earlyrestore (VOID);
+UINT32 agesawrapper_fchs3laterestore (VOID);
+
+UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader);
+
+#endif
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c
new file mode 100644
index 0000000..df5e35a
--- /dev/null
+++ b/src/mainboard/amd/olivehill/buildOpts.c
@@ -0,0 +1,507 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
+ */
+
+#include "AGESA.h"
+//#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+#define INSTALL_FT3_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
+
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+#define INSTALL_FM2_SOCKET_SUPPORT FALSE
+
+
+#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
+ #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
+ #undef INSTALL_FT3_SOCKET_SUPPORT
+ #define INSTALL_FT3_SOCKET_SUPPORT FALSE
+ #endif
+#endif
+
+#define BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING TRUE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+//#define BLDOPT_REMOVE_DMI FALSE //TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 15000
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000
+#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
+#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000
+#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_SLEW_RATE 10000
+#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
+ // core for C-state entry requests. A value
+ // of 0 in this field specifies that the core
+ // does not trap any IO addresses for C-state entry.
+ // Values greater than 0xFFF8 results in undefined behavior.
+#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYNC_FLOOD TRUE
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
+#define BLDCFG_IOMMU_SUPPORT FALSE
+#define OPTION_GFX_INIT_SVIEW FALSE
+//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
+
+//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
+#define BLDCFG_CFG_ABM_SUPPORT TRUE
+
+
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+#ifdef PCIEX_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
+#endif
+
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+#define AGESA_ENTRY_INIT_RESET TRUE
+#define AGESA_ENTRY_INIT_RECOVERY FALSE
+#define AGESA_ENTRY_INIT_EARLY TRUE
+#define AGESA_ENTRY_INIT_POST TRUE
+#define AGESA_ENTRY_INIT_ENV TRUE
+#define AGESA_ENTRY_INIT_MID TRUE
+#define AGESA_ENTRY_INIT_LATE TRUE
+#define AGESA_ENTRY_INIT_S3SAVE TRUE
+#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
+
+#include "KeralaInstall.h"
+
+/* Include the files that instantiate the configuration definitions. */
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+//#define DDR400_FREQUENCY 200 ///< DDR 400
+//#define DDR533_FREQUENCY 266 ///< DDR 533
+//#define DDR667_FREQUENCY 333 ///< DDR 667
+//#define DDR800_FREQUENCY 400 ///< DDR 800
+//#define DDR1066_FREQUENCY 533 ///< DDR 1066
+//#define DDR1333_FREQUENCY 667 ///< DDR 1333
+//#define DDR1600_FREQUENCY 800 ///< DDR 1600
+//#define DDR1866_FREQUENCY 933 ///< DDR 1866
+//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+//
+///* QUANDRANK_TYPE*/
+//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+//
+///* USER_MEMORY_TIMING_MODE */
+//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+//
+///* POWER_DOWN_MODE */
+//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+
+GPIO_CONTROL olivehill_gpio[] = {
+ {183, Function1, GpioIn | GpioOutEnB | PullUpB},
+ {-1}
+};
+//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+#include "PlatformInstall.h"
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ //
+ // The following macros are supported (use comma to separate macros):
+ //
+ // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+ // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+ // AGESA will base on this value to disable unused MemClk to save power.
+ // Example:
+ // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+ // Bit AM3/S1g3 pin name
+ // 0 M[B,A]_CLK_H/L[0]
+ // 1 M[B,A]_CLK_H/L[1]
+ // 2 M[B,A]_CLK_H/L[2]
+ // 3 M[B,A]_CLK_H/L[3]
+ // 4 M[B,A]_CLK_H/L[4]
+ // 5 M[B,A]_CLK_H/L[5]
+ // 6 M[B,A]_CLK_H/L[6]
+ // 7 M[B,A]_CLK_H/L[7]
+ // And platform has the following routing:
+ // CS0 M[B,A]_CLK_H/L[4]
+ // CS1 M[B,A]_CLK_H/L[2]
+ // CS2 M[B,A]_CLK_H/L[3]
+ // CS3 M[B,A]_CLK_H/L[5]
+ // Then platform can specify the following macro:
+ // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+ //
+ // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+ // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+ // AGESA will base on this value to tristate unused CKE to save power.
+ //
+ // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+ // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+ // AGESA will base on this value to tristate unused ODT pins to save power.
+ //
+ // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+ // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+ // AGESA will base on this value to tristate unused Chip select to save power.
+ //
+ // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+ // Specifies the number of DIMM slots per channel.
+ //
+ // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+ // Specifies the number of Chip selects per channel.
+ //
+ // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+ // Specifies the number of channels per socket.
+ //
+ // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+ // Specifies DDR bus speed of channel ChannelID on socket SocketID.
+ //
+ // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+ // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+ //
+ // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ // Byte6Seed, Byte7Seed, ByteEccSeed)
+ // Specifies the write leveling seed for a channel of a socket.
+ //
+ // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ // Byte6Seed, Byte7Seed, ByteEccSeed)
+ // Speicifes the HW RXEN training seed for a channel of a socket
+ //
+ #define SEED_A 0x12
+ HW_RXEN_SEED(
+ ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+ SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+ SEED_A),
+
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+ MOTHER_BOARD_LAYERS (LAYERS_4),
+
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+#include "mm.h"
+#include "mn.h"
+
+// Customer table
+UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ // Hardcoded Memory Training Values
+
+ // The following macro should be used to override training values for your platform
+ //
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+ //
+ // NOTE:
+ // The following training hardcode values are example values that were taken from a tilapia motherboard
+ // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
+ // the table and replace the byte lane values with your own.
+ //
+ // ------------------ BYTE LANES ----------------------
+ // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
+ // Write Data Timing
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+ // DQS Receiver Enable
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+ // Write DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+ // Read DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+ //--------------------------------------------------------------------------------------------------------------------------------------------------
+ // TABLE END
+ NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
+};
+UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);
diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout
new file mode 100644
index 0000000..f6b5806
--- /dev/null
+++ b/src/mainboard/amd/olivehill/cmos.layout
@@ -0,0 +1,114 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb
new file mode 100644
index 0000000..dc489d3
--- /dev/null
+++ b/src/mainboard/amd/olivehill/devicetree.cb
@@ -0,0 +1,76 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+chip northbridge/amd/agesa/family16kb/root_complex
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family16kb
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
+ chip northbridge/amd/agesa/family16kb # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 on end # PCIe Host Bridge
+ device pci 2.1 on end # x4 PCIe slot
+ device pci 2.2 on end # mPCIe slot
+ device pci 2.3 on end # Realtek NIC
+ device pci 2.4 on end # Edge Connector
+ device pci 2.5 on end # Edge Connector
+ end #chip northbridge/amd/agesa/family16kb
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SM
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ end # SM
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on end # LPC 0x439d
+ device pci 14.7 on end # SD
+ end #chip southbridge/amd/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
+ end #domain
+end #northbridge/amd/agesa/family16kb/root_complex
\ No newline at end of file
diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl
new file mode 100644
index 0000000..2ab0a8c
--- /dev/null
+++ b/src/mainboard/amd/olivehill/dsdt.asl
@@ -0,0 +1,1448 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /*
+ * Processor Object
+ *
+ */
+ Scope (\_PR) { /* define processor scope */
+ Processor(
+ P000, /* name space name */
+ 0, /* Unique number for this processor */
+ 0x810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+
+ Processor(
+ P001, /* name space name */
+ 1, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P002, /* name space name */
+ 2, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P003, /* name space name */
+ 3, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P004, /* name space name */
+ 4, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P005, /* name space name */
+ 5, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P006, /* name space name */
+ 6, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P007, /* name space name */
+ 7, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ } /* End _PR scope */
+
+ /* PIC IRQ mapping registers, C00h-C01h. */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PIRA, 0x00000008, /* Index 0 */
+ PIRB, 0x00000008, /* Index 1 */
+ PIRC, 0x00000008, /* Index 2 */
+ PIRD, 0x00000008, /* Index 3 */
+ PIRE, 0x00000008, /* Index 4 */
+ PIRF, 0x00000008, /* Index 5 */
+ PIRG, 0x00000008, /* Index 6 */
+ PIRH, 0x00000008, /* Index 7 */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0xEE),
+ UPWS, 3,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ Scope(\_SB) {
+ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve){
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+
+ Method(CkOT, 0){
+
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+ Method(CIRQ, 0x00, NotSerialized){
+ //Store(0, PIRA)
+ //Store(0, PIRB)
+ //Store(0, PIRC)
+ //Store(0, PIRD)
+ //Store(0, PIRE)
+ //Store(0, PIRF)
+ //Store(0, PIRG)
+ //Store(0, PIRH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PIRA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ //Store(0x1F, PIRA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ //Store(Local0, PIRA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PIRB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ //Store(0, PIRB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PIRC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ //Store(0, PIRC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIRD) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ //Store(0, PIRD)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRD, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRD)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PIRE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ //Store(0, PIRE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PIRF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ //Store(0, PIRF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PIRG) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ //Store(0, PIRG)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRG, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRG)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PIRH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ //Store(0, PIRH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ //Store(Local0, PIRH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ //if (LEqual(Arg0,3)){
+ // Store(0,URRE)
+ //}
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ Store(7, UPWS)
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ //Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ //if (LEqual(Arg0,3)){
+ // Store(1,URRE)
+ //}
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ //Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\\_GPE\\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\\_GPE\\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\\_GPE\\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\\_GPE\\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\\_GPE\\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\\_GPE\\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\\_GPE\\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\\_GPE\\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\\_GPE\\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\\_GPE\\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\\_GPE\\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\\_GPE\\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\\_GPE\\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event - Moved to USB.asl */
+ /* Method(_L1A) {
+ * DBGO("\\_GPE\\_L1A\n")
+ * }
+ */
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\\_GPE\\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\\_GPE\\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\\_GPE\\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\\_GPE\\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ //#include "acpi/usb.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices Dev0 ,Func0*/
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+#if 1
+ /* Dev3 is also an external GFX bridge */
+ Device(PBR3) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS3) } /* APIC mode */
+ Return (PS3) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR3 */
+#endif
+
+ Device(PBR4) {
+ Name(_ADR, 0x00020001)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBR5) {
+ Name(_ADR, 0x00020002)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR5 */
+
+ Device(PBR6) {
+ Name(_ADR, 0x00020003)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR6 */
+
+ /* The onboard EtherNet chip */
+ Device(PBR7) {
+ Name(_ADR, 0x00020004)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR7 */
+
+ /* PCI slot 1, 2, 3 */
+ Device(PIBR) {
+ Name(_ADR, 0x00140004)
+ Name(_PRW, Package() {0x18, 4})
+
+ Method(_PRT, 0) {
+ Return (PCIB)
+ }
+ }
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00110000)
+ //#include "acpi/sata.asl"
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00120000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00120002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00160000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UOH6) {
+ Name(_ADR, 0x00160002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00140005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(XHC0) {
+ Name(_ADR, 0x00100000)
+ Name(_PRW, Package() {0x0B, 4})
+ } /* end XHC0 */
+ Device(XHC1) {
+ Name(_ADR, 0x00100001)
+ Name(_PRW, Package() {0x0B, 4})
+ } /* end XHC1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ //#include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
+ Field(CFG,DWordAcc,NoLock,Preserve){
+ Offset(0xA0),
+ BAR,32} // SPI Controller Base Address Register (Index 0xA0)
+
+ Device(LDRC) // LPC device: Resource consumption
+ {
+ Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
+ Name (CRS, ResourceTemplate () // Current Motherboard resources
+ {
+ Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
+ 0x00000000, // Address Base
+ 0x00000000, // Address Length
+ BAR0 // Descriptor Name
+ )
+ })
+
+ Method(_CRS,0,NotSerialized)
+ {
+ CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
+ CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
+ Store(BAR,SPIB) // SPI base address mapped
+ Store(0x1000,SPIL) // 4k space mapped
+ Return(CRS)
+ }
+ }
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ Name(CRES, ResourceTemplate() {
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0CF7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0CF8 /* length */
+ )
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x03B0, /* range minimum */
+ 0x03DF, /* range maximum */
+ 0x0000, /* translation */
+ 0x0030 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0D00, /* range minimum */
+ 0xFFFF, /* range maximum */
+ 0x0000, /* translation */
+ 0xF300 /* length */
+ )
+
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+ /* memory space for PCI BARs below 4GB */
+ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+ CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+ CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+ /*
+ * Declare memory between TOM1 and 4GB as available
+ * for PCI MMIO.
+ * Use ShiftLeft to avoid 64bit constant (for XP).
+ * This will work even if the OS does 32bit arithmetic, as
+ * 32bit (0x00000000 - TOM1) will wrap and give the same
+ * result as 64bit (0x100000000 - TOM1).
+ */
+ Store(TOM1, MM1B)
+ ShiftLeft(0x10000000, 4, Local0)
+ Subtract(Local0, TOM1, Local0)
+ Store(Local0, MM1L)
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ * }
+ */
+ /* TODO: It is unstable. */
+ //#include "acpi/AmdImc.asl" /* Hudson IMC function */
+ //ITZE() /* enable IMC Fan Control*/
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End \_SB scope */
+
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+}
+/* End of ASL file */
diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c
new file mode 100644
index 0000000..fca2625
--- /dev/null
+++ b/src/mainboard/amd/olivehill/get_bus_conf.c
@@ -0,0 +1,143 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/amd/amdfam14.h>
+#include "agesawrapper.h"
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+ * and acpi_tables busnum is default.
+ */
+u8 bus_isa;
+u8 bus_sb800[3];
+u32 apicid_sb800;
+
+/*
+ * Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ * You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
+u32 pci1234x[] = {
+ 0x0000ff0,
+};
+
+u32 bus_type[256];
+u32 sbdn_sb800;
+
+static u32 get_bus_conf_done = 0;
+
+#if CONFIG_HAVE_ACPI_RESUME
+extern u8 acpi_slp_type;
+#endif
+void get_bus_conf(void)
+{
+ u32 apicid_base;
+ u32 status;
+
+ device_t dev;
+ int i, j;
+
+ if (get_bus_conf_done == 1)
+ return; /* do it only once */
+
+ get_bus_conf_done = 1;
+
+ /*
+ * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
+ * but functionally within the coreboot model, this is the best place to make the
+ * call. The logically correct place to call AmdInitLate is after PCI scan is done,
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM. The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain". There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions. The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
+ * called before the ACPI tables are written. This routine is called at the beginning
+ * of each of the write functions called prior to the ACPI write functions, so this
+ * becomes the best place for this call.
+ */
+#if CONFIG_HAVE_ACPI_RESUME
+ if (acpi_slp_type != 3) {
+ status = agesawrapper_amdinitlate();
+ if(status) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+ }
+ status = agesawrapper_amdS3Save();
+ if (status) {
+ printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status);
+ }
+ }
+#else
+ status = agesawrapper_amdinitlate();
+ if (status)
+ printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+#endif
+ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
+ pci_write_config32(dev, 0xF8, 0);
+ pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
+
+ sbdn_sb800 = 0;
+
+ for (i = 0; i < 3; i++) {
+ bus_sb800[i] = 0;
+ }
+
+ for (i = 0; i < 256; i++) {
+ bus_type[i] = 0; /* default ISA bus. */
+ }
+
+ bus_type[0] = 1; /* pci */
+
+ // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
+
+ /* sb800 */
+ dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+
+ if (dev) {
+ bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ for (j = bus_sb800[1]; j < bus_isa; j++)
+ bus_type[j] = 1;
+ }
+
+ for (i = 0; i < 4; i++) {
+ dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
+ if (dev) {
+ bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ }
+ }
+ for (j = bus_sb800[2]; j < bus_isa; j++)
+ bus_type[j] = 1;
+
+ /* I/O APICs: APIC ID Version State Address */
+ bus_isa = 10;
+ apicid_base = CONFIG_MAX_CPUS;
+ apicid_sb800 = apicid_base;
+}
diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c
new file mode 100644
index 0000000..3bcd3fb
--- /dev/null
+++ b/src/mainboard/amd/olivehill/irq_tables.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam15.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+extern u8 bus_isa;
+extern u8 bus_sb800[2];
+extern unsigned long sbdn_sb800;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be betweeen 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = bus_sb800[0];
+ pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c
new file mode 100644
index 0000000..0a3f9a5
--- /dev/null
+++ b/src/mainboard/amd/olivehill/mainboard.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <arch/acpi.h>
+#include "BiosCallOuts.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include "agesawrapper.h"
+
+/**********************************************
+ * enable the dedicated function in mainboard.
+ **********************************************/
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ /*
+ * The mainboard is the first place that we get control in ramstage. Check
+ * for S3 resume and call the approriate AGESA/CIMx resume functions.
+ */
+#if CONFIG_HAVE_ACPI_RESUME
+ acpi_slp_type = acpi_get_sleep_type();
+ if (acpi_slp_type == 3)
+ agesawrapper_fchs3earlyrestore();
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c
new file mode 100644
index 0000000..7db7160
--- /dev/null
+++ b/src/mainboard/amd/olivehill/mptable.c
@@ -0,0 +1,245 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdfam15.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
+
+//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
+#define IO_APIC_ID CONFIG_MAX_CPUS
+extern u8 bus_sb800[3];
+
+extern u32 bus_type[256];
+extern u32 sbdn_sb800;
+extern u32 apicid_sb800;
+
+u8 picr_data[0x54] = {
+ 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x03,0x04,0x05,0x07
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u32 dword;
+ u8 byte;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ get_bus_conf();
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+
+ dword = 0;
+ dword = pm_ioread(0x34) & 0xF0;
+ dword |= (pm_ioread(0x35) & 0xFF) << 8;
+ dword |= (pm_ioread(0x36) & 0xFF) << 16;
+ dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ /* Set IO APIC ID onto IO_APIC_ID */
+ write32 (dword, 0x00);
+ write32 (dword + 0x10, IO_APIC_ID << 24);
+ apicid_sb800 = IO_APIC_ID;
+ smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
+
+ smp_write_ioapic(mc, apicid_sb800+1, 0x21, 0xFEC20000);
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+#if 0
+ outb(0x0B, 0xCD6);
+ outb(0x02, 0xCD7);
+
+ outb(0x50, 0xCD6);
+ outb(0x1F, 0xCD7);
+
+ outb(0x48, 0xCD6);
+ outb(0xF2, 0xCD7);
+
+ //outb(0xBE, 0xCD6);
+ //outb(0x52, 0xCD7);
+
+ outb(0xED, 0xCD6);
+ outb(0x17, 0xCD7);
+
+ *(volatile u8 *) (0xFED80D00 + 0x31) = 2;
+ *(volatile u8 *) (0xFED80D00 + 0x32) = 2;
+ *(volatile u8 *) (0xFED80D00 + 0x33) = 2;
+ *(volatile u8 *) (0xFED80D00 + 0x34) = 2;
+
+ *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8;
+ *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8;
+ *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8;
+ *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0;
+
+ *(volatile u8 *) (0xFED80D00 + 0x6c) = 1;
+ *(volatile u8 *) (0xFED80D00 + 0x6E) = 2;
+ *(volatile u8 *) (0xFED80D00 + 0x6f) = 2;
+
+ *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0;
+ *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8;
+ *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0;
+
+ *(volatile u8 *) (0xFED80D00 + 0xA6) = 2;
+ *(volatile u8 *) (0xFED80100 + 0xA6) = 0;
+
+ *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8;
+#endif
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+ PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+ PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+ PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+ PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+ PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+ PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+ PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+ PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+ PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+ PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
+ PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
+ PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
new file mode 100644
index 0000000..e74c7f2
--- /dev/null
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -0,0 +1,192 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "agesawrapper.h"
+#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "southbridge/amd/agesa/hudson/hudson.h"
+#include "cpu/amd/agesa/s3_resume.h"
+#include "src/drivers/pc80/i8254.c"
+#include "src/drivers/pc80/i8259.c"
+#include "cbmem.h"
+//#include "superio/ite/it8712f/early_serial.c"
+#define _SIMNOW_ 0
+
+#if _SIMNOW_
+#include "superio/smsc/kbc1100/kbc1100_early_init.c"
+#endif
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
+void disable_cache_as_ram(void);
+
+/* TODO: Larne has some setting which is not clear about the root cause */
+#define _LARNE_ 1
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+#if CONFIG_HAVE_ACPI_RESUME
+ void *resume_backup_memory;
+#endif
+ /* This is not defined in Kabini BKDG. In Hudson RRG,
+ PMIOxD2[5:4] is "Drive strength control for LpcClk[1:0]".
+ It needs to be set as 4mA. Otherwise the serial output is
+ bad code.
+ */
+ #if _LARNE_
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+ #endif
+
+ val = agesawrapper_amdinitmmio();
+
+ hudson_lpc_port80();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+
+ post_code(0x31);
+ #if _SIMNOW_
+ kbc1100_early_init(0x2e);
+ #endif
+
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ #if _LARNE_ && ! _SIMNOW_
+ /* TODO: Just Guess.
+ On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */
+ int i;
+ for(i = 0; i < 200000; i++)
+ val = inb(0xcd6);
+ #endif
+
+ post_code(0x37);
+ val = agesawrapper_amdinitreset();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+ }
+
+ post_code(0x38);
+ printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+
+ post_code(0x39);
+
+ val = agesawrapper_amdinitearly ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+#if CONFIG_HAVE_ACPI_RESUME
+ if (!acpi_is_wakeup_early()) { /* Check for S3 resume */
+#endif
+ post_code(0x40);
+ val = agesawrapper_amdinitpost ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+ post_code(0x41);
+ val = agesawrapper_amdinitenv ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+ /* TODO: Disable cache is not ok. */
+ disable_cache_as_ram();
+#if CONFIG_HAVE_ACPI_RESUME
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ printk(BIOS_DEBUG, "agesawrapper_amdinitresume ");
+ val = agesawrapper_amdinitresume();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n");
+
+ printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
+ val = agesawrapper_amds3laterestore ();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n");
+
+ post_code(0x61);
+ printk(BIOS_DEBUG, "Find resume memory location\n");
+ resume_backup_memory = (void *)backup_resume();
+
+ post_code(0x62);
+ printk(BIOS_DEBUG, "Move CAR stack.\n");
+ move_stack_high_mem();
+ printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
+
+ post_code(0x63);
+ disable_cache_as_ram();
+ printk(BIOS_DEBUG, "CAR disabled.\n");
+ set_resume_cache();
+
+ /*
+ * Copy the system memory that is in the ramstage area to the
+ * reserved area.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
+
+ printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ }
+#endif
+
+ outb(0xEA, 0xCD6);
+ outb(0x1, 0xcd7);
+ /* Initialize i8259 pic */
+ post_code(0x41);
+ setup_i8259 ();
+
+ /* Initialize i8254 timers */
+ post_code(0x42);
+ setup_i8254 ();
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}
1
0
New patch to review for coreboot: 3648769 intel/i5000: remove explicit pcie config accesses
by Kyösti Mälkki 26 Jul '13
by Kyösti Mälkki 26 Jul '13
26 Jul '13
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3813
-gerrit
commit 36487694d95bcdf001d0c5768e45acc3e2ee08cc
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Jul 26 08:53:25 2013 +0300
intel/i5000: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: Ibe2fea68854af465900e443959a745a7167fb753
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/northbridge/intel/i5000/raminit.c | 318 +++++++++++++++++-----------------
1 file changed, 159 insertions(+), 159 deletions(-)
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index 48499da..7055c7a 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -121,26 +121,26 @@ static void i5000_clear_fbd_errors(void)
dev16_1 = PCI_ADDR(0, 16, 1, 0);
dev16_2 = PCI_ADDR(0, 16, 2, 0);
- pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD,
- pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD));
+ pci_write_config32(dev16_1, I5000_EMASK_FBD,
+ pci_read_config32(dev16_1, I5000_EMASK_FBD));
- pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD,
- pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD));
+ pci_write_config32(dev16_1, I5000_NERR_FAT_FBD,
+ pci_read_config32(dev16_1, I5000_NERR_FAT_FBD));
- pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD,
- pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD));
+ pci_write_config32(dev16_1, I5000_FERR_FAT_FBD,
+ pci_read_config32(dev16_1, I5000_FERR_FAT_FBD));
- pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD,
- pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD));
+ pci_write_config32(dev16_1, I5000_NERR_NF_FBD,
+ pci_read_config32(dev16_1, I5000_NERR_NF_FBD));
- pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD,
- pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD));
+ pci_write_config32(dev16_1, I5000_FERR_NF_FBD,
+ pci_read_config32(dev16_1, I5000_FERR_NF_FBD));
- pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL,
- pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL));
+ pci_write_config32(dev16_2, I5000_FERR_GLOBAL,
+ pci_read_config32(dev16_2, I5000_FERR_GLOBAL));
- pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL,
- pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL));
+ pci_write_config32(dev16_2, I5000_NERR_GLOBAL,
+ pci_read_config32(dev16_2, I5000_NERR_GLOBAL));
}
static int i5000_branch_reset(struct i5000_fbd_branch *b)
@@ -654,7 +654,7 @@ static int i5000_amb_preinit(struct i5000_fbdimm *d)
d->device = id >> 16;
}
- pci_mmio_write_config8(d->branch->branchdev,
+ pci_write_config8(d->branch->branchdev,
d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
return 0;
}
@@ -666,11 +666,11 @@ static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
printk(BIOS_DEBUG, " FBD state branch %d: %02x,", b->num, state);
- pci_mmio_write_config8(dev, I5000_FBDHPC, state);
+ pci_write_config8(dev, I5000_FBDHPC, state);
printk(BIOS_DEBUG, "waiting for new state...");
- while(pci_mmio_read_config8(dev, I5000_FBDST) != state && timeout--)
+ while(pci_read_config8(dev, I5000_FBDST) != state && timeout--)
udelay(10);
if (timeout) {
@@ -689,12 +689,12 @@ static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
printk(BIOS_DEBUG, " waiting for pattern recognition...");
- while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0)
+ while(pci_read_config16(dev, 0) != 0x1fff && --i > 0)
udelay(5000);
printk(BIOS_DEBUG, i ? "done\n" : "failed\n");
printk(BIOS_DEBUG, "%d/%d Round trip latency: %d\n", c->branch->num, c->num,
- pci_mmio_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
+ pci_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
return !i;
}
@@ -713,7 +713,7 @@ static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wai
printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n",
c->branch->num, c->num,
pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
- pci_mmio_write_config8(dev, 0, pattern);
+ pci_write_config8(dev, 0, pattern);
if (!wait)
return 0;
@@ -749,14 +749,14 @@ static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_am
u32 portctl;
int i, cnt = 1000;
- portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
+ portctl = pci_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
portctl &= ~0x01000020;
if (mchpad)
portctl |= 0x00800000;
else
portctl &= ~0x00800000;
portctl &= ~0x01000020;
- pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
+ pci_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
/* drive calibration patterns */
if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
@@ -765,7 +765,7 @@ static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_am
if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
return -1;
- while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
+ while (!(pci_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
udelay(10);
if (!cnt) {
@@ -808,7 +808,7 @@ static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
return -1;
}
- pci_mmio_write_config8(c->branch->branchdev,
+ pci_write_config8(c->branch->branchdev,
c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
for(i = 0; i < 4; i++) {
@@ -841,20 +841,20 @@ static int i5000_setup_channel(struct i5000_fbd_channel *c)
int off = c->branch->num ? 0x100 : 0;
u32 val;
- pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
- pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
- pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
- pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
+ pci_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+ pci_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+ pci_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
+ pci_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
- pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
+ pci_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
/* unknown */
- val = pci_mmio_read_config32(branchdev, off + 0x0164);
+ val = pci_read_config32(branchdev, off + 0x0164);
val &= 0xfffbcffc;
val |= 0x4004;
- pci_mmio_write_config32(branchdev, off + 0x164, val);
+ pci_write_config32(branchdev, off + 0x164, val);
- pci_mmio_write_config32(branchdev, off + 0x15c, 0xff);
+ pci_write_config32(branchdev, off + 0x15c, 0xff);
i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
return 0;
}
@@ -863,7 +863,7 @@ static int i5000_link_training0(struct i5000_fbd_branch *b)
{
device_t branchdev = b->branchdev;
- pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
+ pci_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
if (i5000_for_each_channel(b, i5000_setup_channel))
return -1;
@@ -1137,7 +1137,7 @@ static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
(1 << 7) | /* Electrical Throttling enabled */
(1 << 8)); /* DIMM present and compatible */
printk(BIOS_DEBUG, "MTR0: %04x\n", val);
- pci_mmio_write_config16(c->branch->branchdev, mtr, val);
+ pci_write_config16(c->branch->branchdev, mtr, val);
}
if (c->dimm[2].present || c->dimm[3].present) {
@@ -1149,7 +1149,7 @@ static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
(1 << 7) | /* Electrical Throttling enabled */
(1 << 8)); /* DIMM present and compatible */
printk(BIOS_DEBUG, "MTR1: %04x\n", val);
- pci_mmio_write_config16(c->branch->branchdev, mtr+2, val);
+ pci_write_config16(c->branch->branchdev, mtr+2, val);
}
}
@@ -1240,14 +1240,14 @@ static int i5000_setup_dmir(struct i5000_fbd_branch *b)
printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
dmirval);
- pci_mmio_write_config32(dev, dmir, dmirval);
+ pci_write_config32(dev, dmir, dmirval);
dmir += 4;
}
for(; dmir <= I5000_DMIR4; dmir += 4) {
printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
dmirval);
- pci_mmio_write_config32(dev, dmir, dmirval);
+ pci_write_config32(dev, dmir, dmirval);
}
return rankoffset;
}
@@ -1286,9 +1286,9 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup)
printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);;
printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);;
- pci_mmio_write_config16(dev16, I5000_MIR0, mir0);
- pci_mmio_write_config16(dev16, I5000_MIR1, mir1);
- pci_mmio_write_config16(dev16, I5000_MIR2, mir2);
+ pci_write_config16(dev16, I5000_MIR0, mir0);
+ pci_write_config16(dev16, I5000_MIR1, mir1);
+ pci_write_config16(dev16, I5000_MIR2, mir2);
}
static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
@@ -1326,11 +1326,11 @@ static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
(1 << 5); /* enable northbound error detection */
printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
- pci_mmio_write_config32(dev16, I5000_DRTA, drta);
- pci_mmio_write_config32(dev16, I5000_DRTB, drtb);
- pci_mmio_write_config32(dev16, I5000_MC, mc);
+ pci_write_config32(dev16, I5000_DRTA, drta);
+ pci_write_config32(dev16, I5000_DRTB, drtb);
+ pci_write_config32(dev16, I5000_MC, mc);
- mca = pci_mmio_read_config32(dev16, I5000_MCA);
+ mca = pci_read_config32(dev16, I5000_MCA);
mca |= (7 << 28);
if (setup->single_channel)
@@ -1338,9 +1338,9 @@ static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
else
mca &= ~(1 << 14);
printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
- pci_mmio_write_config32(dev16, I5000_MCA, mca);
+ pci_write_config32(dev16, I5000_MCA, mca);
- pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
+ pci_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
@@ -1354,7 +1354,7 @@ static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
tolm <<= 4;
printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
- pci_mmio_write_config16(dev16, I5000_TOLM, tolm);
+ pci_write_config16(dev16, I5000_TOLM, tolm);
return 0;
}
@@ -1398,62 +1398,62 @@ static void i5000_init_setup(struct i5000_fbd_setup *setup)
static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
{
/* register write captured from vendor BIOS, but undocument by Intel */
- pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
-
- pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
- pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
- pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
- pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
- pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
-
- pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
- pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
- pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
-
- pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
- pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
- pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
- pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
-
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
-
- pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
- pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
-
- pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
- pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
-
- pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
- pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
- pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
- pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
- pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
- pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
+ pci_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
+
+ pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
+ pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
+ pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
+ pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
+ pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
+
+ pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
+ pci_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
+ pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
+
+ pci_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
+ pci_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
+ pci_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
+ pci_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
+
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
+
+ pci_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
+ pci_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
+
+ pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
+ pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
+
+ pci_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
+ pci_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
+ pci_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
+ pci_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
+ pci_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
+ pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
if (setup->branch[0].channel[0].used)
- pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
+ pci_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
if (setup->branch[0].channel[1].used)
- pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
+ pci_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
if (setup->branch[1].channel[0].used)
- pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
+ pci_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
if (setup->branch[1].channel[1].used)
- pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
+ pci_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
}
static void i5000_dump_error_registers(void)
{
@@ -1467,22 +1467,22 @@ static void i5000_dump_error_registers(void)
"ERR1_FBD: 0x%08x\n"
"ERR2_FBD: 0x%08x\n"
"MC_ERR_FBD: 0x%08x\n",
- pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD),
- pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD),
- pci_mmio_read_config32(dev, I5000_FERR_NF_FBD),
- pci_mmio_read_config32(dev, I5000_NERR_NF_FBD),
- pci_mmio_read_config32(dev, I5000_EMASK_FBD),
- pci_mmio_read_config32(dev, I5000_ERR0_FBD),
- pci_mmio_read_config32(dev, I5000_ERR1_FBD),
- pci_mmio_read_config32(dev, I5000_ERR2_FBD),
- pci_mmio_read_config32(dev, I5000_MCERR_FBD));
+ pci_read_config32(dev, I5000_FERR_FAT_FBD),
+ pci_read_config32(dev, I5000_NERR_FAT_FBD),
+ pci_read_config32(dev, I5000_FERR_NF_FBD),
+ pci_read_config32(dev, I5000_NERR_NF_FBD),
+ pci_read_config32(dev, I5000_EMASK_FBD),
+ pci_read_config32(dev, I5000_ERR0_FBD),
+ pci_read_config32(dev, I5000_ERR1_FBD),
+ pci_read_config32(dev, I5000_ERR2_FBD),
+ pci_read_config32(dev, I5000_MCERR_FBD));
printk(BIOS_ERR, "Non recoverable error registers:\n"
"NRECMEMA: 0x%08x NRECMEMB: 0x%08x\n"
"NRECFGLOG: 0x%08x\n",
- pci_mmio_read_config32(dev, I5000_NRECMEMA),
- pci_mmio_read_config32(dev, I5000_NRECMEMB),
- pci_mmio_read_config32(dev, I5000_NRECFGLOG));
+ pci_read_config32(dev, I5000_NRECMEMA),
+ pci_read_config32(dev, I5000_NRECMEMB),
+ pci_read_config32(dev, I5000_NRECFGLOG));
printk(BIOS_ERR, "Packet data:\n"
"NRECFBDA: 0x%08x\n"
@@ -1490,18 +1490,18 @@ static void i5000_dump_error_registers(void)
"NRECFBDC: 0x%08x\n"
"NRECFBDD: 0x%08x\n"
"NRECFBDE: 0x%08x\n",
- pci_mmio_read_config32(dev, I5000_NRECFBDA),
- pci_mmio_read_config32(dev, I5000_NRECFBDB),
- pci_mmio_read_config32(dev, I5000_NRECFBDC),
- pci_mmio_read_config32(dev, I5000_NRECFBDD),
- pci_mmio_read_config32(dev, I5000_NRECFBDE));
+ pci_read_config32(dev, I5000_NRECFBDA),
+ pci_read_config32(dev, I5000_NRECFBDB),
+ pci_read_config32(dev, I5000_NRECFBDC),
+ pci_read_config32(dev, I5000_NRECFBDD),
+ pci_read_config32(dev, I5000_NRECFBDE));
printk(BIOS_ERR, "recoverable error registers:\n"
"RECMEMA: 0x%08x RECMEMB: 0x%08x\n"
"RECFGLOG: 0x%08x\n",
- pci_mmio_read_config32(dev, I5000_RECMEMA),
- pci_mmio_read_config32(dev, I5000_RECMEMB),
- pci_mmio_read_config32(dev, I5000_RECFGLOG));
+ pci_read_config32(dev, I5000_RECMEMA),
+ pci_read_config32(dev, I5000_RECMEMB),
+ pci_read_config32(dev, I5000_RECFGLOG));
printk(BIOS_ERR, "Packet data:\n"
"RECFBDA: 0x%08x\n"
@@ -1509,11 +1509,11 @@ static void i5000_dump_error_registers(void)
"RECFBDC: 0x%08x\n"
"RECFBDD: 0x%08x\n"
"RECFBDE: 0x%08x\n",
- pci_mmio_read_config32(dev, I5000_RECFBDA),
- pci_mmio_read_config32(dev, I5000_RECFBDB),
- pci_mmio_read_config32(dev, I5000_RECFBDC),
- pci_mmio_read_config32(dev, I5000_RECFBDD),
- pci_mmio_read_config32(dev, I5000_RECFBDE));
+ pci_read_config32(dev, I5000_RECFBDA),
+ pci_read_config32(dev, I5000_RECFBDB),
+ pci_read_config32(dev, I5000_RECFBDC),
+ pci_read_config32(dev, I5000_RECFBDD),
+ pci_read_config32(dev, I5000_RECFBDE));
}
@@ -1527,13 +1527,13 @@ static void i5000_try_restart(const char *msg)
static void i5000_pam_setup(void)
{
- pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
- pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
- pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
- pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
- pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
- pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
- pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
+ pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
+ pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
+ pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
+ pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
+ pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
+ pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
+ pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
}
static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
@@ -1575,7 +1575,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
}
- ddrfrq = pci_mmio_read_config8(PCI_ADDR(0, 16, 1, 0), 0x56);
+ ddrfrq = pci_read_config8(PCI_ADDR(0, 16, 1, 0), 0x56);
ddrfrqnow = ddrfrq;
ddrfrq &= ~0x3;
@@ -1586,32 +1586,32 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
switch((ddrfrq >> 4) & 3) {
case 0: /* 1:1 mapping */
- pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0xffffffff);
- pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);
- pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0xffffffff);
- pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);
- pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x00);
- pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00);
- pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);
+ pci_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0xffffffff);
+ pci_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);
+ pci_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0xffffffff);
+ pci_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);
+ pci_write_config8(dev, I5000_GRHOSTFULLCFG, 0x00);
+ pci_write_config8(dev, I5000_GRBUBBLECFG, 0x00);
+ pci_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);
break;
case 2: /* 4:5 mapping */
- pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00002323);
- pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000400);
- pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x23023);
- pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x04);
- pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x08);
- pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00);
- pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x04);
+ pci_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00002323);
+ pci_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000400);
+ pci_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x23023);
+ pci_write_config8(dev, I5000_GRFBDLVLDCFG, 0x04);
+ pci_write_config8(dev, I5000_GRHOSTFULLCFG, 0x08);
+ pci_write_config8(dev, I5000_GRBUBBLECFG, 0x00);
+ pci_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x04);
break;
case 3:
/* 5:4 mapping */
- pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00023230);
- pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);
- pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x4323);
- pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);
- pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x02);
- pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x10);
- pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);
+ pci_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00023230);
+ pci_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000);
+ pci_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x4323);
+ pci_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00);
+ pci_write_config8(dev, I5000_GRHOSTFULLCFG, 0x02);
+ pci_write_config8(dev, I5000_GRBUBBLECFG, 0x10);
+ pci_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00);
break;
default:
printk(BIOS_DEBUG, "invalid DDRFRQ: %02x\n", ddrfrq);
@@ -1621,7 +1621,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
if (ddrfrq != ddrfrqnow) {
printk(BIOS_DEBUG, "old DDRFRQ: 0x%02x new DDRFRQ: 0x%02x\n",
ddrfrqnow, ddrfrq);
- pci_mmio_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq);
+ pci_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq);
/* FSB:FBD mapping changed, needs hard reset */
outb(0x06, 0xcf9);
for(;;) asm volatile("hlt");
@@ -1636,12 +1636,12 @@ void i5000_fbdimm_init(void)
memset(&setup, 0, sizeof(setup));
- pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);
+ pci_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);
i5000_init_setup(&setup);
pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
- pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
+ pci_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
i5000_clear_fbd_errors();
@@ -1671,16 +1671,16 @@ void i5000_fbdimm_init(void)
setup.branch[1].channel[0].used ||
setup.branch[1].channel[1].used));
- pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
- pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
+ pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
+ pci_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
/* enable or disable single channel mode */
- mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
+ mca = pci_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
if (setup.single_channel)
mca |= (1 << 14);
else
mca &= ~(1 << 14);
- pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
+ pci_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
/*
* i5000 supports burst length 8 only in single channel mode
@@ -1693,9 +1693,9 @@ void i5000_fbdimm_init(void)
if (!setup.bl)
die("No supported burst length found\n");
- mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
+ mc = pci_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
/* disable error checking for training */
- pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
+ pci_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
printk(BIOS_INFO, "performing fbd link initialization...");
if (i5000_for_each_branch(&setup, i5000_branch_reset) ||
@@ -1740,7 +1740,7 @@ void i5000_fbdimm_init(void)
i5000_clear_fbd_errors();
/* enable error checking */
- pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
+ pci_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
i5000_dram_timing_init(&setup);
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New patch to review for coreboot: 24275d1 intel/lynxpoint: remove explicit pcie config accesses
by Kyösti Mälkki 26 Jul '13
by Kyösti Mälkki 26 Jul '13
26 Jul '13
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3812
-gerrit
commit 24275d119b86abf38a817c6327663f3897114886
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Jul 26 08:52:49 2013 +0300
intel/lynxpoint: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I71923790aa03e51db01ae3a4745e1c44556d281f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/southbridge/intel/lynxpoint/azalia.c | 18 +++++++++---------
src/southbridge/intel/lynxpoint/pcie.c | 18 +++++++++---------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index ac2b79d..ad78e83 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -252,28 +252,28 @@ static void azalia_init(struct device *dev)
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) {
- reg32 = pci_mmio_read_config32(dev, 0x120);
+ reg32 = pci_read_config32(dev, 0x120);
reg32 &= 0xf8ffff01;
reg32 |= (1 << 24); // 25 for server
reg32 |= RCBA32(0x2030) & 0xfe;
- pci_mmio_write_config32(dev, 0x120, reg32);
+ pci_write_config32(dev, 0x120, reg32);
- reg16 = pci_mmio_read_config16(dev, 0x78);
+ reg16 = pci_read_config16(dev, 0x78);
reg16 &= ~(1 << 11);
- pci_mmio_write_config16(dev, 0x78, reg16);
+ pci_write_config16(dev, 0x78, reg16);
} else
printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
- reg32 = pci_mmio_read_config32(dev, 0x114);
+ reg32 = pci_read_config32(dev, 0x114);
reg32 &= ~0xfe;
- pci_mmio_write_config32(dev, 0x114, reg32);
+ pci_write_config32(dev, 0x114, reg32);
// Set VCi enable bit
- if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) |
+ if (pci_read_config32(dev, 0x120) & ((1 << 24) |
(1 << 25) | (1 << 26))) {
- reg32 = pci_mmio_read_config32(dev, 0x120);
+ reg32 = pci_read_config32(dev, 0x120);
reg32 |= (1 << 31);
- pci_mmio_write_config32(dev, 0x120, reg32);
+ pci_write_config32(dev, 0x120, reg32);
}
// Enable HDMI codec:
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 9463d0c..a3b84e3 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -141,30 +141,30 @@ static void pch_pcie_pm_late(struct device *dev)
u32 reg32;
/* Set 0x314 = 0x743a361b */
- pci_mmio_write_config32(dev, 0x314, 0x743a361b);
+ pci_write_config32(dev, 0x314, 0x743a361b);
/* Set 0x318[31:16] = 0x1414 */
- reg32 = pci_mmio_read_config32(dev, 0x318);
+ reg32 = pci_read_config32(dev, 0x318);
reg32 &= 0x0000ffff;
reg32 |= 0x14140000;
- pci_mmio_write_config32(dev, 0x318, reg32);
+ pci_write_config32(dev, 0x318, reg32);
/* Set 0x324[5] = 1 */
- reg32 = pci_mmio_read_config32(dev, 0x324);
+ reg32 = pci_read_config32(dev, 0x324);
reg32 |= (1 << 5);
- pci_mmio_write_config32(dev, 0x324, reg32);
+ pci_write_config32(dev, 0x324, reg32);
/* Set 0x330[7:0] = 0x40 */
- reg32 = pci_mmio_read_config32(dev, 0x330);
+ reg32 = pci_read_config32(dev, 0x330);
reg32 &= ~(0xff);
reg32 |= 0x40;
- pci_mmio_write_config32(dev, 0x330, reg32);
+ pci_write_config32(dev, 0x330, reg32);
/* Set 0x33C[24:0] = 0x854c74 */
- reg32 = pci_mmio_read_config32(dev, 0x33c);
+ reg32 = pci_read_config32(dev, 0x33c);
reg32 &= 0xff000000;
reg32 |= 0x00854c74;
- pci_mmio_write_config32(dev, 0x33c, reg32);
+ pci_write_config32(dev, 0x33c, reg32);
/* No IO-APIC, Disable EOI forwarding */
reg32 = pci_read_config32(dev, 0xd4);
1
0