coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 85581ec cpu/intel/model_67x: Add missing include
by Kyösti Mälkki 28 Jul '13

28 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3826 -gerrit commit 85581ec74cc61c475ac3279e932b812f47e06737 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 28 20:39:40 2013 +0300 cpu/intel/model_67x: Add missing include The added device.h file was indirectly picked from cpu.h, which will have this include removed in a follow-up patch. Change-Id: Ifc0a4800de3b1ef220ab1034934f583be8c527b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_67x/model_67x_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index d34e4da..3ebe361 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> +#include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic.h>

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Patch set updated for coreboot: 6c42978 Add directive __SIMPLE_DEVICE__
by Kyösti Mälkki 28 Jul '13

28 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3555 -gerrit commit 6c42978fa13fbb34298dd787f29d424f92ce5db5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 25 23:17:43 2013 +0300 Add directive __SIMPLE_DEVICE__ The tests for __PRE_RAM__ or __SMM__ were repeatedly used for detection if dev->ops in the devicetree are not available and simple device model functions need be used. If a source file build for ramstage had __PRE_RAM__ inserted at the beginning, the struct device would no longer match the allocation the object had taken. This problem is fixed by replacing such cases with explicit __SIMPLE_DEVICE__. Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/rules.h | 34 ++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/cpu.h | 12 +++++------ src/arch/x86/include/arch/io.h | 6 +++++- src/arch/x86/include/arch/pci_ops.h | 4 ++++ src/arch/x86/include/arch/rules.h | 34 ++++++++++++++++++++++++++++++++ src/include/device/device.h | 21 +++++++++++--------- src/include/device/pci.h | 6 ++++-- src/include/device/pci_ops.h | 2 +- src/include/device/pnp.h | 6 ++++-- src/lib/uart8250mem.c | 4 +--- src/northbridge/intel/gm45/ram_calc.c | 6 +++--- src/northbridge/intel/sch/port_access.c | 6 +++--- src/southbridge/amd/agesa/hudson/reset.c | 6 +++--- src/southbridge/amd/cimx/sb700/reset.c | 6 +++--- src/southbridge/amd/cimx/sb800/reset.c | 6 +++--- src/southbridge/amd/cimx/sb900/early.c | 6 +++--- src/southbridge/amd/cimx/sb900/reset.c | 6 +++--- src/southbridge/amd/sb600/reset.c | 6 +++--- src/southbridge/amd/sb700/reset.c | 6 +++--- src/southbridge/amd/sb800/reset.c | 6 +++--- src/southbridge/intel/common/usb_debug.c | 6 +++--- 21 files changed, 138 insertions(+), 57 deletions(-) diff --git a/src/arch/armv7/include/arch/rules.h b/src/arch/armv7/include/arch/rules.h new file mode 100644 index 0000000..a790365 --- /dev/null +++ b/src/arch/armv7/include/arch/rules.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__PRE_RAM__) +#define __SIMPLE_DEVICE__ +#endif + +#endif /* _ARCH_RULES_H */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 6944834..3e50be4 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -2,6 +2,7 @@ #define ARCH_CPU_H #include <stdint.h> +#include <arch/rules.h> /* * EFLAGS bits @@ -141,12 +142,13 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> - int cpu_phys_address_size(void); int cpu_have_cpuid(void); +#ifndef __SIMPLE_DEVICE__ + +struct device; + struct cpu_device_id { unsigned vendor; unsigned device; @@ -163,7 +165,7 @@ struct cpu_driver *find_cpu_driver(struct device *cpu); struct thread; struct cpu_info { - device_t cpu; + struct device *cpu; unsigned int index; #if CONFIG_COOP_MULTITASKING struct thread *thread; @@ -188,8 +190,6 @@ static inline unsigned long cpu_index(void) ci = cpu_info(); return ci->index; } -#else -#include <arch/io.h> #endif #ifndef __ROMCC__ // romcc is segfaulting in some cases diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index b258dd0..3b61e85 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -2,6 +2,7 @@ #define _ASM_IO_H #include <stdint.h> +#include <arch/rules.h> /* * This file contains the definitions for the x86 IO instructions @@ -188,6 +189,9 @@ static inline int log2f(int value) return r; } +#endif + +#ifdef __SIMPLE_DEVICE__ #define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ (((SEGBUS) & 0xFFF) << 20) | \ @@ -325,7 +329,7 @@ static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsi pnp_write_config(dev, index, drq & 0xff); } -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ #endif diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index b7ec0ba..e1b148b 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -1,6 +1,8 @@ #ifndef ARCH_I386_PCI_OPS_H #define ARCH_I386_PCI_OPS_H +#ifndef __SIMPLE_DEVICE__ + extern const struct pci_bus_operations pci_cf8_conf1; #if CONFIG_MMCONF_SUPPORT @@ -9,4 +11,6 @@ extern const struct pci_bus_operations pci_ops_mmconf; const struct pci_bus_operations *pci_bus_default_ops(device_t dev); +#endif + #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/arch/x86/include/arch/rules.h b/src/arch/x86/include/arch/rules.h new file mode 100644 index 0000000..4b84677 --- /dev/null +++ b/src/arch/x86/include/arch/rules.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__PRE_RAM__) || defined(__SMM__) +#define __SIMPLE_DEVICE__ +#endif + +#endif /* _ARCH_RULES_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index 1eff4a2..797e717 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -1,14 +1,15 @@ #ifndef DEVICE_H #define DEVICE_H -#ifndef __SMM__ #include <stdint.h> #include <stddef.h> +#include <arch/rules.h> #include <device/resource.h> #include <device/path.h> struct device; -#ifndef __PRE_RAM__ + +#ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; @@ -45,7 +46,7 @@ struct device_operations { const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); const struct pnp_mode_ops *ops_pnp_mode; }; -#endif +#endif /* ! __SIMPLE_DEVICE__ */ struct bus { @@ -116,9 +117,10 @@ struct device { * static.c file and is generated by the config tool at compile time. */ extern ROMSTAGE_CONST struct device dev_root; -#ifndef __PRE_RAM__ -extern struct device *all_devices; /* list of all devices */ +#ifndef __SIMPLE_DEVICE__ + +extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; extern struct bus *free_links; @@ -222,13 +224,14 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); -#else + +#else /* vv __SIMPLE_DEVICE__ vv */ + ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, unsigned int devfn); ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); + #endif -#else /* __SMM__ */ -#include <arch/io.h> -#endif /* __SMM__ */ + #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 2dea1cf..be91ed3 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -17,13 +17,15 @@ #include <stdint.h> #include <stddef.h> +#include <arch/rules.h> #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> -#if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/pci_ops.h> #include <device/pci_rom.h> +#ifndef __SIMPLE_DEVICE__ + /* Common pci operations without a standard interface */ struct pci_operations { /* set the Subsystem IDs for the PCI device */ @@ -94,5 +96,5 @@ static inline const struct pci_operations *ops_pci(device_t dev) return pops; } -#endif +#endif /* ! __SIMPLE_DEVICE__ */ #endif /* PCI_H */ diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 20fbb99..ae58a01 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -1,11 +1,11 @@ #ifndef PCI_OPS_H #define PCI_OPS_H -#ifndef __SMM__ #include <stdint.h> #include <device/device.h> #include <arch/pci_ops.h> +#ifndef __SIMPLE_DEVICE__ u8 pci_read_config8(device_t dev, unsigned int where); u16 pci_read_config16(device_t dev, unsigned int where); u32 pci_read_config32(device_t dev, unsigned int where); diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 434f0a4..a229edb 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -2,10 +2,12 @@ #define DEVICE_PNP_H #include <stdint.h> +#include <arch/rules.h> #include <device/device.h> #include <device/pnp_def.h> -#if !defined(__PRE_RAM__) && !defined(__SMM__) +#ifndef __SIMPLE_DEVICE__ + /* Primitive PNP resource manipulation */ void pnp_write_config(device_t dev, u8 reg, u8 value); u8 pnp_read_config(device_t dev, u8 reg); @@ -59,5 +61,5 @@ struct pnp_mode_ops { void pnp_enter_conf_mode(device_t dev); void pnp_exit_conf_mode(device_t dev); -#endif +#endif /* ! __SIMPLE_DEVICE__ */ #endif /* DEVICE_PNP_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 8224843..8d85855 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -24,9 +24,7 @@ #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif -#if !defined(__SMM__) && !defined(__PRE_RAM__) #include <device/device.h> -#endif #include <delay.h> /* Should support 8250, 16450, 16550, 16550A type UARTs */ @@ -129,7 +127,7 @@ u32 uart_mem_init(void) /* Now find the UART base address and calculate the divisor */ #if CONFIG_DRIVERS_OXFORD_OXPCIE -#if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__) +#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) device_t dev = dev_find_device(0x1415, 0xc158, NULL); if (!dev) dev = dev_find_device(0x1415, 0xc11b, NULL); diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 9e54c10..4590544 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -19,9 +19,9 @@ * MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c index c73f709..a33a564 100644 --- a/src/northbridge/intel/sch/port_access.c +++ b/src/northbridge/intel/sch/port_access.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <device/pci_def.h> diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index 315a065..79fd79e 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb700/reset.c +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index d6036dd..4879904 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <device/pci_ids.h> #include <arch/io.h> diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c index 0936516..1ef408b 100644 --- a/src/southbridge/amd/sb600/reset.c +++ b/src/southbridge/amd/sb600/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index ef4115e..e457368 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index 315a065..79fd79e 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 397c686..d140123 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <console/console.h>

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Patch set updated for coreboot: 0815840 Add directive __SIMPLE_DEVICE__
by Kyösti Mälkki 28 Jul '13

28 Jul '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3555 -gerrit commit 0815840a651105f095f513466c85d1b40b17e832 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 25 23:17:43 2013 +0300 Add directive __SIMPLE_DEVICE__ The tests for __PRE_RAM__ or __SMM__ were repeatedly used for detection if dev->ops in the devicetree are not available and simple device model functions need be used. If a source file build for ramstage had __PRE_RAM__ inserted at the beginning, the struct device would no longer match the allocation the object had taken. This problem is fixed by replacing such cases with explicit __SIMPLE_DEVICE__. Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/rules.h | 34 ++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/cpu.h | 12 +++++------ src/arch/x86/include/arch/io.h | 6 +++++- src/arch/x86/include/arch/pci_ops.h | 4 ++++ src/arch/x86/include/arch/rules.h | 34 ++++++++++++++++++++++++++++++++ src/include/device/device.h | 21 +++++++++++--------- src/include/device/pci.h | 6 ++++-- src/include/device/pci_ops.h | 2 +- src/include/device/pnp.h | 6 ++++-- src/lib/uart8250mem.c | 4 +--- src/northbridge/intel/gm45/ram_calc.c | 6 +++--- src/northbridge/intel/sch/port_access.c | 6 +++--- src/southbridge/amd/agesa/hudson/reset.c | 6 +++--- src/southbridge/amd/cimx/sb700/reset.c | 6 +++--- src/southbridge/amd/cimx/sb800/reset.c | 6 +++--- src/southbridge/amd/cimx/sb900/early.c | 6 +++--- src/southbridge/amd/cimx/sb900/reset.c | 6 +++--- src/southbridge/amd/sb600/reset.c | 6 +++--- src/southbridge/amd/sb700/reset.c | 6 +++--- src/southbridge/amd/sb800/reset.c | 6 +++--- src/southbridge/intel/common/usb_debug.c | 6 +++--- 21 files changed, 138 insertions(+), 57 deletions(-) diff --git a/src/arch/armv7/include/arch/rules.h b/src/arch/armv7/include/arch/rules.h new file mode 100644 index 0000000..a790365 --- /dev/null +++ b/src/arch/armv7/include/arch/rules.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__PRE_RAM__) +#define __SIMPLE_DEVICE__ +#endif + +#endif /* _ARCH_RULES_H */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 6944834..3e50be4 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -2,6 +2,7 @@ #define ARCH_CPU_H #include <stdint.h> +#include <arch/rules.h> /* * EFLAGS bits @@ -141,12 +142,13 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> - int cpu_phys_address_size(void); int cpu_have_cpuid(void); +#ifndef __SIMPLE_DEVICE__ + +struct device; + struct cpu_device_id { unsigned vendor; unsigned device; @@ -163,7 +165,7 @@ struct cpu_driver *find_cpu_driver(struct device *cpu); struct thread; struct cpu_info { - device_t cpu; + struct device *cpu; unsigned int index; #if CONFIG_COOP_MULTITASKING struct thread *thread; @@ -188,8 +190,6 @@ static inline unsigned long cpu_index(void) ci = cpu_info(); return ci->index; } -#else -#include <arch/io.h> #endif #ifndef __ROMCC__ // romcc is segfaulting in some cases diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index b258dd0..3b61e85 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -2,6 +2,7 @@ #define _ASM_IO_H #include <stdint.h> +#include <arch/rules.h> /* * This file contains the definitions for the x86 IO instructions @@ -188,6 +189,9 @@ static inline int log2f(int value) return r; } +#endif + +#ifdef __SIMPLE_DEVICE__ #define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ (((SEGBUS) & 0xFFF) << 20) | \ @@ -325,7 +329,7 @@ static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsi pnp_write_config(dev, index, drq & 0xff); } -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ #endif diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index b7ec0ba..e1b148b 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -1,6 +1,8 @@ #ifndef ARCH_I386_PCI_OPS_H #define ARCH_I386_PCI_OPS_H +#ifndef __SIMPLE_DEVICE__ + extern const struct pci_bus_operations pci_cf8_conf1; #if CONFIG_MMCONF_SUPPORT @@ -9,4 +11,6 @@ extern const struct pci_bus_operations pci_ops_mmconf; const struct pci_bus_operations *pci_bus_default_ops(device_t dev); +#endif + #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/arch/x86/include/arch/rules.h b/src/arch/x86/include/arch/rules.h new file mode 100644 index 0000000..4b84677 --- /dev/null +++ b/src/arch/x86/include/arch/rules.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__PRE_RAM__) || defined(__SMM__) +#define __SIMPLE_DEVICE__ +#endif + +#endif /* _ARCH_RULES_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index 1eff4a2..797e717 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -1,14 +1,15 @@ #ifndef DEVICE_H #define DEVICE_H -#ifndef __SMM__ #include <stdint.h> #include <stddef.h> +#include <arch/rules.h> #include <device/resource.h> #include <device/path.h> struct device; -#ifndef __PRE_RAM__ + +#ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; @@ -45,7 +46,7 @@ struct device_operations { const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); const struct pnp_mode_ops *ops_pnp_mode; }; -#endif +#endif /* ! __SIMPLE_DEVICE__ */ struct bus { @@ -116,9 +117,10 @@ struct device { * static.c file and is generated by the config tool at compile time. */ extern ROMSTAGE_CONST struct device dev_root; -#ifndef __PRE_RAM__ -extern struct device *all_devices; /* list of all devices */ +#ifndef __SIMPLE_DEVICE__ + +extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; extern struct bus *free_links; @@ -222,13 +224,14 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); -#else + +#else /* vv __SIMPLE_DEVICE__ vv */ + ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, unsigned int devfn); ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); + #endif -#else /* __SMM__ */ -#include <arch/io.h> -#endif /* __SMM__ */ + #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 2dea1cf..be91ed3 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -17,13 +17,15 @@ #include <stdint.h> #include <stddef.h> +#include <arch/rules.h> #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> -#if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/pci_ops.h> #include <device/pci_rom.h> +#ifndef __SIMPLE_DEVICE__ + /* Common pci operations without a standard interface */ struct pci_operations { /* set the Subsystem IDs for the PCI device */ @@ -94,5 +96,5 @@ static inline const struct pci_operations *ops_pci(device_t dev) return pops; } -#endif +#endif /* ! __SIMPLE_DEVICE__ */ #endif /* PCI_H */ diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 20fbb99..ae58a01 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -1,11 +1,11 @@ #ifndef PCI_OPS_H #define PCI_OPS_H -#ifndef __SMM__ #include <stdint.h> #include <device/device.h> #include <arch/pci_ops.h> +#ifndef __SIMPLE_DEVICE__ u8 pci_read_config8(device_t dev, unsigned int where); u16 pci_read_config16(device_t dev, unsigned int where); u32 pci_read_config32(device_t dev, unsigned int where); diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 434f0a4..a229edb 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -2,10 +2,12 @@ #define DEVICE_PNP_H #include <stdint.h> +#include <arch/rules.h> #include <device/device.h> #include <device/pnp_def.h> -#if !defined(__PRE_RAM__) && !defined(__SMM__) +#ifndef __SIMPLE_DEVICE__ + /* Primitive PNP resource manipulation */ void pnp_write_config(device_t dev, u8 reg, u8 value); u8 pnp_read_config(device_t dev, u8 reg); @@ -59,5 +61,5 @@ struct pnp_mode_ops { void pnp_enter_conf_mode(device_t dev); void pnp_exit_conf_mode(device_t dev); -#endif +#endif /* ! __SIMPLE_DEVICE__ */ #endif /* DEVICE_PNP_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 8224843..8d85855 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -24,9 +24,7 @@ #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif -#if !defined(__SMM__) && !defined(__PRE_RAM__) #include <device/device.h> -#endif #include <delay.h> /* Should support 8250, 16450, 16550, 16550A type UARTs */ @@ -129,7 +127,7 @@ u32 uart_mem_init(void) /* Now find the UART base address and calculate the divisor */ #if CONFIG_DRIVERS_OXFORD_OXPCIE -#if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__) +#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) device_t dev = dev_find_device(0x1415, 0xc158, NULL); if (!dev) dev = dev_find_device(0x1415, 0xc11b, NULL); diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 9e54c10..4590544 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -19,9 +19,9 @@ * MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c index c73f709..a33a564 100644 --- a/src/northbridge/intel/sch/port_access.c +++ b/src/northbridge/intel/sch/port_access.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <device/pci_def.h> diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index 315a065..79fd79e 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb700/reset.c +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index d6036dd..4879904 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <device/pci_ids.h> #include <arch/io.h> diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c index 0936516..1ef408b 100644 --- a/src/southbridge/amd/sb600/reset.c +++ b/src/southbridge/amd/sb600/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index ef4115e..e457368 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index 315a065..79fd79e 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 397c686..d140123 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <console/console.h>

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New patch to review for coreboot: 65eff4e Rename sb900 Oem.h to OEM.h and SbEarly.h to sb_cimx.h
by Corey Osgood 28 Jul '13

28 Jul '13

Corey Osgood (corey.osgood(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3825 -gerrit commit 65eff4eca11b9d55f37d1d22c78e71123116b6f9 Author: Corey Osgood <corey.osgood(a)gmail.com> Date: Sun Jul 28 05:36:45 2013 -0400 Rename sb900 Oem.h to OEM.h and SbEarly.h to sb_cimx.h Northbridge code includes these headers, so they all need to have the same name to allow e.g. agesa/fam14 to use either sb800 or sb900 seemlessly. Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> --- src/mainboard/amd/torpedo/get_bus_conf.c | 2 +- src/mainboard/amd/torpedo/romstage.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/southbridge/amd/cimx/sb900/SbEarly.h | 56 ----- src/southbridge/amd/cimx/sb900/SbPlatform.h | 2 +- src/southbridge/amd/cimx/sb900/early.c | 2 +- src/southbridge/amd/cimx/sb900/sb_cimx.h | 56 +++++ .../amd/agesa/f12/Proc/Fch/FchPlatform.h | 2 +- src/vendorcode/amd/cimx/sb900/OEM.h | 233 +++++++++++++++++++++ src/vendorcode/amd/cimx/sb900/Oem.h | 233 --------------------- 10 files changed, 295 insertions(+), 295 deletions(-) diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index 4444937..fcc5e8d 100644 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -24,7 +24,7 @@ #include <stdint.h> #include <stdlib.h> #include <cpu/amd/amdfam12.h> -#include "SbEarly.h" +#include "sb_cimx.h" #include "agesawrapper.h" /* Global variables for MB layouts and these will be shared by irqtable mptable diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index bbcd764..00044c6 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -33,7 +33,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -#include "SbEarly.h" +#include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> #include "platform_cfg.h" diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 621246f..76a9604 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -34,7 +34,7 @@ #include <cpu/amd/mtrr.h> #include "northbridge.h" -#include "SbEarly.h" +#include "sb_cimx.h" #include "agesawrapper.h" //#define FX_DEVS NODE_NUMS diff --git a/src/southbridge/amd/cimx/sb900/SbEarly.h b/src/southbridge/amd/cimx/sb900/SbEarly.h deleted file mode 100644 index c5e37e5..0000000 --- a/src/southbridge/amd/cimx/sb900/SbEarly.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#ifndef _CIMX_SB_EARLY_H_ -#define _CIMX_SB_EARLY_H_ - -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 - -#define SB900_ACPI_IO_BASE 0x800 - -#define ACPI_PM_EVT_BLK (SB900_ACPI_IO_BASE + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (SB900_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (SB900_ACPI_IO_BASE + 0x0F) /* 1 byte */ -#define ACPI_PM_TMR_BLK (SB900_ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_GPE0_BLK (SB900_ACPI_IO_BASE + 0x20) /* 8 bytes */ -#define ACPI_CPU_CONTROL (SB900_ACPI_IO_BASE + 0x10) /* 6 bytes */ - -#define REV_SB900_A11 0x11 -#define REV_SB900_A12 0x12 - -/** - * @brief Get SouthBridge device number, called by finalize_node_setup() - * @param[in] bus target bus number - * @return southbridge device number - */ -u32 get_sbdn(u32 bus); - -/** - * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper. - */ -void sb_poweron_init(void); -void sb_before_pci_init(void); - -void sb_After_Pci_Init (void); -void sb_Mid_Post_Init (void); -void sb_Late_Post (void); - -#endif diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 36c186a..5e41978 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -67,7 +67,7 @@ typedef union _PCI_ADDR { #include "AmdSbLib.h" #include "SbSubFun.h" #include "platform_cfg.h" /* mainboard specific configuration */ -#include "Oem.h" /* platform default configuration */ +#include "OEM.h" /* platform default configuration */ #include "AMD.h" #include "SbBiosRamUsage.h" #include "EcFan.h" diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index d6036dd..8ed5c29 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -24,7 +24,7 @@ #include <device/pci_ids.h> #include <arch/io.h> #include "SbPlatform.h" -#include "SbEarly.h" +#include "sb_cimx.h" #include <console/console.h> #include <console/loglevel.h> #include "smbus.h" diff --git a/src/southbridge/amd/cimx/sb900/sb_cimx.h b/src/southbridge/amd/cimx/sb900/sb_cimx.h new file mode 100644 index 0000000..c5e37e5 --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/sb_cimx.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_SB_EARLY_H_ +#define _CIMX_SB_EARLY_H_ + +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 + +#define SB900_ACPI_IO_BASE 0x800 + +#define ACPI_PM_EVT_BLK (SB900_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (SB900_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (SB900_ACPI_IO_BASE + 0x0F) /* 1 byte */ +#define ACPI_PM_TMR_BLK (SB900_ACPI_IO_BASE + 0x08) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB900_ACPI_IO_BASE + 0x20) /* 8 bytes */ +#define ACPI_CPU_CONTROL (SB900_ACPI_IO_BASE + 0x10) /* 6 bytes */ + +#define REV_SB900_A11 0x11 +#define REV_SB900_A12 0x12 + +/** + * @brief Get SouthBridge device number, called by finalize_node_setup() + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus); + +/** + * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper. + */ +void sb_poweron_init(void); +void sb_before_pci_init(void); + +void sb_After_Pci_Init (void); +void sb_Mid_Post_Init (void); +void sb_Late_Post (void); + +#endif diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h index a8ff2f2..0561d3d 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h +++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h @@ -108,7 +108,7 @@ #include "FchCommonCfg.h" #include "AcpiLib.h" #include "FchDef.h" -#include "Oem.h" +#include "OEM.h" #include "FchBiosRamUsage.h" #include "AmdFch.h" diff --git a/src/vendorcode/amd/cimx/sb900/OEM.h b/src/vendorcode/amd/cimx/sb900/OEM.h new file mode 100755 index 0000000..f374b30 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb900/OEM.h @@ -0,0 +1,233 @@ +/*;******************************************************************************** +; +; Copyright (c) 2011, Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef BIOS_SIZE + #define BIOS_SIZE 0x04 //04 - 1MB +#endif +#ifndef LEGACY_FREE + #define LEGACY_FREE 0x00 +#endif +#define ACPI_SLEEP_TRAP 0x01 +//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 + +/** + * Module Specific Defines for platform BIOS + * + */ + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 + #define PCIEX_BASE_ADDRESS 0xF7000000 +#else + #define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + +/** + * SMBUS0_BASE_ADDRESS - Smbus base address + * + */ +#ifndef SMBUS0_BASE_ADDRESS + #define SMBUS0_BASE_ADDRESS 0xB00 +#endif + +/** + * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address + * + */ +#ifndef SMBUS1_BASE_ADDRESS + #define SMBUS1_BASE_ADDRESS 0xB20 +#endif + +/** + * SIO_PME_BASE_ADDRESS - Super IO PME base address + * + */ +#ifndef SIO_PME_BASE_ADDRESS + #define SIO_PME_BASE_ADDRESS 0xE00 +#endif + +/** + * SPI_BASE_ADDRESS - SPI controller (ROM) base address + * + */ +#ifndef SPI_BASE_ADDRESS + #define SPI_BASE_ADDRESS 0xFEC10000 +#endif + +/** + * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address + * + */ +#ifndef WATCHDOG_TIMER_BASE_ADDRESS + #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#endif + +/** + * HPET_BASE_ADDRESS - HPET base address + * + */ +#ifndef HPET_BASE_ADDRESS + #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address +#endif + +/** + * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address + * + */ +#ifdef ALT_ADDR_400 + #define ACPI_BLK_BASE 0x400 +#else + #define ACPI_BLK_BASE 0x800 +#endif + +#define PM1_STATUS_OFFSET 0x00 +#define PM1_ENABLE_OFFSET 0x02 +#define PM1_CONTROL_OFFSET 0x04 +#define PM_TIMER_OFFSET 0x08 +#define CPU_CONTROL_OFFSET 0x10 +#define EVENT_STATUS_OFFSET 0x20 +#define EVENT_ENABLE_OFFSET 0x24 + +/** + * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address + * + */ +#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr + +/** + * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address + * + */ +#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr + +/** + * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address + * + */ +#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr + +/** + * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address + * + */ +#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr + +/** + * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address + * + */ +#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr + +/** + * SMI_CMD_PORT - ACPI SMI Command block base address + * + */ +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr + +/** + * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address + * + */ +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr + +/** + * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. + * Define value for SSID while SATA controller set to IDE mode. + */ +#define SATA_IDE_MODE_SSID 0x78001022 +/** + * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID. + * Define value for SSID while SATA controller set to RAID mode. + */ +#define SATA_RAID_MODE_SSID 0x78021022 + +/** + * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID. + * Define value for SSID while SATA controller set to RAID5 mode. + */ +#define SATA_RAID5_MODE_SSID 0x78031022 + +/** + * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID. + * Define value for SSID while SATA controller set to AHCI mode. + */ +#define SATA_AHCI_SSID 0x78011022 + +/** + * OHCI_SSID - All SB OHCI controllers SSID value. + * + */ +#define OHCI_SSID 0x78071022 + +/** + * EHCI_SSID - All SB EHCI controllers SSID value. + * + */ +#define EHCI_SSID 0x78081022 + +/** + * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value. + * + */ +#define OHCI4_SSID 0x78091022 + +/** + * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value. + * + */ +#define SMBUS_SSID 0x780B1022 + +/** + * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value. + * + */ +#define IDE_SSID 0x780C1022 + +/** + * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value. + * + */ +#define AZALIA_SSID 0x780D1022 + +/** + * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value. + * + */ +#define LPC_SSID 0x780E1022 + +/** + * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value. + * + */ +#define PCIB_SSID 0x780F1022 + diff --git a/src/vendorcode/amd/cimx/sb900/Oem.h b/src/vendorcode/amd/cimx/sb900/Oem.h deleted file mode 100755 index f374b30..0000000 --- a/src/vendorcode/amd/cimx/sb900/Oem.h +++ /dev/null @@ -1,233 +0,0 @@ -/*;******************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;*********************************************************************************/ - -#ifndef BIOS_SIZE - #define BIOS_SIZE 0x04 //04 - 1MB -#endif -#ifndef LEGACY_FREE - #define LEGACY_FREE 0x00 -#endif -#define ACPI_SLEEP_TRAP 0x01 -//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 - -/** - * Module Specific Defines for platform BIOS - * - */ - -/** - * PCIEX_BASE_ADDRESS - Define PCIE base address - * - * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 - */ -#ifdef MOVE_PCIEBAR_TO_F0000000 - #define PCIEX_BASE_ADDRESS 0xF7000000 -#else - #define PCIEX_BASE_ADDRESS 0xE0000000 -#endif - -/** - * SMBUS0_BASE_ADDRESS - Smbus base address - * - */ -#ifndef SMBUS0_BASE_ADDRESS - #define SMBUS0_BASE_ADDRESS 0xB00 -#endif - -/** - * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address - * - */ -#ifndef SMBUS1_BASE_ADDRESS - #define SMBUS1_BASE_ADDRESS 0xB20 -#endif - -/** - * SIO_PME_BASE_ADDRESS - Super IO PME base address - * - */ -#ifndef SIO_PME_BASE_ADDRESS - #define SIO_PME_BASE_ADDRESS 0xE00 -#endif - -/** - * SPI_BASE_ADDRESS - SPI controller (ROM) base address - * - */ -#ifndef SPI_BASE_ADDRESS - #define SPI_BASE_ADDRESS 0xFEC10000 -#endif - -/** - * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address - * - */ -#ifndef WATCHDOG_TIMER_BASE_ADDRESS - #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address -#endif - -/** - * HPET_BASE_ADDRESS - HPET base address - * - */ -#ifndef HPET_BASE_ADDRESS - #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address -#endif - -/** - * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address - * - */ -#ifdef ALT_ADDR_400 - #define ACPI_BLK_BASE 0x400 -#else - #define ACPI_BLK_BASE 0x800 -#endif - -#define PM1_STATUS_OFFSET 0x00 -#define PM1_ENABLE_OFFSET 0x02 -#define PM1_CONTROL_OFFSET 0x04 -#define PM_TIMER_OFFSET 0x08 -#define CPU_CONTROL_OFFSET 0x10 -#define EVENT_STATUS_OFFSET 0x20 -#define EVENT_ENABLE_OFFSET 0x24 - -/** - * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address - * - */ -#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr - -/** - * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address - * - */ -#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr - -/** - * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address - * - */ -#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr - -/** - * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address - * - */ -#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr - -/** - * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address - * - */ -#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr - -/** - * SMI_CMD_PORT - ACPI SMI Command block base address - * - */ -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr - -/** - * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address - * - */ -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr - -/** - * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. - * Define value for SSID while SATA controller set to IDE mode. - */ -#define SATA_IDE_MODE_SSID 0x78001022 -/** - * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID. - * Define value for SSID while SATA controller set to RAID mode. - */ -#define SATA_RAID_MODE_SSID 0x78021022 - -/** - * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID. - * Define value for SSID while SATA controller set to RAID5 mode. - */ -#define SATA_RAID5_MODE_SSID 0x78031022 - -/** - * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID. - * Define value for SSID while SATA controller set to AHCI mode. - */ -#define SATA_AHCI_SSID 0x78011022 - -/** - * OHCI_SSID - All SB OHCI controllers SSID value. - * - */ -#define OHCI_SSID 0x78071022 - -/** - * EHCI_SSID - All SB EHCI controllers SSID value. - * - */ -#define EHCI_SSID 0x78081022 - -/** - * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value. - * - */ -#define OHCI4_SSID 0x78091022 - -/** - * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value. - * - */ -#define SMBUS_SSID 0x780B1022 - -/** - * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value. - * - */ -#define IDE_SSID 0x780C1022 - -/** - * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value. - * - */ -#define AZALIA_SSID 0x780D1022 - -/** - * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value. - * - */ -#define LPC_SSID 0x780E1022 - -/** - * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value. - * - */ -#define PCIB_SSID 0x780F1022 -

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Patch set updated for coreboot: 818621c AMD Olive Hill: Replace the development CODEC verb data
by Bruce Griffith 26 Jul '13

26 Jul '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3820 -gerrit commit 818621cc436bd9080ed0cded6a6547f9085d198f Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jun 18 18:09:07 2013 -0600 AMD Olive Hill: Replace the development CODEC verb data Replace the development CODEC verb table with one that was derived from Parmer and hand validated against the Realtek ALC272 spec. Change-Id: Ia302120e7bf9150a20f1c448b5cba6075e0e9da1 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/amd/olivehill/BiosCallOuts.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 3efaa2b..f86242d 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -66,20 +66,20 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) * AMD Olivehill Platform ALC272 Verb Table */ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, - {0x12, 0x411111F0}, - {0x13, 0x411111F0}, - {0x14, 0x411111F0}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x17, 0x411111F0}, - {0x18, 0x01a19840}, - {0x19, 0x411111F0}, - {0x1a, 0x01813030}, - {0x1b, 0x411111F0}, - {0x1d, 0x40130605}, - {0x1e, 0x01441120}, - {0x21, 0x01211010}, + {0x11, 0x411111F0}, // - SPDIF_OUT2 + {0x12, 0x411111F0}, // - DMIC_1/2 + {0x13, 0x411111F0}, // - DMIC_3/4 + {0x14, 0x411111F0}, // Port D - LOUT1 + {0x15, 0x411111F0}, // Port A - LOUT2 + {0x16, 0x411111F0}, // + {0x17, 0x411111F0}, // Port H - MONO + {0x18, 0x01a19840}, // Port B - MIC1 + {0x19, 0x411111F0}, // Port F - MIC2 + {0x1a, 0x01813030}, // Port C - LINE1 + {0x1b, 0x411111F0}, // Port E - LINE2 + {0x1d, 0x40130605}, // - PCBEEP + {0x1e, 0x01441120}, // - SPDIF_OUT1 + {0x21, 0x01214010}, // Port I - HPOUT {0xff, 0xffffffff} };

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Patch set updated for coreboot: 1fc305a AMD Olive Hill: Enable WARNINGS_ARE_ERRORS (remove override)
by Bruce Griffith 26 Jul '13

26 Jul '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3819 -gerrit commit 1fc305ac0dba61fbb8de51f9eb1fa6068567ce75 Author: Bruce Griffith <bruce.griffith(a)se-eng.com> Date: Tue Jul 23 21:43:52 2013 -0600 AMD Olive Hill: Enable WARNINGS_ARE_ERRORS (remove override) Change-Id: Idf26eb3fb541355bd9553c1897f647738c347eb5 Signed-off-by: Bruce Griffith <bruce.griffith(a)se-eng.com> --- src/mainboard/amd/olivehill/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index adb5d81..cacc0f4 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -97,8 +97,4 @@ config HUDSON_LEGACY_FREE bool default y -config WARNINGS_ARE_ERRORS - bool - default n - endif # BOARD_AMD_OLIVEHILL

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Patch set updated for coreboot: aff7ef8 AMD Olive Hill: Eliminate unnecessary memory copy
by Bruce Griffith 26 Jul '13

26 Jul '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3818 -gerrit commit aff7ef8c1960771f0809fbb11ed246113d615526 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed Jul 10 22:24:47 2013 -0600 AMD Olive Hill: Eliminate unnecessary memory copy Eliminate an unnecessary copy of the DDI descriptor list and the PCIe port descriptor list. As descriptor tables, these tables do not need dynamic updating and should be used from ROM without runtime copying. There will be a corresponding patch for AGESA that adds CONST modifiers to function parameters that are pass-by-reference "IN" values (read-only pointers). Change-Id: I7ab78e58041e9247db22d0f97a6f76d45f338db0 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Tested-by: Bruce Griffith <bruce.griffith(a)se-eng.com> --- src/mainboard/amd/olivehill/PlatformGnbPcie.c | 58 +++++++-------------------- 1 file changed, 14 insertions(+), 44 deletions(-) diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcie.c b/src/mainboard/amd/olivehill/PlatformGnbPcie.c index 1131718..3e1c327 100644 --- a/src/mainboard/amd/olivehill/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehill/PlatformGnbPcie.c @@ -26,7 +26,7 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE -PCIe_PORT_DESCRIPTOR PortList [] = { +static PCIe_PORT_DESCRIPTOR PortList [] = { { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), @@ -78,7 +78,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { } }; -PCIe_DDI_DESCRIPTOR DdiList [] = { +static PCIe_DDI_DESCRIPTOR DdiList [] = { /* DP0 to HDMI0/DP */ { 0, @@ -99,11 +99,11 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { }, }; -PCIe_COMPLEX_DESCRIPTOR Kabini = { - DESCRIPTOR_TERMINATE_LIST, - 0, - PortList, - DdiList +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + DESCRIPTOR_TERMINATE_LIST, + 0, + PortList, + DdiList }; /*---------------------------------------------------------------------------------------*/ @@ -127,10 +127,8 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; - VOID *KabiniPcieComplexListPtr; - VOID *KabiniPciePortPtr; - VOID *KabiniPcieDdiPtr; + AGESA_STATUS Status; + PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; ALLOCATE_HEAP_PARAMS AllocHeapParams; @@ -139,46 +137,18 @@ OemCustomizeInitEarly ( /* */ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ /* */ - AllocHeapParams.RequestedBufferSize = sizeof(Kabini) + sizeof(PortList) + sizeof(DdiList); + AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); if ( Status!= AGESA_SUCCESS) { - /* Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ + /* Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR */ ASSERT(FALSE); return; } - KabiniPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof(Kabini); - KabiniPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof(PortList); - KabiniPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - - LibAmdMemFill (KabiniPcieComplexListPtr, - 0, - sizeof (Kabini), - &InitEarly->StdHeader); - - LibAmdMemFill (KabiniPciePortPtr, - 0, - sizeof (PortList), - &InitEarly->StdHeader); - - LibAmdMemFill (KabiniPcieDdiPtr, - 0, - sizeof (DdiList), - &InitEarly->StdHeader); - - LibAmdMemCopy (KabiniPcieComplexListPtr, &Kabini, sizeof (Kabini), &InitEarly->StdHeader); - LibAmdMemCopy (KabiniPciePortPtr, &PortList[0], sizeof (PortList), &InitEarly->StdHeader); - LibAmdMemCopy (KabiniPcieDdiPtr, &DdiList[0], sizeof (DdiList), &InitEarly->StdHeader); - - ((PCIe_COMPLEX_DESCRIPTOR*)KabiniPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)KabiniPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)KabiniPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)KabiniPcieDdiPtr; - - InitEarly->GnbConfig.PcieComplexList = KabiniPcieComplexListPtr; + PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); + InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; }

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Patch set updated for coreboot: e23c74d AMD Olive Hill: Remove default VBIOS vendor/device ID
by Bruce Griffith 26 Jul '13

26 Jul '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3816 -gerrit commit e23c74d5fb44042668d58a04f63048852a350e1e Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Mon Jul 8 11:33:45 2013 -0600 AMD Olive Hill: Remove default VBIOS vendor/device ID The VBIOS device ID is set by processor family using the map_oprom_vendev() function in the northbridge code. There is rarely a reason why this should be overridden by the mainboard. Since Kabini includes a default VBIOS vendor/device ID in the northbridge Kconfig code, remove the setting from the Olive Hill mainboard settings. Change-Id: Icd69155f5b51105d564dd82c89e4bb54a6118a82 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/olivehill/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 085dc7a..adb5d81 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -93,10 +93,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config VGA_BIOS_ID - string - default "1002,9832" - config HUDSON_LEGACY_FREE bool default y

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Patch set updated for coreboot: 18917ce AMD Olive Hill: Change SB800 references to Yangtze
by Bruce Griffith 26 Jul '13

26 Jul '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3815 -gerrit commit 18917ce03c577caf320b93bd9462fb5e291578e6 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Sun Jul 7 02:04:16 2013 -0600 AMD Olive Hill: Change SB800 references to Yangtze Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/olivehill/Kconfig | 4 +++ src/mainboard/amd/olivehill/get_bus_conf.c | 30 +++++++++---------- src/mainboard/amd/olivehill/irq_tables.c | 10 +++---- src/mainboard/amd/olivehill/mptable.c | 48 +++++++++++++++--------------- src/mainboard/amd/olivehill/romstage.c | 2 +- 5 files changed, 49 insertions(+), 45 deletions(-) diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 141da33..085dc7a 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -97,6 +97,10 @@ config VGA_BIOS_ID string default "1002,9832" +config HUDSON_LEGACY_FREE + bool + default y + config WARNINGS_ARE_ERRORS bool default n diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index fca2625..0d379d5 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -30,8 +30,8 @@ * and acpi_tables busnum is default. */ u8 bus_isa; -u8 bus_sb800[3]; -u32 apicid_sb800; +u8 bus_yangtze[3]; +u32 apicid_yangtze; /* * Here you only need to set value in pci1234 for HT-IO that could be installed or not @@ -43,7 +43,7 @@ u32 pci1234x[] = { }; u32 bus_type[256]; -u32 sbdn_sb800; +u32 sbdn_yangtze; static u32 get_bus_conf_done = 0; @@ -98,10 +98,10 @@ void get_bus_conf(void) pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - sbdn_sb800 = 0; + sbdn_yangtze = 0; for (i = 0; i < 3; i++) { - bus_sb800[i] = 0; + bus_yangtze[i] = 0; } for (i = 0; i < 256; i++) { @@ -110,34 +110,34 @@ void get_bus_conf(void) bus_type[0] = 1; /* pci */ - // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; + // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; - /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + /* yangtze */ + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); if (dev) { - bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - for (j = bus_sb800[1]; j < bus_isa; j++) + for (j = bus_yangtze[1]; j < bus_isa; j++) bus_type[j] = 1; } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); if (dev) { - bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; } } - for (j = bus_sb800[2]; j < bus_isa; j++) + for (j = bus_yangtze[2]; j < bus_isa; j++) bus_type[j] = 1; /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; - apicid_sb800 = apicid_base; + apicid_yangtze = apicid_base; } diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index 3bcd3fb..c7f2cce 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -44,8 +44,8 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, } extern u8 bus_isa; -extern u8 bus_sb800[2]; -extern unsigned long sbdn_sb800; +extern u8 bus_yangtze[2]; +extern unsigned long sbdn_yangtze; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -72,8 +72,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = bus_yangtze[0]; + pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4; pirq->exclusive_irqs = 0; @@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 7db7160..118f860 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -30,11 +30,11 @@ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS -extern u8 bus_sb800[3]; +extern u8 bus_yangtze[3]; extern u32 bus_type[256]; -extern u32 sbdn_sb800; -extern u32 apicid_sb800; +extern u32 sbdn_yangtze; +extern u32 apicid_yangtze; u8 picr_data[0x54] = { 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, @@ -103,10 +103,10 @@ static void *smp_write_config_table(void *v) /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); - apicid_sb800 = IO_APIC_ID; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + apicid_yangtze = IO_APIC_ID; + smp_write_ioapic(mc, apicid_yangtze, 0x21, dword); - smp_write_ioapic(mc, apicid_sb800+1, 0x21, 0xFEC20000); + smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000); /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { outb(byte, 0xC00); @@ -160,13 +160,13 @@ static void *smp_write_config_table(void *v) /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -195,26 +195,26 @@ static void *smp_write_config_table(void *v) /* PCI slots */ /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14); + PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15); + PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16); + PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15); + PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16); + PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17); + PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16); + PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17); + PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14); + PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12); + PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13); + PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index e74c7f2..f4906da 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39);

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Patch set updated for coreboot: 1622186 AMD Olive Hill: Enable HDMI audio setting in build options
by Bruce Griffith 26 Jul '13

26 Jul '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3814 -gerrit commit 1622186a2d4530f53e51c4af31ae46ab634ed110 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed Jul 10 01:26:26 2013 -0600 AMD Olive Hill: Enable HDMI audio setting in build options Change-Id: Ifc180e6fcd594dbedc2512ea5bef283a3ad689d3 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/olivehill/buildOpts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index df5e35a..fff0a45 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -163,7 +163,7 @@ //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL #define BLDCFG_CFG_ABM_SUPPORT TRUE - +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID

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coreboot-gerrit July 2013