New patch to review for coreboot: df51dc8 intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses
Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3810
-gerrit
commit df51dc89bb88a981c3d7229b72fc4e1d71e821f9 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Jul 26 08:50:53 2013 +0300
intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO.
Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/google/stout/mainboard_smi.c | 4 ++-- src/northbridge/intel/sandybridge/finalize.c | 22 ++++++++--------- src/southbridge/intel/bd82x6x/azalia.c | 16 ++++++------- src/southbridge/intel/bd82x6x/finalize.c | 8 +++---- src/southbridge/intel/bd82x6x/me.c | 10 ++++---- src/southbridge/intel/bd82x6x/me_8.x.c | 8 +++---- src/southbridge/intel/bd82x6x/pcie.c | 18 +++++++------- src/southbridge/intel/bd82x6x/smihandler.c | 36 ++++++++++++++-------------- src/southbridge/intel/bd82x6x/spi.c | 12 +++++----- 9 files changed, 67 insertions(+), 67 deletions(-)
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 8b37da3..0f2ecd5 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -102,10 +102,10 @@ void mainboard_smi_sleep(u8 slp_typ) * after the transition into suspend. */ if (smm_get_gnvs()->xhci) { - u32 reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74); + u32 reg32 = pci_read_config32(PCH_XHCI_DEV, 0x74); reg32 &= ~(1 << 8); /* disable PME */ reg32 |= (1 << 15); /* clear PME status */ - pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32); + pci_write_config32(PCH_XHCI_DEV, 0x74, reg32); } }
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 9b41cfa..b0a8d6a 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -26,17 +26,17 @@
void intel_sandybridge_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 2d854a4..9fcb770 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -250,26 +250,26 @@ static void azalia_init(struct device *dev) printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) { - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 24); // 2 << 24 for server reg32 |= RCBA32(0x2030) & 0xfe; - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32);
- reg16 = pci_mmio_read_config16(dev, 0x78); + reg16 = pci_read_config16(dev, 0x78); reg16 |= (1 << 11); - pci_mmio_write_config16(dev, 0x78, reg16); + pci_write_config16(dev, 0x78, reg16); } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
- reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= ~0xfe; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32);
// Set VCi enable bit - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32);
// Enable HDMI codec: reg32 = pci_read_config32(dev, 0xc4); diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 76e75c8..ad2586c 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -57,15 +57,15 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); - pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, - pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); + pci_write_config32(PCI_DEV(0, 27, 0), 0x74, + pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 626e61a..17be63b 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -502,14 +502,14 @@ static void intel_me7_finalize_smm(void) u32 reg32;
mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
/* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == 0xfffffff0) return;
/* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, ®32, sizeof(u32));
/* Abort and leave device alone if not normal mode */ @@ -522,10 +522,10 @@ static void intel_me7_finalize_smm(void) mkhi_end_of_post();
/* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -533,7 +533,7 @@ static void intel_me7_finalize_smm(void)
void intel_me_finalize_smm(void) { - u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); switch (did) { case 0x1c3a8086: intel_me7_finalize_smm(); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 72175d8..92f132d 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -497,14 +497,14 @@ void intel_me8_finalize_smm(void) u32 reg32;
mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
/* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == 0xfffffff0) return;
/* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, ®32, sizeof(u32));
/* Abort and leave device alone if not normal mode */ @@ -517,10 +517,10 @@ void intel_me8_finalize_smm(void) mkhi_end_of_post();
/* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 2e3e465..fadb43f 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -139,30 +139,30 @@ static void pch_pcie_pm_late(struct device *dev) u32 reg32;
/* Set 0x314 = 0x743a361b */ - pci_mmio_write_config32(dev, 0x314, 0x743a361b); + pci_write_config32(dev, 0x314, 0x743a361b);
/* Set 0x318[31:16] = 0x1414 */ - reg32 = pci_mmio_read_config32(dev, 0x318); + reg32 = pci_read_config32(dev, 0x318); reg32 &= 0x0000ffff; reg32 |= 0x14140000; - pci_mmio_write_config32(dev, 0x318, reg32); + pci_write_config32(dev, 0x318, reg32);
/* Set 0x324[5] = 1 */ - reg32 = pci_mmio_read_config32(dev, 0x324); + reg32 = pci_read_config32(dev, 0x324); reg32 |= (1 << 5); - pci_mmio_write_config32(dev, 0x324, reg32); + pci_write_config32(dev, 0x324, reg32);
/* Set 0x330[7:0] = 0x40 */ - reg32 = pci_mmio_read_config32(dev, 0x330); + reg32 = pci_read_config32(dev, 0x330); reg32 &= ~(0xff); reg32 |= 0x40; - pci_mmio_write_config32(dev, 0x330, reg32); + pci_write_config32(dev, 0x330, reg32);
/* Set 0x33C[24:0] = 0x854c74 */ - reg32 = pci_mmio_read_config32(dev, 0x33c); + reg32 = pci_read_config32(dev, 0x33c); reg32 &= 0xff000000; reg32 |= 0x00854c74; - pci_mmio_write_config32(dev, 0x33c, reg32); + pci_write_config32(dev, 0x33c, reg32);
/* No IO-APIC, Disable EOI forwarding */ reg32 = pci_read_config32(dev, 0xd4); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 9588703..491f997 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -64,7 +64,7 @@ static u32 tseg_base = 0; u32 smi_get_tseg_base(void) { if (!tseg_base) - tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; + tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; return tseg_base; } void tseg_relocate(void **ptr) @@ -301,7 +301,7 @@ static void southbridge_gate_memory_reset(void) u32 reg32; u16 gpiobase;
- gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; + gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; if (!gpiobase) return;
@@ -333,15 +333,15 @@ static void xhci_sleep(u8 slp_typ) switch (slp_typ) { case SLP_TYP_S3: case SLP_TYP_S4: - reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 &= ~0x03UL; - pcie_write_config32(PCH_XHCI_DEV, 0x74, reg16); + pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
- reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
- xhci_bar = pcie_read_config32(PCH_XHCI_DEV, + xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL;
if ((xhci_bar + 0x4C0) & 1) @@ -353,19 +353,19 @@ static void xhci_sleep(u8 slp_typ) if ((xhci_bar + 0x4F0) & 1) pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
- reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
- reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 |= 0x03; - pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16); + pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); break;
case SLP_TYP_S5: - reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74); + reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 |= ((1 << 8) | 0x03); - pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16); + pci_write_config16(PCH_XHCI_DEV, 0x74, reg16); break; } } @@ -436,13 +436,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) { reg8 &= ~1; } else { reg8 |= 1; } - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -672,7 +672,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl;
- bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -686,7 +686,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -813,7 +813,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav u32 smi_sts;
/* Update global variable pmbase */ - pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 320cf8c..ec5d7de 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -36,17 +36,17 @@ #ifdef __SMM__ #include <arch/pci_mmio_cfg.h> #define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pcie_read_config8(dev, reg) + *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ - *(targ) = pcie_read_config16(dev, reg) + *(targ) = pci_read_config16(dev, reg) #define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pcie_read_config32(dev, reg) + *(targ) = pci_read_config32(dev, reg) #define pci_write_config_byte(dev, reg, val)\ - pcie_write_config8(dev, reg, val) + pci_write_config8(dev, reg, val) #define pci_write_config_word(dev, reg, val)\ - pcie_write_config16(dev, reg, val) + pci_write_config16(dev, reg, val) #define pci_write_config_dword(dev, reg, val)\ - pcie_write_config32(dev, reg, val) + pci_write_config32(dev, reg, val) #else /* !__SMM__ */ #include <device/device.h> #include <device/pci.h>
-
Kyösti Mälkki