coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 32ab283 cpu: Add CPU microcode file to cbfs with 16-byte alignment
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 32ab283b1086ef53fadcd4be92df6e41c5d06438 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jun 11 16:36:37 2013 -0500 cpu: Add CPU microcode file to cbfs with 16-byte alignment On x86 there is a 16-byte alignment requirement for the addresses containing the CPU microcode. The cbfs files containing the microcode are used in memory-mapped fashion when loading new mircocode. Therefore, the data payload's address/offset of a cbfs file in flash dictates the resulting alignment. Fix this by processing the CPU microcode cbfs file separately as it uses $(CBFSTOOL) to find the proper location within the provided rom image. Change-Id: Ia200d62dbcf7ff1fa59598654718a0b7e178ca4c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3663 for details. -gerrit

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Patch merged into coreboot/master: e221aad ec: Reserve correct ioport regions for Chrome OS EC to use
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit e221aad27fb860f31be089180d920df9d2243ae2 Author: Bill Richardson <wfrichar(a)chromium.org> Date: Wed Jun 12 10:50:41 2013 -0700 ec: Reserve correct ioport regions for Chrome OS EC to use The LPC-based ChromeOS EC uses several ioport regions to communicate with the AP. In order for the new unified userspace access method to work, we need them to be reserved by the BIOS. Before /proc/ioports shows: 0800-0803 0804-08ff We'd like just a single 256-byte region at 0x800, but ASL can't handle that. So this will work: 0800-087f 0880-08ff Change-Id: I3f8060bff32d3a49f1488b26830ae26b83dab79d Signed-off-by: Bill Richardson <wfrichar(a)chromium.org> Reviewed-on: http://review.coreboot.org/3746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3746 for details. -gerrit

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Patch merged into coreboot/master: a86c33a google/snow: Don't spew output with GPIO config
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit a86c33a31a6c3faa91df12ee3e592a98f5702bc6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 17 10:34:25 2013 -0700 google/snow: Don't spew output with GPIO config There are hundreds of GPIOs on the Exynos5250. Don't always print all of them per default. Change-Id: Ie349f2a4117883302b743027ed13cc9705b804f8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3661 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3661 for details. -gerrit

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Patch merged into coreboot/master: 6d16c43 slippy/falco/peppy: Enable SERIRQ continuous mode
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 6d16c437fc2609a4521de3b7e78a07b4155ceaba Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 4 10:07:15 2013 -0700 slippy/falco/peppy: Enable SERIRQ continuous mode The Chrome EC still does not tolerate SERIRQ in quiet mode and so the keyboard does not work properly. Change-Id: I9ab052187c9926ce0e2c86b86dfe987dd6564c1b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/3745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3745 for details. -gerrit

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Patch merged into coreboot/master: 7cced0d ec: Add romstage function for checking and rebooting EC
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 7cced0d20e44c1bbcd0b5d4aced53c682fcd23fc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 4 10:03:34 2013 -0700 ec: Add romstage function for checking and rebooting EC Now that we are executing VbInit() in coreboot we can end up in a situation where the recovery reason is consumed during VbInit (end of romstage) and then the EC is rebooted to RO during ramstage EC init, thereby losing the recovery reason. Two possiblities are to remove the EC check+reboot from ramstage and let it happen in depthcharge. This however means that the system has to boot all the way into depthcharge and then reboot the EC and the system again. Instead if we do a check in romstage before VbInit() is called then we can reboot the EC into RO early and avoid booting all the way to depthcharge first. This change adds a ramstage version the EC init function and calls it from the shared romstage code immediately after the PCH decode windows are setup. Change-Id: I30d2a0c7131b8e4ec30c63eea36944ec111a8fba Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/3744 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3744 for details. -gerrit

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Patch merged into coreboot/master: 433432b chrome ec: Update EC header from EC repository
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 433432b6544fc57c7998a66aaa34c45609e4fc8c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 3 10:38:22 2013 -0700 chrome ec: Update EC header from EC repository - Updated ec_commands.h is copied in directly from EC repo - Removed "old" interface and update resources for "new" interface - Updated temp sensor constants and added "not calibrated" - Update mainboards to remove check for EC_SWITCH_KEYBOARD_RECOVERY Change-Id: Ic93c1914f86b6f5bc224178270624ed92b5c1e15 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/3743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3743 for details. -gerrit

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Patch merged into coreboot/master: e8b08ba Drop ELF remains from boot code
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit e8b08ba47c8b17480bd94eef7dc8a47629191957 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 24 15:09:36 2013 -0700 Drop ELF remains from boot code This stuff is not used, so let's drop it. Change-Id: I671a5e87855b4c59622cafacdefe466ab3d70143 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3660 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3660 for details. -gerrit

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Patch merged into coreboot/master: 93ce3b3 ARMv7: flatten arch/armv7 source tree
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 93ce3b3a28dc0aad0bb501072bc7fc31e9cd6ce2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 24 14:38:48 2013 -0700 ARMv7: flatten arch/armv7 source tree With only 19 source files it doesn't make a whole lot of sense to create sub directories in arch/armv7, especially since the files were distributed somewhat randomly. Change-Id: I029c7848e915edf1737e1c401c034837c95d179d Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3659 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3659 for details. -gerrit

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Patch merged into coreboot/master: 5420e09 exynos5420: Replace the 5250 clock logic with 5420.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 5420e0913144e3abbd0f36dbfbc0bcbe8f052e7b Author: Gabe Black <gabeblack(a)google.com> Date: Fri May 17 11:29:22 2013 -0700 exynos5420: Replace the 5250 clock logic with 5420. The new code is stolen from U-Boot with little or no understanding of how it works. Change-Id: I3de7d25174072f6068d9d4fdaa308c0462296737 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3658 for details. -gerrit

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Patch merged into coreboot/master: 99ed2a8 exynos5420: Make the ps_hold_setup function public.
by gerrit＠coreboot.org 10 Jul '13

10 Jul '13

the following patch was just integrated into master: commit 99ed2a83b5ae69d134333deaa7d326b9c0aa08b7 Author: Gabe Black <gabeblack(a)google.com> Date: Fri May 17 11:17:15 2013 -0700 exynos5420: Make the ps_hold_setup function public. This function had been declared in a public header file, but was marked static when actually defined. Change-Id: Ia551a5a12e7dbaf7bc00861e085695145ab7b91a Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3657 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3657 for details. -gerrit

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coreboot-gerrit July 2013