coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

1 participants
593 discussions

Patch set updated for coreboot: 7aa9501 ASUS F2A85-M: Correct and clean up PCIe config
by Paul Menzel 16 May '13

16 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3194 -gerrit commit 7aa9501012decdb54a794037f149ad5b0948da43 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat May 4 00:08:34 2013 +0200 ASUS F2A85-M: Correct and clean up PCIe config Assign the lanes correctly to the physical slots on the motherboard in `PlatformGnbPcie.c`. • UMI is connected to SB via 4x PCIe bridge 8. • The blue x16 slot is not shared with DDI and is routed through PCIe bridge 2. • The black x8 slot is in fact a x4 slot and uses all 4 GPPs from the CPU. • Assume that DDI is on out-of-PCIe-band lanes. Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 66 ++++------------------ .../asus/f2a85-m/PlatformGnbPcieComplex.h | 40 ------------- 2 files changed, 10 insertions(+), 96 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index fff40a8..8ff64c6 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -72,57 +72,32 @@ */ PCIe_PORT_DESCRIPTOR PortList [] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ { 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - - /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1, TODO: Disabled. */ - { - 0, /* Descriptor flags */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - - /* PCIe port, Lanes 7, PCI Device Number 7, LAN , TODO: not the last entry.*/ - { - 0, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) - }, - -#if 1 - /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ { DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, -#endif }; +/* + * It is not known, if the setup is complete. + * + * Tested and works: VGA/DVI + * Untested: HDMI + */ PCIe_DDI_DESCRIPTOR DdiList [] = { // DP0 to HDMI0/DP { @@ -139,29 +114,9 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { // DP2 to HDMI1/DP { 0, -// PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 32, 38), PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) }, - // GFX Lane 15-12 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) - }, - // GFX Lane 11-8 - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) - }, - // GFX Lane 7-4 - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) - } }; PCIe_COMPLEX_DESCRIPTOR Trinity = { @@ -205,7 +160,6 @@ OemCustomizeInitEarly ( // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); - AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h index 3f14805..b3c69cf 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h @@ -24,46 +24,6 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly

1 0

Patch set updated for coreboot: 8d5d8a8 AMD Llano, Brazos boards: Use `sizeof(var)` to get its size
by Paul Menzel 16 May '13

16 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3248 -gerrit commit 8d5d8a83236fdf8a80388b49a00287378b7c48c3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue May 14 10:06:47 2013 +0200 AMD Llano, Brazos boards: Use `sizeof(var)` to get its size Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Rudolf Marek’s patch »ASUS F2A85-M: Correct and clean up PCIe config« [1] contains the same change and is ported over. In the commit message Rudolf makes the following comment. »Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR?« [1] http://review.coreboot.org/#/c/3194/ Change-Id: I123031b3819a10c9c85577fdca96c70d9c992e87 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 21 ++++++++++----------- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/amd/south_station/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/amd/torpedo/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/amd/union_station/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 20 +++++++++----------- .../lippert/frontrunner-af/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/lippert/toucan-af/PlatformGnbPcie.c | 20 +++++++++----------- 8 files changed, 73 insertions(+), 88 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index c1fc77f..a201a0f 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -108,9 +108,7 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 4 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -123,30 +121,31 @@ OemCustomizeInitEarly ( BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 4; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 4, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 4, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index fa909d2..3cd69f1 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -117,9 +117,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -132,30 +130,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index d0fd71b..a8511ea 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -116,9 +116,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -131,30 +129,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index a42d056..1639393 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -126,9 +126,7 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR) * 6; + AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -141,30 +139,30 @@ OemCustomizeInitEarly ( LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Llano); LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof(PortList); LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (LlanoPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Llano), &InitEarly->StdHeader); LibAmdMemFill (LlanoPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (LlanoPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr; diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index 98dd995..829b6c9 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -118,9 +118,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -133,30 +131,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index ee25ac9..50a8db9 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -118,9 +118,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -133,30 +131,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c index 9bd9958..9724be1 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c @@ -117,9 +117,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -132,30 +130,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c index 772ea53..61318b1 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c @@ -117,9 +117,7 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 5 + - sizeof (PCIe_DDI_DESCRIPTOR) * 2; + AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -132,30 +130,30 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Brazos); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 2, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;

1 0

Patch set updated for coreboot: f643680 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
by Paul Menzel 16 May '13

16 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3250 -gerrit commit f643680c3ea3ccf0cfefdb61e5d63fe9c4642aeb Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed May 15 23:31:56 2013 -0600 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer The following commit commit 05f3b117dd44776ed17bc57318f260766039b7e8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue May 14 09:28:26 2013 +0200 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer Reviewed-on: http://review.coreboot.org/3246 changed one calculation for the size of the array PortList[] to reflect only four elements, but neglected three additional calculations of the size of the same table. Correct that by setting the size for four array elements in all four calculations. [1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbP… Change-Id: Ib66b7b2b388d847888663e9eb6d1c8c9d50b9939 Reported-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index 20351ac..c1fc77f 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -126,7 +126,7 @@ OemCustomizeInitEarly ( AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 4; BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, @@ -136,7 +136,7 @@ OemCustomizeInitEarly ( LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof (PCIe_PORT_DESCRIPTOR) * 4, &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, @@ -145,7 +145,7 @@ OemCustomizeInitEarly ( &InitEarly->StdHeader); LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 4, &InitEarly->StdHeader); LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);

1 0

New patch to review for coreboot: 0f232d8 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
by Bruce Griffith 16 May '13

16 May '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3250 -gerrit commit 0f232d8691d040232fed5c5490f96efefd48e58b Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed May 15 23:31:56 2013 -0600 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer The following commit commit 05f3b117dd44776ed17bc57318f260766039b7e8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue May 14 09:28:26 2013 +0200 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer Reviewed-on: http://review.coreboot.org/3246 Changed one calculation for the size of the array PortList[] to reflect only four elements, but neglected three additional calculations of the size of the same table. Correct that by setting the size for four array elements in all four calculations. [1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbP… Change-Id: Ib66b7b2b388d847888663e9eb6d1c8c9d50b9939 Reported-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index 20351ac..c1fc77f 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -126,7 +126,7 @@ OemCustomizeInitEarly ( AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5; + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 4; BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (BrazosPcieComplexListPtr, @@ -136,7 +136,7 @@ OemCustomizeInitEarly ( LibAmdMemFill (BrazosPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 5, + sizeof (PCIe_PORT_DESCRIPTOR) * 4, &InitEarly->StdHeader); LibAmdMemFill (BrazosPcieDdiPtr, @@ -145,7 +145,7 @@ OemCustomizeInitEarly ( &InitEarly->StdHeader); LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader); + LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 4, &InitEarly->StdHeader); LibAmdMemCopy (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);

1 0

Patch merged into coreboot/master: 05f3b11 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
by gerrit＠coreboot.org 16 May '13

16 May '13

the following patch was just integrated into master: commit 05f3b117dd44776ed17bc57318f260766039b7e8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue May 14 09:28:26 2013 +0200 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer The following commit commit d0790694b0a66353e5531715648ddaa1a6d577cb Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Jan 19 13:18:37 2012 +0800 Inagua: Inagua GNB ddi lanes and pcie lanes config update Reviewed-on: http://review.coreboot.org/544 assigns lanes 4 and 5 to PCI device number 4, but does not adapt the rest of the code. After the commit above, the array `PortList []` only has four elements, but the buffer size `AllocHeapParams.RequestedBufferSize` is set to a size as it still has five elements. Correct that by setting the size for four array elements. [1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbP… Change-Id: I3ff07f308ffd417d2bf73117eda9da2a1a05f199 Reported-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3246 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> See http://review.coreboot.org/3246 for details. -gerrit

1 0

Patch merged into coreboot/master: 5b54d35 haswell: enable cache-as-ram migration
by gerrit＠coreboot.org 16 May '13

16 May '13

the following patch was just integrated into master: commit 5b54d353aa89685c1cde0d6254a9899cf327a712 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:51:43 2013 -0500 haswell: enable cache-as-ram migration The haswell code allows for vboot ramstage verification. However, that code path relies on accessing global cache-as-ram variables after cache-as-ram is torn down. In order to avoid that situation enable cache-as-ram migration. cbmemc_reinit() no longer needs to be called from romstage because it is invoked automatically by the cache-as-ram migration infrastructure. Change-Id: I08998dca579c167699030e1e24ea0af8802c0758 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3236 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3236 for details. -gerrit

1 0

Patch merged into coreboot/master: 2ad6bd2 cbmem console: use cache-as-ram API and cleanup
by gerrit＠coreboot.org 16 May '13

16 May '13

the following patch was just integrated into master: commit 2ad6bd23a7ebcaf593f717db9c356284237ed639 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:45:37 2013 -0500 cbmem console: use cache-as-ram API and cleanup Allow for automatic cache-as-ram migration for the cbmem console. The code was refactored in the thought of making it easier to read. The #ifdefs still exist, but they are no longer sprinkled throughout the code. The cbmem_console_p variable now exists globally in both romstage and ramstage. However, the cbmem_console_p is referenced using the cache-as-ram API. When cbmem is initialized the console is automatically copied over by calling cbmemc_reinit() through a callback. Change-Id: I9f4a64e33c58b8b7318db27942e37c13804e6f2c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3235 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3235 for details. -gerrit

1 0

Patch merged into coreboot/master: 677e155 chromeos: use cache-as-ram migration API for vbnv
by gerrit＠coreboot.org 16 May '13

16 May '13

the following patch was just integrated into master: commit 677e1558c32d1c88ade486e5ac42e60a3da1fdcf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:42:14 2013 -0500 chromeos: use cache-as-ram migration API for vbnv It's possible that the vbnv global variables may be accessed in romstage after cache-as-ram is torn down. Therefore use the cache-as-ram migration API. Wrappers were written to wrap the API to keep the existing code as close as possible. Change-Id: Ia1d8932f98e00def0a44444a1ead0018a59d3d98 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3234 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3234 for details. -gerrit

1 0

Patch merged into coreboot/master: cb997d3 pc80/tpm: allow for cache-as-ram migration
by gerrit＠coreboot.org 16 May '13

16 May '13

the following patch was just integrated into master: commit cb997d3710900d5950d244edd607e25bb45ea962 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:40:56 2013 -0500 pc80/tpm: allow for cache-as-ram migration As the TPM driver can be accessed in romstage after cache-as-ram is torn down use the cache-as-ram migration API to dynamically determine the global variable address. Change-Id: I149d7c130bc3677ed52282095670c07a76c34439 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3233 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3233 for details. -gerrit

1 0

Patch merged into coreboot/master: 716738a x86: add cache-as-ram migration option
by gerrit＠coreboot.org 16 May '13

16 May '13

the following patch was just integrated into master: commit 716738a6b84535f731ee9749f161505945eab93c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:33:32 2013 -0500 x86: add cache-as-ram migration option There are some boards that do a significant amount of work after cache-as-ram is torn down but before ramstage is loaded. For example, using vboot to verify the ramstage is one such operation. However, there are pieces of code that are executed that reference global variables that are linked in the cache-as-ram region. If those variables are referenced after cache-as-ram is torn down then the values observed will most likely be incorrect. Therefore provide a Kconfig option to select cache-as-ram migration to memory using cbmem. This option is named CAR_MIGRATION. When enabled, the address of cache-as-ram variables may be obtained dynamically. Additionally, when cache-as-ram migration occurs the cache-as-ram data region for global variables is copied into cbmem. There are also automatic callbacks for other modules to perform their own migration, if necessary. Change-Id: I2e77219647c2bd2b1aa845b262be3b2543f1fcb7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/3232 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3232 for details. -gerrit

1 0

← Newer
1
...
24
25
26
27
28
29
30
...
60
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2013