coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 36dd261 Lenovo X60: Add int15 handler
by Denis Carikli 21 May '13

21 May '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3265 -gerrit commit 36dd26103939e6d2a731d58e94d4e9a58b368895 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue May 21 03:13:46 2013 +0200 Lenovo X60: Add int15 handler Without that commit, with CONFIG_PCI_OPTION_ROM_RUN_YABEL, The VGA option rom doesn't init the right display, and we see nothing either on the external display. This commit is based on the code of mainboard.c in src/mainboard/roda/rk886ex. Change-Id: I8457aaf0503e0efdf0fcba9ff5e8a07ac04c5ca6 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/mainboard.c | 61 ++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 3cb28ff..7d29bc1 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -36,6 +36,11 @@ #include "dock.h" #include <arch/x86/include/arch/acpigen.h> +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN +#include <arch/interrupt.h> +#include <x86emu/x86emu.h> +#endif + int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, unsigned int gfx); @@ -45,6 +50,56 @@ static acpi_cstate_t cst_entries[] = { { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + /* This int15 handler is Intel IGD. specific. Other chipsets need other + * handlers. The right way to do this is to move this handler code into + * the mainboard or northbridge code. + * TODO: completely move to mainboards / chipsets. + */ + u8 display_id; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f40: /* Boot Panel Type */ + /* LCD panel type is SIO GPIO40-43 */ + // display_id = inb(0x60f) & 0x0f; + display_id = 3; + // M.x86.R_AX = 0x015f; // Supported but failed + X86_AX = 0x005f; // Success + X86_CL = display_id; + printk(BIOS_DEBUG, "DISPLAY=%x\n", X86_CL); + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif + + + int get_cst_entries(acpi_cstate_t **entries) { *entries = cst_entries; @@ -62,6 +117,12 @@ static void mainboard_enable(device_t dev) ec_set_bit(0x03, 2); ec_write(0x0c, 0x88); } + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)

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Patch merged into coreboot/master: 883b03f AMD AGESA Hudson: Include `stdint.h` and `io.h` to fix build
by gerrit＠coreboot.org 20 May '13

20 May '13

the following patch was just integrated into master: commit 883b03f3230ad032dffae9e3e053c6c1963abebc Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon May 6 15:18:57 2013 +0200 AMD AGESA Hudson: Include `stdint.h` and `io.h` to fix build Apparently the files `smbus.{h,c}`, where never used and therefore build beforehand. Needing one function in them for the ASUS F2A85-M the build fails as some headers are missing. Including the headers `stdint.h` and `io.h` fixes the following errors. […] CC southbridge/amd/agesa/hudson/smbus.romstage.o In file included from src/southbridge/amd/agesa/hudson/smbus.c:23:0: src/southbridge/amd/agesa/hudson/smbus.h:67:24: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:67:43: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:67:55: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:25: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:44: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:56: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:69: error: unknown type name 'u8' src/southbridge/amd/agesa/hudson/smbus.h:69:24: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:69:43: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:70:24: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:70:43: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:70:55: error: unknown type name 'u8' src/southbridge/amd/agesa/hudson/smbus.h:71:20: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:35: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:49: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:59: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:69: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:20: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:35: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:49: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:59: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:20: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:32: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:44: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:54: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.c: In function 'smbus_delay': src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'outb' [-Werror=implicit-function-declaration] src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'inb' [-Werror=implicit-function-declaration] […] Probably all the (AMD(?)) `smbus.{h,c}` suffer from this and should be fixed. Even better, as these function do not differ between most boards, the file should be moved out from the specific southbridge directories. [1] http://qa.coreboot.org/job/coreboot-gerrit/6168/testReport/junit/(root)/boa… Change-Id: I285101fa06a365da44fa27b688c536e614d57f50 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3202 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/3202 for details. -gerrit

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Patch merged into coreboot/master: b2cddd4 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
by gerrit＠coreboot.org 20 May '13

20 May '13

the following patch was just integrated into master: commit b2cddd4c12d99df55a1fd856cceea27372ce3f69 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun May 5 12:09:16 2013 +0200 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case Currently the code in the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So negate the predicate to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 add `southbridge/amd/agesa/hudson/smbus.c` providing the function `do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can actually be used after the needed header files are included in a previous commit. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard <david.c.hubbard+coreboot(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3200 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3200 for details. -gerrit

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Patch merged into coreboot/master: 963bed5 Make: Use unaltered object list for dependency inclusion
by gerrit＠coreboot.org 20 May '13

20 May '13

the following patch was just integrated into master: commit 963bed546f316af15bf1e4d1819388b8998ef5ec Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed May 15 11:47:51 2013 +0200 Make: Use unaltered object list for dependency inclusion It looks like the inclusion of dependency files was broken for all ramstage objects since the list of those gets processed through the ramstage-postprocess macro. Fix that by taking the unaltered list for dependency files. The output of `make printall` (look for DEPENDENCIES=) shows which dependency files will be included. See also: commit 79f9010e80a04f2e0fb0cca5759e3215dff79aff Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Nov 25 14:31:08 2012 +0100 build system: Add hook to postprocess classes (object lists) and: commit f33e395213f0516a9256f33ede4c6bba3babb0e9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Nov 25 17:10:47 2012 +0100 build system: Split linking into multiple steps Change-Id: If93b1773c5d53240f98382aab11bf7f5a4649ee8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3258 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/3258 for details. -gerrit

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Patch merged into coreboot/master: b0fb223 Drop llshell
by gerrit＠coreboot.org 20 May '13

20 May '13

the following patch was just integrated into master: commit b0fb2234be259a32325f5fc28750bd7b8aebc708 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 16 12:51:07 2013 -0700 Drop llshell This feature has not been used and was never fully integrated. In the progress of cleaning up coreboot, let's drop it. Change-Id: Ib40acdba30aef00a4a162f2b1009bf8b7db58bbb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/3251 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3251 for details. -gerrit

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New patch to review for coreboot: baf59df AMD Family 10h–14h CPUs: AGESA: Provide monotonic counter
by Paul Menzel 18 May '13

18 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3264 -gerrit commit baf59dff8899efbd953cae5790d6d8d231026f5a Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon May 13 23:36:02 2013 +0200 AMD Family 10h–14h CPUs: AGESA: Provide monotonic counter Big thanks to Rudolf for educating me on accessing indexed registers [1]. Unfortunately, the PCI access helpers seem to be not available in romstage. 1. `arch/io.h` is changed to make it compile. 2. Booting fails with `get_pbus: dev is NULL!` [2]. The question is, if the CPU root complex can be accessed that early. [1] http://www.coreboot.org/pipermail/coreboot/2013-May/075871.html [2] http://www.coreboot.org/pipermail/coreboot/2013-May/075874.html Change-Id: I7bd13512646c5defed536812087104e1491f228c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/include/arch/io.h | 2 ++ src/cpu/amd/agesa/Kconfig | 9 +++++- src/cpu/amd/agesa/Makefile.inc | 2 ++ src/cpu/amd/agesa/monotonic_timer.c | 64 +++++++++++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 29c8339..a7c62e7 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -188,6 +188,7 @@ static inline int log2f(int value) return r; } +#endif #define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ (((SEGBUS) & 0xFFF) << 20) | \ @@ -206,6 +207,7 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) +#if defined(__PRE_RAM__) || defined(__SMM__) typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index c660470..39c9ebb 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,7 +27,6 @@ config CPU_AMD_AGESA default n select TSC_SYNC_LFENCE select UDELAY_LAPIC - select LAPIC_MONOTONIC_TIMER if CPU_AMD_AGESA @@ -50,6 +49,14 @@ config UDELAY_LAPIC_FIXED_FSB int default 200 +config MONOTONIC_TIMER_REG + def_bool y + select HAVE_MONOTONIC_TIMER + help + Provide a monotonic timer using the 1 MHz BIOS Timer. + + Selecting this option means that the timer is enabled, that means, the clock rate in the BIOS Timer Control indexed register (D0F0xE4_x0130_80F1) is not 00h. + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index b5f39d6..69cfa15 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,4 +24,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_MONOTONIC_TIMER_REG) += monotonic_timer.c + cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/monotonic_timer.c b/src/cpu/amd/agesa/monotonic_timer.c new file mode 100644 index 0000000..4f96ed1 --- /dev/null +++ b/src/cpu/amd/agesa/monotonic_timer.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <timer.h> + +static struct monotonic_counter { + int initialized; + struct mono_time time; + uint32_t last_value; +} mono_counter; + +static inline uint32_t read_counter_msr(void) +{ + /* D0F0xE4_x0130_80F0 BIOS Timer + * + * This field increments once every microsecond when the timer is + * enabled. The counter rolls over and continues counting when it + * reaches FFFF_FFFFh. A write to this register causes the counter + * to reset and begin counting from the value written. */ + pci_write_config32(PCI_DEV(0, 0, 0), 0xe4, 0x013080F0); + + return pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); +} + +void timer_monotonic_get(struct mono_time *mt) +{ + uint32_t current_tick; + uint32_t usecs_elapsed; + + if (!mono_counter.initialized) { + mono_counter.last_value = read_counter_msr(); + mono_counter.initialized = 1; + } + + current_tick = read_counter_msr(); + usecs_elapsed = current_tick - mono_counter.last_value; + + /* Update current time and tick values only if a full tick occurred. */ + if (usecs_elapsed) { + mono_time_add_usecs(&mono_counter.time, usecs_elapsed); + mono_counter.last_value = current_tick; + } + + /* Save result. */ + *mt = mono_counter.time; +}

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Patch set updated for coreboot: fab4614 cpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMER
by Paul Menzel 18 May '13

18 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3172 -gerrit commit fab46149b9209522fafbc7fca5be30252134e25f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 1 16:36:56 2013 +0200 cpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMER Thanks to Aaron Durbin coreboot provides monotonic timers. Select the LAPIC monotonic timer for the AMD AGESA CPUs. The following is an excerpt from serial log of the ASRock E350M1. $ grep usec seriallog-20130502_100902.log 01.016: Root Device init 1578 usecs 01.029: CPU_CLUSTER: 0 init 112415 usecs 01.029: PCI: 00:00.0 init 3240 usecs 01.088: PCI: 00:01.0 init 104572 usecs 01.088: PCI: 00:01.1 init 1663 usecs 01.088: PCI: 00:11.0 init 1662 usecs 01.088: PCI: 00:14.0 init 1662 usecs 01.088: PCI: 00:14.3 init 8665 usecs 01.088: PCI: 00:14.4 init 1665 usecs 01.088: PCI: 00:18.0 init 1662 usecs 01.088: PCI: 00:18.1 init 1663 usecs 01.088: PCI: 00:18.2 init 1663 usecs 01.088: PCI: 00:18.3 init 1663 usecs 01.088: PCI: 00:18.4 init 1663 usecs 01.088: PCI: 00:18.5 init 1665 usecs 01.088: PCI: 00:18.6 init 1664 usecs 01.088: PCI: 00:18.7 init 1663 usecs 01.088: PNP: 002e.2 init 1576 usecs 01.088: PNP: 002e.5 init 1577 usecs 01.088: PNP: 002e.a init 1590 usecs 01.088: PNP: 002e.b init 30144 usecs 01.088: PCI: 03:00.0 init 1663 usecs So the graphics device needs around 100 ms for being initialized. The full serial log is in the Gerrit comments. Change-Id: Ia7b3012e51fcf94b0f22290cdef2b4424295ad6d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 37b376a..c660470 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,6 +27,7 @@ config CPU_AMD_AGESA default n select TSC_SYNC_LFENCE select UDELAY_LAPIC + select LAPIC_MONOTONIC_TIMER if CPU_AMD_AGESA

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New patch to review for coreboot: 0cfe13e include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other defines
by Paul Menzel 18 May '13

18 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3263 -gerrit commit 0cfe13e018a481d7506def749c8ea8f9642a9bc1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon May 13 18:22:23 2013 +0200 include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other defines Probably due to different (character) widths for a tab, sometimes only one tab was used for aligning the define `CPU_ID_EXT_FEATURES_MSR`. For the “correct” alignment, that means where a tab is eight characters, two tabs are necessary. Change it accordingly. Change-Id: I450a7796dc00b934b5a6bab8642db04a27f69f4b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/include/cpu/amd/amdfam12.h | 2 +- src/include/cpu/amd/amdfam14.h | 2 +- src/include/cpu/amd/model_10xxx_msr.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/include/cpu/amd/amdfam12.h b/src/include/cpu/amd/amdfam12.h index 5252e89..896d30c 100644 --- a/src/include/cpu/amd/amdfam12.h +++ b/src/include/cpu/amd/amdfam12.h @@ -31,7 +31,7 @@ #define BU_CFG2_MSR 0xC001102A #define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 #if defined(__PRE_RAM__) void wait_all_core0_started(void); diff --git a/src/include/cpu/amd/amdfam14.h b/src/include/cpu/amd/amdfam14.h index c39019b..d8b8843 100644 --- a/src/include/cpu/amd/amdfam14.h +++ b/src/include/cpu/amd/amdfam14.h @@ -31,7 +31,7 @@ #define BU_CFG2_MSR 0xC001102A #define CPU_ID_FEATURES_MSR 0xC0011004 -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 #if defined(__PRE_RAM__) void wait_all_core0_started(void); diff --git a/src/include/cpu/amd/model_10xxx_msr.h b/src/include/cpu/amd/model_10xxx_msr.h index 6678a4f..84f0ff5 100644 --- a/src/include/cpu/amd/model_10xxx_msr.h +++ b/src/include/cpu/amd/model_10xxx_msr.h @@ -37,6 +37,6 @@ #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_HYPER_EXT_FEATURES 0xC001100d #define LOGICAL_CPUS_NUM_MSR 0xC001100d -#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 #endif /* CPU_AMD_MODEL_10XXX_MSR_H */

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New patch to review for coreboot: fd2cbda cpu/intel/haswell/Kconfig: Intend help text with two spaces
by Paul Menzel 18 May '13

18 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3262 -gerrit commit fd2cbda060366058a2edac4f095ed0637fde26f4 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon May 13 23:06:34 2013 +0200 cpu/intel/haswell/Kconfig: Intend help text with two spaces Commit »haswell: 24MHz monotonic time implementation« (c46cc6f1) [1] added the Kconfig variable `MONOTONIC_TIMER_MSR` with a help text, but only used one space instead of the suggested two spaces for indentation. So add one space. »Lines under a "config" definition are indented with one tab, while help text is indented an additional two spaces.« [2] [1] http://review.coreboot.org/3153 [2] https://www.kernel.org/doc/Documentation/CodingStyle (Chapter 10: Kconfig configuration files) Change-Id: I39cf356bfd54c66a2f1b837c6667dcc915e41f29 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/haswell/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 4c61b2d..c352e36 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -61,6 +61,6 @@ config MONOTONIC_TIMER_MSR depends on INTEL_LYNXPOINT_LP select HAVE_MONOTONIC_TIMER help - Provide a monotonic timer using the 24MHz MSR counter. + Provide a monotonic timer using the 24MHz MSR counter. endif

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New patch to review for coreboot: fa56389 include/timer.h: Fix typo in in*iti*alize in comment
by Paul Menzel 18 May '13

18 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3261 -gerrit commit fa563896fafb149c8293668748ae16c6d6d8c00e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon May 13 23:59:20 2013 +0200 include/timer.h: Fix typo in in*iti*alize in comment Correct a typo in a comment introduced in commit »coreboot: introduce monotonic timer API« (a421791d) [1]. [1] http://review.coreboot.org/3152 Change-Id: Ia0abc5304547d419478db1ae37b5525406fa19cc Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/include/timer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/timer.h b/src/include/timer.h index c32effe..40ac367 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -111,7 +111,7 @@ static inline int rela_time_cmp(const struct rela_time *t1, return 1; } -/* Iniitalize a rela_time structure. */ +/* Initialize a rela_time structure. */ static inline struct rela_time rela_time_init_usecs(long us) { struct rela_time t;

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coreboot-gerrit May 2013