coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 3c20cdf Make: Use unaltered object list for dependency inclusion
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3258 -gerrit commit 3c20cdf566f447e5eb15817c86725b8c16477840 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed May 15 11:47:51 2013 +0200 Make: Use unaltered object list for dependency inclusion It looks like the inclusion of dependency files was broken for all ramstage objects since the list of those gets processed through the ramstage-postprocess macro. Fix that by taking the unaltered list for dependency files. See also: commit 79f9010e80a04f2e0fb0cca5759e3215dff79aff Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Nov 25 14:31:08 2012 +0100 build system: Add hook to postprocess classes (object lists) and: commit f33e395213f0516a9256f33ede4c6bba3babb0e9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Nov 25 17:10:47 2012 +0100 build system: Split linking into multiple steps Change-Id: If93b1773c5d53240f98382aab11bf7f5a4649ee8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9aafe7c..dec32e5 100644 --- a/Makefile +++ b/Makefile @@ -242,6 +242,9 @@ $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs)))) src-to-obj=$(addsuffix .$(1).o, $(basename $(patsubst src/%, $(obj)/%, $($(1)-srcs)))) $(foreach class,$(classes),$(eval $(class)-objs:=$(call src-to-obj,$(class)))) +# Save all objs before processing them (for dependency inclusion) +originalobjs:=$(foreach var, $(addsuffix -objs,$(classes)), $($(var))) + # Call post-processors if they're defined $(foreach class,$(classes),\ $(if $(value $(class)-postprocess),$(eval $(call $(class)-postprocess,$($(class)-objs))))) @@ -273,7 +276,7 @@ $(foreach class,$(classes), \ foreach-src=$(foreach file,$($(1)-srcs),$(eval $(call $(1)-objs_$(subst .,,$(suffix $(file)))_template,$(subst src/,,$(basename $(file)))))) $(eval $(foreach class,$(classes),$(call foreach-src,$(class)))) -DEPENDENCIES = $(allobjs:.o=.d) +DEPENDENCIES = $(originalobjs:.o=.d) -include $(DEPENDENCIES) printall:

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New patch to review for coreboot: 25ab0a1 intel/gm45: Add more debug output to read/write training
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3257 -gerrit commit 25ab0a15c516c79df281e6a487ed473ab8483939 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 12:28:42 2013 +0200 intel/gm45: Add more debug output to read/write training This adds debug output for the timing values of the edges found during read and write training. Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 26 +++++++++++++++++----- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 0a23901..a4ba4ef 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -56,6 +56,13 @@ typedef struct { int t; int p; } read_timing_t; +static void print_read_timing(const int msg_lvl, const char *const msg, + const int lane, const int channel, + const read_timing_t *const timing) +{ + printk(msg_lvl, "%s for byte lane %d on channel %d: %d.%d\n", + msg, lane, channel, timing->t, timing->p); +} static int normalize_read_timing(read_timing_t *const timing) { while (timing->p >= READ_TIMING_P_BOUND) { @@ -182,6 +189,7 @@ static void read_training_per_lane(const int channel, const int lane, lower.p = 0; if (read_training_find_lower(channel, lane, addresses, &lower) < 0) die("Read training failure: lower bound.\n"); + print_read_timing(BIOS_SPEW, "Lower bound", lane, channel, &lower); /*** Search upper bound. ***/ @@ -191,6 +199,7 @@ static void read_training_per_lane(const int channel, const int lane, if (read_training_find_upper(channel, lane, addresses, &upper) < 0) /* Overflow on upper edge is not fatal. */ printk(BIOS_WARNING, "Read training failure: upper bound.\n"); + print_read_timing(BIOS_SPEW, "Upper bound", lane, channel, &upper); /*** Calculate and program mean value. ***/ @@ -201,8 +210,7 @@ static void read_training_per_lane(const int channel, const int lane, lower.t = mean_p >> READ_TIMING_P_SHIFT; lower.p = mean_p & (READ_TIMING_P_BOUND - 1); program_read_timing(channel, lane, &lower); - printk(BIOS_DEBUG, "Final timings for byte lane %d on channel %d: " - "%d.%d\n", lane, channel, lower.t, lower.p); + print_read_timing(BIOS_DEBUG, "Final timings", lane, channel, &lower); } static void perform_read_training(const dimminfo_t *const dimms) { @@ -341,6 +349,13 @@ typedef struct { const int t_bound; int p; } write_timing_t; +static void print_write_timing(const int msg_lvl, const char *const msg, + const int group, const int channel, + const write_timing_t *const timing) +{ + printk(msg_lvl, "%s for group %d on channel %d: %d.%d.%d\n", + msg, group, channel, timing->f, timing->t, timing->p); +} static int normalize_write_timing(write_timing_t *const timing) { while (timing->p >= WRITE_TIMING_P_BOUND) { @@ -516,6 +531,7 @@ static void write_training_per_group(const int ch, const int group, if (write_training_find_lower(ch, group, addresses, masks, memclk1067, &lower) < 0) die("Write training failure: lower bound.\n"); + print_write_timing(BIOS_SPEW, "Lower bound", group, ch, &lower); /*** Search upper bound. ***/ @@ -527,6 +543,7 @@ static void write_training_per_group(const int ch, const int group, if (write_training_find_upper(ch, group, addresses, masks, memclk1067, &upper) < 0) printk(BIOS_WARNING, "Write training failure: upper bound.\n"); + print_write_timing(BIOS_SPEW, "Upper bound", group, ch, &upper); /*** Calculate and program mean value. ***/ @@ -540,10 +557,7 @@ static void write_training_per_group(const int ch, const int group, lower.t = (mean_p >> WRITE_TIMING_P_SHIFT) % lower.t_bound; lower.p = mean_p & (WRITE_TIMING_P_BOUND - 1); program_write_timing(ch, group, &lower, memclk1067); - - printk(BIOS_DEBUG, "Final timings for group %d" - " on channel %d: %d.%d.%d\n", - group, ch, lower.f, lower.t, lower.p); + print_write_timing(BIOS_DEBUG, "Final timings", group, ch, &lower); } static void perform_write_training(const int memclk1067, const dimminfo_t *const dimms)

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New patch to review for coreboot: baad491 intel/gm45: Handle overflows during DDR3 write training
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3256 -gerrit commit baad491d4f776d563ca0346751bce597e880fd44 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 12:15:05 2013 +0200 intel/gm45: Handle overflows during DDR3 write training We halted the machine on any overflow during the write training. However, overflows during the search for a good to bad edge are non-fatal, and should be ignored. Change-Id: I45ccbabc214e208974039246d806b0d2ca2fdc03 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 90 +++++++++++++++------- 1 file changed, 62 insertions(+), 28 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 733b087..0a23901 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -341,7 +341,7 @@ typedef struct { const int t_bound; int p; } write_timing_t; -static void normalize_write_timing(write_timing_t *const timing) +static int normalize_write_timing(write_timing_t *const timing) { while (timing->p >= WRITE_TIMING_P_BOUND) { timing->t++; @@ -359,16 +359,31 @@ static void normalize_write_timing(write_timing_t *const timing) timing->f--; timing->t += timing->t_bound; } - if ((timing->f < 0) || (timing->f >= WRITE_TIMING_F_BOUND)) - die("Timing under-/overflow during write training.\n"); + if (timing->f < 0) { + printk(BIOS_WARNING, + "Timing underflow during write training.\n"); + timing->f = 0; + timing->t = 0; + timing->p = 0; + return -1; + } else if (timing->f >= WRITE_TIMING_F_BOUND) { + printk(BIOS_WARNING, + "Timing overflow during write training.\n"); + timing->f = WRITE_TIMING_F_BOUND - 1; + timing->t = timing->t_bound - 1; + timing->p = WRITE_TIMING_P_BOUND - 1; + return -1; + } + return 0; } -static void program_write_timing(const int ch, const int group, - write_timing_t *const timing, int memclk1067) +static int program_write_timing(const int ch, const int group, + write_timing_t *const timing, int memclk1067) { /* MEM_CLOCK_1067MT? X lower/upper */ const u32 d_bounds[2][2] = { { 1, 6 }, { 2, 9 } }; - normalize_write_timing(timing); + if (normalize_write_timing(timing) < 0) + return -1; const int f = timing->f; const int t = timing->t; @@ -384,6 +399,8 @@ static void program_write_timing(const int ch, const int group, reg &= ~CxWRTy_D_MASK; reg |= CxWRTy_T(t) | CxWRTy_P(p) | CxWRTy_F(f) | d; MCHBAR32(CxWRTy_MCHBAR(ch, group)) = reg; + + return 0; } /* Returns 1 on success, 0 on failure. */ static int write_training_test(const address_bunch_t *const addresses, @@ -425,45 +442,60 @@ _bad_timing_out: return ret; } -static void write_training_find_lower(const int ch, const int group, - const address_bunch_t *const addresses, - const u32 masks[][2], const int memclk1067, - write_timing_t *const lower) +static int write_training_find_lower(const int ch, const int group, + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const lower) { program_write_timing(ch, group, lower, memclk1067); /* Coarse search for good t. */ while (!write_training_test(addresses, masks[group])) { ++lower->t; - program_write_timing(ch, group, lower, memclk1067); + if (program_write_timing(ch, group, lower, memclk1067) < 0) + return -1; } - /* Fine search for good p. */ + /* Step back, then fine search for good p. */ + if ((lower->f <= 0) && (lower->t <= 0)) + /* Can't step back, zero is good. */ + return 0; --lower->t; program_write_timing(ch, group, lower, memclk1067); while (!write_training_test(addresses, masks[group])) { ++lower->p; - program_write_timing(ch, group, lower, memclk1067); + if (program_write_timing(ch, group, lower, memclk1067) < 0) + return -1; } + + return 0; } -static void write_training_find_upper(const int ch, const int group, - const address_bunch_t *const addresses, - const u32 masks[][2], const int memclk1067, - write_timing_t *const upper) +static int write_training_find_upper(const int ch, const int group, + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const upper) { - program_write_timing(ch, group, upper, memclk1067); - if (!write_training_test(addresses, masks[group])) - die("Write training failed; limits too narrow.\n"); - /* Coarse search for good t. */ + if (program_write_timing(ch, group, upper, memclk1067) < 0) + return -1; + if (!write_training_test(addresses, masks[group])) { + printk(BIOS_WARNING, + "Write training failure; limits too narrow.\n"); + return -1; + } + /* Coarse search for bad t. */ while (write_training_test(addresses, masks[group])) { ++upper->t; - program_write_timing(ch, group, upper, memclk1067); + if (program_write_timing(ch, group, upper, memclk1067) < 0) + return -1; } - /* Fine search for good p. */ + /* Fine search for bad p. */ --upper->t; program_write_timing(ch, group, upper, memclk1067); while (write_training_test(addresses, masks[group])) { ++upper->p; - program_write_timing(ch, group, upper, memclk1067); + if (program_write_timing(ch, group, upper, memclk1067) < 0) + return -1; } + + return 0; } static void write_training_per_group(const int ch, const int group, const address_bunch_t *const addresses, @@ -481,8 +513,9 @@ static void write_training_per_group(const int ch, const int group, lower.p = (reg >> 8) & 0x7; lower.f = ((reg >> 2) & 0x3) - 1; - write_training_find_lower(ch, group, addresses, - masks, memclk1067, &lower); + if (write_training_find_lower(ch, group, addresses, + masks, memclk1067, &lower) < 0) + die("Write training failure: lower bound.\n"); /*** Search upper bound. ***/ @@ -491,8 +524,9 @@ static void write_training_per_group(const int ch, const int group, upper.p = lower.p; upper.f = lower.f; - write_training_find_upper(ch, group, addresses, - masks, memclk1067, &upper); + if (write_training_find_upper(ch, group, addresses, + masks, memclk1067, &upper) < 0) + printk(BIOS_WARNING, "Write training failure: upper bound.\n"); /*** Calculate and program mean value. ***/

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New patch to review for coreboot: 0557680 intel/gm45: Refactor DDR3 write training
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3255 -gerrit commit 055768012a10ce061860fafc4b4ba21fdd527ea8 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:58:44 2013 +0200 intel/gm45: Refactor DDR3 write training Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 85 ++++++++++++++-------- 1 file changed, 54 insertions(+), 31 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 948956a..733b087 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -425,6 +425,46 @@ _bad_timing_out: return ret; } +static void write_training_find_lower(const int ch, const int group, + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const lower) +{ + program_write_timing(ch, group, lower, memclk1067); + /* Coarse search for good t. */ + while (!write_training_test(addresses, masks[group])) { + ++lower->t; + program_write_timing(ch, group, lower, memclk1067); + } + /* Fine search for good p. */ + --lower->t; + program_write_timing(ch, group, lower, memclk1067); + while (!write_training_test(addresses, masks[group])) { + ++lower->p; + program_write_timing(ch, group, lower, memclk1067); + } +} +static void write_training_find_upper(const int ch, const int group, + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const upper) +{ + program_write_timing(ch, group, upper, memclk1067); + if (!write_training_test(addresses, masks[group])) + die("Write training failed; limits too narrow.\n"); + /* Coarse search for good t. */ + while (write_training_test(addresses, masks[group])) { + ++upper->t; + program_write_timing(ch, group, upper, memclk1067); + } + /* Fine search for good p. */ + --upper->t; + program_write_timing(ch, group, upper, memclk1067); + while (write_training_test(addresses, masks[group])) { + ++upper->p; + program_write_timing(ch, group, upper, memclk1067); + } +} static void write_training_per_group(const int ch, const int group, const address_bunch_t *const addresses, const u32 masks[][2], const int memclk1067) @@ -433,46 +473,29 @@ static void write_training_per_group(const int ch, const int group, write_timing_t lower = { 0, 0, t_bound, 0 }, upper = { 0, 0, t_bound, 0 }; - /* Search lower bound. */ + /*** Search lower bound. ***/ + + /* Start at -1f from current values. */ const u32 reg = MCHBAR32(CxWRTy_MCHBAR(ch, group)); lower.t = (reg >> 12) & 0xf; lower.p = (reg >> 8) & 0x7; lower.f = ((reg >> 2) & 0x3) - 1; - program_write_timing(ch, group, &lower, memclk1067); - /* Coarse search for good t. */ - while (!write_training_test(addresses, masks[group])) { - ++lower.t; - program_write_timing(ch, group, &lower, memclk1067); - } - /* Fine search for good p. */ - --lower.t; - program_write_timing(ch, group, &lower, memclk1067); - while (!write_training_test(addresses, masks[group])) { - ++lower.p; - program_write_timing(ch, group, &lower, memclk1067); - } - /* Search upper bound. */ + write_training_find_lower(ch, group, addresses, + masks, memclk1067, &lower); + + /*** Search upper bound. ***/ + + /* Start at lower + 3t. */ upper.t = lower.t + 3; upper.p = lower.p; upper.f = lower.f; - program_write_timing(ch, group, &upper, memclk1067); - if (!write_training_test(addresses, masks[group])) - die("Write training failed; limits too narrow.\n"); - /* Coarse search for good t. */ - while (write_training_test(addresses, masks[group])) { - ++upper.t; - program_write_timing(ch, group, &upper, memclk1067); - } - /* Fine search for good p. */ - --upper.t; - program_write_timing(ch, group, &upper, memclk1067); - while (write_training_test(addresses, masks[group])) { - ++upper.p; - program_write_timing(ch, group, &upper, memclk1067); - } - /* Calculate and program mean value. */ + write_training_find_upper(ch, group, addresses, + masks, memclk1067, &upper); + + /*** Calculate and program mean value. ***/ + lower.t += lower.f * lower.t_bound; lower.p += lower.t << WRITE_TIMING_P_SHIFT; upper.t += upper.f * upper.t_bound;

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New patch to review for coreboot: 65988b0 intel/gm45: Handle overflows during DDR3 read training
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3254 -gerrit commit 65988b06c423f402e2da07e2505c720aa40c205c Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:25:59 2013 +0200 intel/gm45: Handle overflows during DDR3 read training We halted the machine on any overflow during the read training. However, overflows during the search for a good to bad edge are non-fatal, and should be ignored. Change-Id: I77085840ade25bce955480689c84603334113d1f Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 87 +++++++++++++++------- 1 file changed, 59 insertions(+), 28 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 6936d07..948956a 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -56,7 +56,7 @@ typedef struct { int t; int p; } read_timing_t; -static void normalize_read_timing(read_timing_t *const timing) +static int normalize_read_timing(read_timing_t *const timing) { while (timing->p >= READ_TIMING_P_BOUND) { timing->t++; @@ -66,18 +66,33 @@ static void normalize_read_timing(read_timing_t *const timing) timing->t--; timing->p += READ_TIMING_P_BOUND; } - if ((timing->t < 0) || (timing->t >= READ_TIMING_T_BOUND)) - die("Timing under-/overflow during read training.\n"); + if (timing->t < 0) { + printk(BIOS_WARNING, + "Timing underflow during read training.\n"); + timing->t = 0; + timing->p = 0; + return -1; + } else if (timing->t >= READ_TIMING_T_BOUND) { + printk(BIOS_WARNING, + "Timing overflow during read training.\n"); + timing->t = READ_TIMING_T_BOUND - 1; + timing->p = READ_TIMING_P_BOUND - 1; + return -1; + } + return 0; } -static void program_read_timing(const int ch, const int lane, - read_timing_t *const timing) +static int program_read_timing(const int ch, const int lane, + read_timing_t *const timing) { - normalize_read_timing(timing); + if (normalize_read_timing(timing) < 0) + return -1; u32 reg = MCHBAR32(CxRDTy_MCHBAR(ch, lane)); reg &= ~(CxRDTy_T_MASK | CxRDTy_P_MASK); reg |= CxRDTy_T(timing->t) | CxRDTy_P(timing->p); MCHBAR32(CxRDTy_MCHBAR(ch, lane)) = reg; + + return 0; } /* Returns 1 on success, 0 on failure. */ static int read_training_test(const int channel, const int lane, @@ -99,46 +114,59 @@ static int read_training_test(const int channel, const int lane, } return 1; } -static void read_training_find_lower(const int channel, const int lane, - const address_bunch_t *const addresses, - read_timing_t *const lower) +static int read_training_find_lower(const int channel, const int lane, + const address_bunch_t *const addresses, + read_timing_t *const lower) { /* Coarse search for good t. */ program_read_timing(channel, lane, lower); while (!read_training_test(channel, lane, addresses)) { ++lower->t; - program_read_timing(channel, lane, lower); + if (program_read_timing(channel, lane, lower) < 0) + return -1; } /* Step back, then fine search for good p. */ - if (lower->t > 0) { - --lower->t; - program_read_timing(channel, lane, lower); - while (!read_training_test(channel, lane, addresses)) { - ++lower->p; - program_read_timing(channel, lane, lower); - } + if (lower->t <= 0) + /* Can't step back, zero is good. */ + return 0; + --lower->t; + program_read_timing(channel, lane, lower); + while (!read_training_test(channel, lane, addresses)) { + ++lower->p; + if (program_read_timing(channel, lane, lower) < 0) + return -1; } + + return 0; } -static void read_training_find_upper(const int channel, const int lane, - const address_bunch_t *const addresses, - read_timing_t *const upper) +static int read_training_find_upper(const int channel, const int lane, + const address_bunch_t *const addresses, + read_timing_t *const upper) { - program_read_timing(channel, lane, upper); - if (!read_training_test(channel, lane, addresses)) - die("Read training failed: limits too narrow.\n"); + if (program_read_timing(channel, lane, upper) < 0) + return -1; + if (!read_training_test(channel, lane, addresses)) { + printk(BIOS_WARNING, + "Read training failure: limits too narrow.\n"); + return -1; + } /* Coarse search for bad t. */ do { ++upper->t; - program_read_timing(channel, lane, upper); + if (program_read_timing(channel, lane, upper) < 0) + return -1; } while (read_training_test(channel, lane, addresses)); /* Fine search for bad p. */ --upper->t; program_read_timing(channel, lane, upper); while (read_training_test(channel, lane, addresses)) { ++upper->p; - program_read_timing(channel, lane, upper); + if (program_read_timing(channel, lane, upper) < 0) + return -1; } + + return 0; } static void read_training_per_lane(const int channel, const int lane, const address_bunch_t *const addresses) @@ -152,17 +180,20 @@ static void read_training_per_lane(const int channel, const int lane, /* Start at zero. */ lower.t = 0; lower.p = 0; - read_training_find_lower(channel, lane, addresses, &lower); + if (read_training_find_lower(channel, lane, addresses, &lower) < 0) + die("Read training failure: lower bound.\n"); /*** Search upper bound. ***/ /* Start at lower + 1t. */ upper.t = lower.t + 1; upper.p = lower.p; + if (read_training_find_upper(channel, lane, addresses, &upper) < 0) + /* Overflow on upper edge is not fatal. */ + printk(BIOS_WARNING, "Read training failure: upper bound.\n"); - read_training_find_upper(channel, lane, addresses, &upper); + /*** Calculate and program mean value. ***/ - /* Calculate and program mean value. */ lower.p += lower.t << READ_TIMING_P_SHIFT; upper.p += upper.t << READ_TIMING_P_SHIFT; const int mean_p = (lower.p + upper.p) >> 1;

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New patch to review for coreboot: 0ba8715 intel/gm45: Refactor DDR3 read training
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3253 -gerrit commit 0ba8715f4deebfed37fa4fb9ffd5d566b82c60ef Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:43:03 2013 +0200 intel/gm45: Refactor DDR3 read training Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- .../intel/gm45/raminit_read_write_training.c | 74 ++++++++++++++-------- 1 file changed, 46 insertions(+), 28 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 8c8e66a..6936d07 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -99,50 +99,68 @@ static int read_training_test(const int channel, const int lane, } return 1; } -static void read_training_per_lane(const int channel, const int lane, - const address_bunch_t *const addresses) +static void read_training_find_lower(const int channel, const int lane, + const address_bunch_t *const addresses, + read_timing_t *const lower) { - read_timing_t lower, upper; - - MCHBAR32(CxRDTy_MCHBAR(channel, lane)) |= 3 << 25; - - /* Search lower bound. */ - lower.t = 0; - lower.p = 0; - program_read_timing(channel, lane, &lower); /* Coarse search for good t. */ + program_read_timing(channel, lane, lower); while (!read_training_test(channel, lane, addresses)) { - ++lower.t; - program_read_timing(channel, lane, &lower); + ++lower->t; + program_read_timing(channel, lane, lower); } + /* Step back, then fine search for good p. */ - if (lower.t > 0) { - --lower.t; - program_read_timing(channel, lane, &lower); + if (lower->t > 0) { + --lower->t; + program_read_timing(channel, lane, lower); while (!read_training_test(channel, lane, addresses)) { - ++lower.p; - program_read_timing(channel, lane, &lower); + ++lower->p; + program_read_timing(channel, lane, lower); } } - - /* Search upper bound. */ - upper.t = lower.t + 1; - upper.p = lower.p; - program_read_timing(channel, lane, &upper); +} +static void read_training_find_upper(const int channel, const int lane, + const address_bunch_t *const addresses, + read_timing_t *const upper) +{ + program_read_timing(channel, lane, upper); if (!read_training_test(channel, lane, addresses)) die("Read training failed: limits too narrow.\n"); /* Coarse search for bad t. */ do { - ++upper.t; - program_read_timing(channel, lane, &upper); + ++upper->t; + program_read_timing(channel, lane, upper); } while (read_training_test(channel, lane, addresses)); /* Fine search for bad p. */ - --upper.t; - program_read_timing(channel, lane, &upper); + --upper->t; + program_read_timing(channel, lane, upper); while (read_training_test(channel, lane, addresses)) { - ++upper.p; - program_read_timing(channel, lane, &upper); + ++upper->p; + program_read_timing(channel, lane, upper); } +} +static void read_training_per_lane(const int channel, const int lane, + const address_bunch_t *const addresses) +{ + read_timing_t lower, upper; + + MCHBAR32(CxRDTy_MCHBAR(channel, lane)) |= 3 << 25; + + /*** Search lower bound. ***/ + + /* Start at zero. */ + lower.t = 0; + lower.p = 0; + read_training_find_lower(channel, lane, addresses, &lower); + + /*** Search upper bound. ***/ + + /* Start at lower + 1t. */ + upper.t = lower.t + 1; + upper.p = lower.p; + + read_training_find_upper(channel, lane, addresses, &upper); /* Calculate and program mean value. */ lower.p += lower.t << READ_TIMING_P_SHIFT;

1 0

New patch to review for coreboot: 8c89f3c intel/gm45: Fix interpretation of VT-d disable bit
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3252 -gerrit commit 8c89f3c1a7d8ee3066b96a45b7ce2e01e07e8dfa Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue May 14 11:02:43 2013 +0200 intel/gm45: Fix interpretation of VT-d disable bit When configuring the GTT size for the integrated graphics, the state of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is _disabled_. Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/gm45/igd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index d54ee41..0a8f21e 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -67,7 +67,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) reg16 = pci_read_config16(mch_dev, D0F0_GGC); reg16 &= 0xf00f; reg16 |= 0x0350; - if (capid & (1 << (48 - 32))) + if (!(capid & (1 << (48 - 32)))) reg16 |= 0x0800; pci_write_config16(mch_dev, D0F0_GGC, reg16);

1 0

New patch to review for coreboot: f492ecd Drop llshell
by Stefan Reinauer 16 May '13

16 May '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3251 -gerrit commit f492ecd40cedc59787d2e29e01bc9852c5b75e1e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 16 12:51:07 2013 -0700 Drop llshell This feature has not been used and was never fully integrated. In the progress of cleaning up coreboot, let's drop it. Change-Id: Ib40acdba30aef00a4a162f2b1009bf8b7db58bbb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 8 - src/arch/armv7/Makefile.inc | 4 - src/arch/x86/Makefile.inc | 4 - src/arch/x86/include/arch/llshell.h | 11 - src/arch/x86/llshell/console.inc | 340 ----------- src/arch/x86/llshell/llshell.inc | 901 ---------------------------- src/arch/x86/llshell/pci.inc | 229 ------- src/arch/x86/llshell/ramtest.inc | 127 ---- src/arch/x86/llshell/readme.coreboot | 25 - src/mainboard/iei/pm-lx-800-r11/romstage.c | 1 - src/mainboard/iei/pm-lx2-800-r10/romstage.c | 1 - src/mainboard/thomson/ip1000/romstage.c | 5 - 12 files changed, 1656 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 308deaa..f6819b4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -930,14 +930,6 @@ config DEBUG_INTEL_ME is present on Intel 6-series chipsets. endif -config LLSHELL - bool "Built-in low-level shell" - default n - help - If enabled, you will have a low level shell to examine your machine. - Put llshell() in your (romstage) code to start the shell. - See src/arch/x86/llshell/llshell.inc for details. - config TRACE bool "Trace function calls" default n diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index b726ead..2c280f4 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -149,10 +149,6 @@ ldscripts += $(src)/arch/armv7/romstage.ld crt0s += $(cpu_incs) crt0s += $(cpu_incs-y) -ifeq ($(CONFIG_LLSHELL),y) -crt0s += $(src)/arch/armv7/llshell/llshell.inc -endif - $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 62f7a3f..7f1b7b2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -197,10 +197,6 @@ endif crt0s += $(cpu_incs) crt0s += $(cpu_incs-y) -ifeq ($(CONFIG_LLSHELL),y) -crt0s += $(src)/arch/x86/llshell/llshell.inc -endif - crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc ifeq ($(CONFIG_ROMCC),y) diff --git a/src/arch/x86/include/arch/llshell.h b/src/arch/x86/include/arch/llshell.h deleted file mode 100644 index 556df7d..0000000 --- a/src/arch/x86/include/arch/llshell.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ARCH_LLSHELL__ -#define __ARCH_LLSHELL__ - - -#if CONFIG_LLSHELL -#define llshell() asm("jmp low_level_shell"); -#else -#define llshell() print_debug("LLSHELL not active.\n"); -#endif - -#endif diff --git a/src/arch/x86/llshell/console.inc b/src/arch/x86/llshell/console.inc deleted file mode 100644 index 84f62e3..0000000 --- a/src/arch/x86/llshell/console.inc +++ /dev/null @@ -1,340 +0,0 @@ - -jmp console0 - -#define __STR(X) #X -#define STR(X) __STR(X) - - -#undef STR - /* uses: ax, dx */ -#if defined(SERIAL_CONSOLE) -#define __CONSOLE_INLINE_TX_AL TTYS0_TX_AL -#else -#define __CONSOLE_INLINE_TX_AL -#endif - - /* uses: esp, ax, dx */ -#define __CONSOLE_TX_CHAR(byte) \ - mov byte, %al ; \ - CALLSP(console_tx_al) - - /* uses: ax, dx */ -#define __CONSOLE_INLINE_TX_CHAR(byte) \ - mov byte, %al ; \ - __CONSOLE_INLINE_TX_AL - - /* uses: esp, ax, edx */ -#define __CONSOLE_TX_HEX8(byte) \ - mov byte, %al ; \ - CALLSP(console_tx_hex8) - - /* uses: byte, ax, dx */ -#define __CONSOLE_INLINE_TX_HEX8(byte) \ - movb byte, %dl ; \ - shll $16, %edx ; \ - shr $4, %al ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL ; \ - shrl $16, %edx ; \ - movb %dl, %al ; \ - and $0x0f, %al ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL - - /* uses: esp, eax, ebx, dx */ -#define __CONSOLE_TX_HEX32(lword) \ - mov lword, %eax ; \ - CALLSP(console_tx_hex32) - - /* uses: eax, lword, dx */ -#define __CONSOLE_INLINE_TX_HEX32(lword) \ - mov lword, %eax ; \ - shr $28, %eax ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL ; \ - ; \ - mov lword, %eax ; \ - shr $24, %eax ; \ - and $0x0f, %al ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL ; \ - ; \ - mov lword, %eax ; \ - shr $20, %eax ; \ - and $0x0f, %al ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL ; \ - ; \ - mov lword, %eax ; \ - shr $16, %eax ; \ - and $0x0f, %al ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL ; \ - ; \ - mov lword, %eax ; \ - shr $12, %eax ; \ - and $0x0f, %al ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL ; \ - ; \ - mov lword, %eax ; \ - shr $8, %eax ; \ - and $0x0f, %al ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL ; \ - ; \ - mov lword, %eax ; \ - shr $4, %eax ; \ - and $0x0f, %al ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL ; \ - ; \ - mov lword, %eax ; \ - and $0x0f, %al ; \ - add $'0', %al ; \ - cmp $'9', %al ; \ - jle 9f ; \ - add $39, %al ; \ -9: ; \ - __CONSOLE_INLINE_TX_AL - - - /* uses: esp, ebx, ax, dx */ -#define __CONSOLE_TX_STRING(string) \ - mov string, %ebx ; \ - CALLSP(console_tx_string) - - /* uses: ebx, ax, dx */ -#define __CONSOLE_INLINE_TX_STRING(string) \ - movl string, %ebx ; \ -10: movb (%ebx), %al ; \ - incl %ebx ; \ - testb %al, %al ; \ - jz 11f ; \ - __CONSOLE_INLINE_TX_AL ; \ - jmp 10b ; \ -11: - - -#define CONSOLE_EMERG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) -#define CONSOLE_EMERG_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) -#define CONSOLE_EMERG_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) -#define CONSOLE_EMERG_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) -#define CONSOLE_EMERG_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) -#define CONSOLE_EMERG_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) -#define CONSOLE_EMERG_TX_STRING(string) __CONSOLE_TX_STRING(string) -#define CONSOLE_EMERG_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) - -#define CONSOLE_ALERT_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) -#define CONSOLE_ALERT_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) -#define CONSOLE_ALERT_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) -#define CONSOLE_ALERT_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) -#define CONSOLE_ALERT_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) -#define CONSOLE_ALERT_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) -#define CONSOLE_ALERT_TX_STRING(string) __CONSOLE_TX_STRING(string) -#define CONSOLE_ALERT_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) - -#define CONSOLE_CRIT_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) -#define CONSOLE_CRIT_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) -#define CONSOLE_CRIT_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) -#define CONSOLE_CRIT_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) -#define CONSOLE_CRIT_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) -#define CONSOLE_CRIT_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) -#define CONSOLE_CRIT_TX_STRING(string) __CONSOLE_TX_STRING(string) -#define CONSOLE_CRIT_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) - -#define CONSOLE_ERR_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) -#define CONSOLE_ERR_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) -#define CONSOLE_ERR_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) -#define CONSOLE_ERR_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) -#define CONSOLE_ERR_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) -#define CONSOLE_ERR_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) -#define CONSOLE_ERR_TX_STRING(string) __CONSOLE_TX_STRING(string) -#define CONSOLE_ERR_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) - -#define CONSOLE_WARNING_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) -#define CONSOLE_WARNING_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) -#define CONSOLE_WARNING_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) -#define CONSOLE_WARNING_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) -#define CONSOLE_WARNING_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) -#define CONSOLE_WARNING_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) -#define CONSOLE_WARNING_TX_STRING(string) __CONSOLE_TX_STRING(string) -#define CONSOLE_WARNING_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) - -#define CONSOLE_NOTICE_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) -#define CONSOLE_NOTICE_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) -#define CONSOLE_NOTICE_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) -#define CONSOLE_NOTICE_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) -#define CONSOLE_NOTICE_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) -#define CONSOLE_NOTICE_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) -#define CONSOLE_NOTICE_TX_STRING(string) __CONSOLE_TX_STRING(string) -#define CONSOLE_NOTICE_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) - -#define CONSOLE_INFO_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) -#define CONSOLE_INFO_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) -#define CONSOLE_INFO_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) -#define CONSOLE_INFO_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) -#define CONSOLE_INFO_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) -#define CONSOLE_INFO_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) -#define CONSOLE_INFO_TX_STRING(string) __CONSOLE_TX_STRING(string) -#define CONSOLE_INFO_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) - -#define CONSOLE_DEBUG_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) -#define CONSOLE_DEBUG_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) -#define CONSOLE_DEBUG_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) -#define CONSOLE_DEBUG_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) -#define CONSOLE_DEBUG_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) -#define CONSOLE_DEBUG_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) -#define CONSOLE_DEBUG_TX_STRING(string) __CONSOLE_TX_STRING(string) -#define CONSOLE_DEBUG_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) - -#define CONSOLE_SPEW_TX_CHAR(byte) __CONSOLE_TX_CHAR(byte) -#define CONSOLE_SPEW_INLINE_TX_CHAR(byte) __CONSOLE_INLINE_TX_CHAR(byte) -#define CONSOLE_SPEW_TX_HEX8(byte) __CONSOLE_TX_HEX8(byte) -#define CONSOLE_SPEW_INLINE_TX_HEX8(byte) __CONSOLE_INLINE_TX_HEX8(byte) -#define CONSOLE_SPEW_TX_HEX32(lword) __CONSOLE_TX_HEX32(lword) -#define CONSOLE_SPEW_INLINE_TX_HEX32(lword) __CONSOLE_INLINE_TX_HEX32(lword) -#define CONSOLE_SPEW_TX_STRING(string) __CONSOLE_TX_STRING(string) -#define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) - - /* uses: esp, ax, dx */ -console_tx_al: - __CONSOLE_INLINE_TX_AL - RETSP - - /* uses: esp, ax, edx */ -console_tx_hex8: - __CONSOLE_INLINE_TX_HEX8(%al) - RETSP - - - /* uses: esp, ebx, eax, dx */ -console_tx_hex32: - mov %eax, %ebx - shr $28, %eax - add $'0', %al - cmp $'9', %al - jle 9f - add $39, %al -9: - __CONSOLE_INLINE_TX_AL - - mov %ebx, %eax - shr $24, %eax - and $0x0f, %al - add $'0', %al - cmp $'9', %al - jle 9f - add $39, %al -9: - __CONSOLE_INLINE_TX_AL - - mov %ebx, %eax - shr $20, %eax - and $0x0f, %al - add $'0', %al - cmp $'9', %al - jle 9f - add $39, %al -9: - __CONSOLE_INLINE_TX_AL - - mov %ebx, %eax - shr $16, %eax - and $0x0f, %al - add $'0', %al - cmp $'9', %al - jle 9f - add $39, %al -9: - __CONSOLE_INLINE_TX_AL - - mov %ebx, %eax - shr $12, %eax - and $0x0f, %al - add $'0', %al - cmp $'9', %al - jle 9f - add $39, %al -9: - __CONSOLE_INLINE_TX_AL - - mov %ebx, %eax - shr $8, %eax - and $0x0f, %al - add $'0', %al - cmp $'9', %al - jle 9f - add $39, %al -9: - __CONSOLE_INLINE_TX_AL - - mov %ebx, %eax - shr $4, %eax - and $0x0f, %al - add $'0', %al - cmp $'9', %al - jle 9f - add $39, %al -9: - __CONSOLE_INLINE_TX_AL - - mov %ebx, %eax - and $0x0f, %al - add $'0', %al - cmp $'9', %al - jle 9f - add $39, %al -9: - __CONSOLE_INLINE_TX_AL - RETSP - - /* Uses esp, ebx, ax, dx */ - -console_tx_string: - mov (%ebx), %al - inc %ebx - cmp $0, %al - jne 9f - RETSP -9: - __CONSOLE_INLINE_TX_AL - jmp console_tx_string - -console0: diff --git a/src/arch/x86/llshell/llshell.inc b/src/arch/x86/llshell/llshell.inc deleted file mode 100644 index a66ac15..0000000 --- a/src/arch/x86/llshell/llshell.inc +++ /dev/null @@ -1,901 +0,0 @@ - -#define RET_LABEL(label) \ - jmp label##_done - -#define CALL_LABEL(label) \ - jmp label ;\ -label##_done: - -#define CALLSP(func) \ - lea 0f, %esp ; \ - jmp func ; \ -0: - -#define RETSP \ - jmp *%esp - - -#include "console.inc" -#include "pci.inc" -#include "ramtest.inc" - -jmp llshell_out - -// (c) 2004 Bryan Chafy, This program is released under the GPL - -// LLShell, A low level interactive debug shell -// Designed to be an interactive shell that operates with zero -// system resources. For example at initial boot. - -// to use, jump to label "low_level_shell" -// set %esp to the return address for exiting - - -#define UART_BASEADDR $0x3f8 -#define resultreg %esi -#define subroutinereg %edi -#define freqtime $2193 // 1.93 * freq -#define timertime $6000 -.equ sys_IOPL, 110 - -// .data -// .text - -welcome: - .string "\r\n! Low Level Shell (LLShell) (c)2004 Bryan Chafy \r\n\r\n" -prompt: - .string "\r\n!> " -badcmd: - .string "bad command\r\n" -sorry: - .string "sorry, not yet implemented\r\n" -cmds: - .string "\r\nList of commands:\r\n \ -\r\nbeep -- pc speaker beep \ -\r\nrst (or RST) -- reset \ -\r\nout(b,w,l) <val> <port> -- raw out val at port \ -\r\nin(b,w,l) <port> -- show raw port value \ -\r\njmp <address> -- jmp to address (llshell addr is in eax) \ -\r\ncall <address> -- funcion call (assumes a working stack) \ -\r\ncli -- clear interrupts \ -\r\nsti -- enable interrupts \ -\r\npush <value> -- push value onto stack \ -\r\npop -- pop from stack and display \ -\r\nwm(b,w,l) <addr> <val> -- write mem \ -\r\ndm <addr> <lines> -- dump mem \ -\r\nmcp <src> <dst> <size> -- mem copy \ -\r\nmpat <pat> <dst> <size> -- mem pattern \ -\r\nmemt <begin> <end> -- memory test \ -\r\npcir(b,w,l) <loc> -- pci read config \ -\r\npciw(b,w,l) <loc> <val> -- pci write config \ -\r\ndl <addr> <size> -- memory download (display xor cheksum at completion) \ -\r\ncram <addr> <size> -- enable cache to be ram (experimental) \ -\r\nbaud <val> -- change baudrate (not yet implemented) \ -\r\nexit -- exit shell \ -\r\nAll values in hex (0x prefixing ok) \ -\r\n" - -cr: - .string "\r\n" -spaces: - .string " " - -// .globl _start -//ASSUME CS:@CODE, DS:@DATA - -// _start: - -// call ioperms - -low_level_shell: - -mov $preamble,subroutinereg -jmp beep -preamble: -mov $welcome,resultreg -mov $readcommand,subroutinereg -jmp displaystring - -readcommand: -mov $prompt,resultreg -mov $rcmd,subroutinereg -jmp displaystring - -rcmd: -mov $readcommand,subroutinereg -movl $0x0, resultreg - -readchar: -mov UART_BASEADDR+5,%dx -in %dx, %al -and $0x9f,%al -test $0x01,%al -jz readchar -mov UART_BASEADDR,%dx -in %dx,%al //char in al -xchg %al,%ah - -send_char: -mov UART_BASEADDR+5,%dx -us_wait: -in %dx,%al -test $0x20,%al -jz us_wait -mov UART_BASEADDR,%dx -xchg %al,%ah -out %al,%dx // output char - -cmp $0x0D,%al //CR -jnz eval_char -mov $0x0A,%ah -jmp send_char - -eval_char: -cmp $0x20,%al //space -jz cmdtable -cmp $0x0A,%al //CR -jz cmdtable -cmp $0x08,%al //BS -jnz additup -//subit: -shr $0x8,resultreg -jmp readchar -additup: -shl $0x8,resultreg -and $0xff,%eax -add %eax,resultreg -jmp readchar - -cmdtable: -mov resultreg,%eax -cmp $0,%eax -jz readcommand -cmp $0x74657374,%eax -jz dotest -cmp $0x68656c70,%eax -jz dohelp -cmp $0x0000003f,%eax -jz dohelp -cmp $0x6f757462,%eax -jz dooutb -cmp $0x6f757477,%eax -jz dooutw -cmp $0x6f75746c,%eax -jz dooutd -cmp $0x00696e62,%eax -jz doinb -cmp $0x00696e77,%eax -jz doinw -cmp $0x00696e6c,%eax -jz doind -cmp $0x63697262,%eax -jz pcirb -cmp $0x63697277,%eax -jz pcirw -cmp $0x6369726c,%eax -jz pcirl -cmp $0x63697762,%eax -jz pciwb -cmp $0x63697777,%eax -jz pciww -cmp $0x6369776c,%eax -jz pciwl -cmp $0x00776d62,%eax -jz wmemb -cmp $0x00776d77,%eax -jz wmemw -cmp $0x00776d6c,%eax -jz wmeml -cmp $0x0000646d,%eax -jz dodmem -cmp $0x6d656d74,%eax -jz memt // mem test -cmp $0x00727374,%eax -jz rst // reset -cmp $0x00525354,%eax -jz RST -cmp $0x62656570,%eax -jz beep -cmp $0x0000646c,%eax -jz dodl // download to mem <loc> <size> -cmp $0x006a6d70,%eax -jz jmpto // jump to location (eax holds return addr) -cmp $0x62617564,%eax -jz baud // change baudrate -cmp $0x00696e74,%eax -jz doint // trigger an interrupt -cmp $0x63616c6c,%eax -jz callto // call assumes memory -cmp $0x70757368,%eax -jz dopush // assumes mem -cmp $0x00706f70,%eax -jz dopop // assumes mem -cmp $0x6372616d,%eax -jz cram // cache ram trick <location> <size> -cmp $0x006d6370,%eax -jz mcp // mem copy <src> <dst> <size> -cmp $0x6d706174,%eax -jz dopattern -cmp $0x00636c69,%eax -jz docli -cmp $0x00737469,%eax -jz dosti -cmp $0x65786974,%eax -jz doexit -mov $badcmd,resultreg -mov $readcommand,subroutinereg -jmp displaystring - - -readnibbles: -movl $0x0, resultreg -readit: -mov UART_BASEADDR+5,%dx -in %dx, %al -and $0x9f,%al -test $0x1,%al -jz readit -mov UART_BASEADDR,%dx -in %dx,%al -xchg %al,%ah - -sendchar: -mov UART_BASEADDR+5,%dx -us_waitit: -in %dx,%al -test $0x20,%al -jz us_waitit -mov UART_BASEADDR,%dx -xchg %al,%ah -out %al,%dx // output char - -cmp $0x78,%al -jz readit -cmp $0x0D,%al //CR -jnz evalchar -mov $0x0A,%ah -jmp sendchar - -evalchar: -cmp $0x20,%al //space -jz gosub -cmp $0x0A,%al //CR -jz gosub -cmp $0x08,%al //BS -jnz processchar -//subit: -shr $0x04,resultreg -jmp readit -processchar: -cmp $0x3A,%al -jl subnum -cmp $0x47,%al -jl subcaps -//sublc: -sub $0x57,%al -jmp additupn -subcaps: -sub $0x37,%al -jmp additupn -subnum: -sub $0x30,%al -additupn: -shl $0x04,resultreg -and $0xf,%eax -add %eax,resultreg -jmp readit - -gosub: -jmp *subroutinereg - -//intersubcall -// eax,edx,esi,edi - -// ebx,ecx,ebp,esp(?) -// ds,es,fs,gs - -dotest: -mov $ramtest,resultreg -mov $test1a,subroutinereg -jmp displayhex -test1a: -mov $welcome,resultreg -mov $readcommand,subroutinereg -jmp displayhex - -dodmem: - -movl $dmem1a, subroutinereg -jmp readnibbles -dmem1a: -mov resultreg,%ebx // address -movl $dmem1b, subroutinereg -jmp readnibbles -dmem1b: -mov resultreg,%ecx // length - -dmemloop: -mov %ebx,resultreg -mov $daddr1,subroutinereg -jmp displayhex -daddr1: -mov $spaces,resultreg -mov $startshowm,subroutinereg -jmp displaystring - -startshowm: -mov (%ebx),resultreg -mov $showm1,subroutinereg -jmp displayhexlinear -showm1: -add $0x04,%ebx -mov (%ebx),resultreg -mov $showm2,subroutinereg -jmp displayhexlinear -showm2: -add $0x04,%ebx -mov (%ebx),resultreg -mov $showm3,subroutinereg -jmp displayhexlinear -showm3: -add $0x04,%ebx -mov (%ebx),resultreg -mov $showa0,subroutinereg -jmp displayhexlinear - -showa0: -sub $0xC,%ebx -mov (%ebx),resultreg -mov $showa1,subroutinereg -jmp displayasciilinear -showa1: -add $0x04,%ebx -mov (%ebx),resultreg -mov $showa2,subroutinereg -jmp displayasciilinear -showa2: -add $0x04,%ebx -mov (%ebx),resultreg -mov $showa3,subroutinereg -jmp displayasciilinear -showa3: -add $0x04,%ebx -mov (%ebx),resultreg -mov $doneshow,subroutinereg -jmp displayasciilinear -doneshow: -mov $cr,resultreg -mov $doneshow1,subroutinereg -jmp displaystring -doneshow1: -dec %cx -cmp $0x0,%cx -jz exitdmem -add $0x04,%ebx -jmp dmemloop -exitdmem: -jmp readcommand - -dooutb: -// out val,port -movl $outb1a, subroutinereg -jmp readnibbles -outb1a: -mov resultreg,%ebx -movl $outb1b, subroutinereg -jmp readnibbles -outb1b: -mov resultreg,%edx -mov %ebx,%eax -out %al,%dx -jmp readcommand - -dooutw: -// out val,port -movl $outw1a, subroutinereg -jmp readnibbles -outw1a: -mov resultreg,%ebx -movl $outw1b, subroutinereg -jmp readnibbles -outw1b: -mov resultreg,%edx -mov %ebx,%eax -out %ax,%dx -jmp readcommand - -dooutd: -// out val,port -movl $outd1a, subroutinereg -jmp readnibbles -outd1a: -mov resultreg,%ebx -movl $outd1b, subroutinereg -jmp readnibbles -outd1b: -mov resultreg,%edx -mov %ebx,%eax -out %eax,%dx -jmp readcommand - -wmemb: -movl $wmemba, subroutinereg -jmp readnibbles -wmemba: -mov resultreg,%ebx -movl $wmembb, subroutinereg -jmp readnibbles -wmembb: -mov resultreg,%eax -mov %al,(%ebx) -jmp readcommand - -wmemw: -movl $wmemwa, subroutinereg -jmp readnibbles -wmemwa: -mov resultreg,%ebx -movl $wmemwb, subroutinereg -jmp readnibbles -wmemwb: -mov resultreg,%eax -mov %ax,(%ebx) -jmp readcommand - -wmeml: -movl $wmemla, subroutinereg -jmp readnibbles -wmemla: -mov resultreg,%ebx -movl $wmemlb, subroutinereg -jmp readnibbles -wmemlb: -mov resultreg,%eax -mov %eax,(%ebx) -jmp readcommand - -doinb: -// in port -movl $inb1a, subroutinereg -jmp readnibbles -inb1a: -mov resultreg,%edx -mov $0x0,%eax -in %dx,%al -mov %eax,resultreg -mov $readcommand,subroutinereg -jmp displayhex - -doinw: -// in port -movl $inw1a, subroutinereg -jmp readnibbles -inw1a: -mov resultreg,%edx -mov $0x0,%eax -in %dx,%ax -mov %eax,resultreg -mov $readcommand,subroutinereg -jmp displayhex - -doind: -// in port -movl $ind1a, subroutinereg -jmp readnibbles -ind1a: -mov resultreg,%edx -in %dx,%eax -mov %eax,resultreg -mov $readcommand,subroutinereg -jmp displayhex - -jmpto: -movl $jmp1a, subroutinereg -jmp readnibbles -jmp1a: -mov $readcommand,%eax -jmp *resultreg - -callto: -movl $call1a, subroutinereg -jmp readnibbles -call1a: -mov $readcommand,%eax -call *resultreg -jmp readcommand - -dopush: -movl $push1a, subroutinereg -jmp readnibbles -push1a: -mov resultreg,%eax -push %eax -jmp readcommand - -doint: -movl $int1a, subroutinereg -jmp readnibbles -int1a: -mov resultreg,%eax -// need to lookup int table? -// int %eax -jmp readcommand - -doenter: -//setup stack frame - - -dopop: -movl $readcommand, subroutinereg -pop resultreg -jmp displayhex - -docli: -cli -jmp readcommand - -dosti: -sti -jmp readcommand - - -displaystring: -// resultreg= pointer to string terminated by \0 -dsloop: -movb (resultreg),%ah -cmp $0x0, %ah -jz displaystringexit -mov UART_BASEADDR+5,%dx -us_waits: -in %dx,%al -test $0x20,%al -jz us_waits -mov UART_BASEADDR,%dx -xchg %al,%ah -out %al,%dx // output char -inc resultreg -jmp dsloop -displaystringexit: -jmp *subroutinereg - -displayhexlinear: -mov resultreg,%eax -xchg %al,%ah -rol $0x10,%eax -xchg %al,%ah -mov %eax,resultreg -displayhex: -rol $0x10,%ecx -mov $0x8,%cx -dhloop: -cmp $0xf,%cl -je exitdisplayhex -rol $0x04,resultreg -movl resultreg,%eax -and $0xf,%al -cmp $0xa,%al -jl addnum -//addcaps -add $0x37,%al -jmp outcharhex -addnum: -add $0x30,%al -outcharhex: -xchg %al,%ah -mov UART_BASEADDR+5,%dx -us_waith: -in %dx,%al -test $0x20,%al -jz us_waith -mov UART_BASEADDR,%dx -xchg %al,%ah -out %al,%dx // output char -dec %cx -cmp $0x0,%cx -jne dhloop -mov $0x20,%al -mov $0x10,%cl -jmp outcharhex -exitdisplayhex: -rol $0x10,%ecx -jmp *subroutinereg - -displayasciilinear: -mov resultreg,%eax -xchg %al,%ah -rol $0x10,%eax -xchg %al,%ah -mov %eax,resultreg -displayascii: -rol $0x10,%ecx -mov $0x4,%cx -daloop: -rol $0x08,resultreg -movl resultreg,%eax -cmp $0x7e,%al -jg unprintable -cmp $0x20,%al -jl unprintable -jmp outcharascii -unprintable: -mov $0x2e,%al // dot -outcharascii: -xchg %al,%ah -mov UART_BASEADDR+5,%dx -us_waita: -in %dx,%al -test $0x20,%al -jz us_waita -mov UART_BASEADDR,%dx -xchg %al,%ah -out %al,%dx // output char -dec %cx -cmp $0x0,%cx -jne daloop -rol $0x10,%ecx -jmp *subroutinereg - -rst: -cli -movb $0x0fe,%al -out %al,$0x64 -hlt - -RST: -cli -lidt %cs:0x03fff -int $0x3 -hlt - - -beep: -mov timertime,%eax -rol $0x10,%eax -mov $0xb6,%al -out %al,$0x43 -mov freqtime,%ax -out %al,$0x42 -xchg %al,%ah -out %al,$0x42 - -in $0x61,%al -or $0x03,%al -out %al,$0x61 - -//timer here -timer: -in $0x42,%al -// xchg %al,%ah -in $0x42,%al -// xchg %al,%ah -cmp $0x0,%al -jnz timer -rol $0x10,%eax -dec %ax -cmp $0x0,%ax; -rol $0x10,%eax -jnz timer -// timer - -in $0x61,%al -and $0xfc,%al -out %al,$0x61 -jmp *subroutinereg - -dohelp: -mov $cmds,resultreg -mov $readcommand,subroutinereg -jmp displaystring - -memt: -movl $memt1, subroutinereg -jmp readnibbles -memt1: -mov resultreg,%ecx -movl $memt2, subroutinereg -jmp readnibbles -memt2: -mov resultreg,%ebx -xchg %ecx,%eax -mov $readcommand,%esp // internal to linux bios -jmp ramtest - -pcirb: -movl $pcirb1, subroutinereg -jmp readnibbles -pcirb1: -mov resultreg,%eax -PCI_READ_CONFIG_BYTE -and $0xff,%eax -mov %eax,resultreg -mov $readcommand,subroutinereg -jmp displayhex - -pcirw: -movl $pcirw1, subroutinereg -jmp readnibbles -pcirw1: -mov resultreg,%eax -PCI_READ_CONFIG_WORD -and $0xffff,%eax -mov %eax,resultreg -mov $readcommand,subroutinereg -jmp displayhex - -pcirl: -movl $pcirl1, subroutinereg -jmp readnibbles -pcirl1: -mov resultreg,%eax -PCI_READ_CONFIG_DWORD -mov %eax,resultreg -mov $readcommand,subroutinereg -jmp displayhex - - - - -pciwb: -movl $pciwb1, subroutinereg -jmp readnibbles -pciwb1: -mov resultreg,%ebx -movl $pciwb2, subroutinereg -jmp readnibbles -pciwb2: -mov resultreg,%edx -mov %ebx,%eax -PCI_WRITE_CONFIG_BYTE -jmp readcommand - -pciww: -movl $pciww1, subroutinereg -jmp readnibbles -pciww1: -mov resultreg,%ebx -movl $pciww2, subroutinereg -jmp readnibbles -pciww2: -mov resultreg,%ecx -mov %ebx,%eax -PCI_WRITE_CONFIG_WORD -jmp readcommand - -pciwl: -movl $pciwl1, subroutinereg -jmp readnibbles -pciwl1: -mov resultreg,%ebx -movl $pciwl2, subroutinereg -jmp readnibbles -pciwl2: -mov resultreg,%ecx -mov %ebx,%eax -PCI_WRITE_CONFIG_DWORD -jmp readcommand - -cram: -//likely not working. Just testing for now -movl $cram1, subroutinereg -jmp readnibbles -cram1: -mov resultreg,%ebx -movl $cram1, subroutinereg -jmp readnibbles -cram2: -mov resultreg,%ecx -// enable it -mov %cr0,%eax -and $0x9fffffff,%eax // also try 0x0fff, 0x2ff(write back)... -mov %eax,%cr0 -//wbinvd ?? -cacheloop: -mov (%ebx),%eax -inc %ebx -loop cacheloop -// disable it -mov %cr0,%eax -or $0x60000000,%eax -mov %eax,%cr0 -//wbinvd ?? - -dodl: -movl $dl1, subroutinereg -jmp readnibbles -dl1: -mov resultreg,%ebx -movl $dl2, subroutinereg -jmp readnibbles -dl2: -mov resultreg,%ecx -mov resultreg,subroutinereg -mov %ebx,resultreg -dlloop: -mov UART_BASEADDR+5,%dx -in %dx, %al -and $0x9f,%al -test $0x01,%al -jz dlloop -mov UART_BASEADDR,%dx -in %dx,%al -mov %al,(%ebx) -inc %ebx -loop dlloop -csum: -mov subroutinereg,%ecx -shr $0x02,%ecx -mov resultreg,%ebx -mov $0x0,%eax -csumloop: -rol $0x03,%eax -mov (%ebx),%dl -xor %dl,%al -inc %ebx -loop csumloop -mov $readcommand,subroutinereg -mov %eax,resultreg -jmp displayhex - -baud: -mov $sorry,resultreg -mov $readcommand,subroutinereg -jmp displaystring - -mcp: -movl $mcp1, subroutinereg -jmp readnibbles -mcp1: -mov resultreg,%ebx -movl $mcp2, subroutinereg -jmp readnibbles -mcp2: -mov resultreg,%ecx -movl $mcp3, subroutinereg -jmp readnibbles -mcp3: -mov resultreg,%eax -xchg %ecx,%eax -mcploop: -mov (%ebx),%dl -mov %dl,(%eax) -inc %ebx -inc %eax -loop mcploop -jmp readcommand - -dopattern: -movl $pat1, subroutinereg -jmp readnibbles -pat1: -mov resultreg,%ebx -movl $pat2, subroutinereg -jmp readnibbles -pat2: -mov resultreg,%ecx -movl $pat3, subroutinereg -jmp readnibbles -pat3: -mov resultreg,%eax -xchg %ecx,%eax -patloop: -rol $0x08,%ebx -mov %bl,(%eax) -inc %eax -loop patloop -jmp readcommand - - -doexit: - // LB specific: -RETSP // if there's no stack yet, caller must set %esp manually -// RET_LABEL(low_level_shell) - - -//Linux OS Specific -ioperms: -movl $sys_IOPL, %eax # system-call ID-number -movl $3, %ebx # new value for IO0PL -int $0x80 # enter the kernel -ret - -llshell_out: diff --git a/src/arch/x86/llshell/pci.inc b/src/arch/x86/llshell/pci.inc deleted file mode 100644 index 7cb7410..0000000 --- a/src/arch/x86/llshell/pci.inc +++ /dev/null @@ -1,229 +0,0 @@ - - /* - * Macro: PCI_WRITE_CONFIG_BYTE - * Arguments: %eax address to write to (includes bus, device, function, &offset) - * %dl byte to write - * - * Results: none - * - * Trashed: %eax, %edx - * Effects: writes a single byte to pci config space - * - * Notes: This routine is optimized for minimal register usage. - * And the tricks it does cannot scale beyond writing a single byte. - * - * What it does is almost simple. - * It preserves %eax (baring special bits) until it is written - * out to the appropriate port. And hides the data byte - * in the high half of edx. - * - * In %edx[3] it stores the byte to write. - * In %edx[2] it stores the lower three bits of the address. - */ - - -#define PCI_WRITE_CONFIG_BYTE \ - shll $8, %edx ; \ - movb %al, %dl ; \ - andb $0x3, %dl ; \ - shll $16, %edx ; \ - \ - orl $0x80000000, %eax ; \ - andl $0xfffffffc, %eax ; \ - movw $0xcf8, %dx ; \ - outl %eax, %dx ; \ - \ - shrl $16, %edx ; \ - movb %dh, %al ; \ - movb $0, %dh ; \ - addl $0xcfc, %edx ; \ - outb %al, %dx - - - /* - * Macro: PCI_WRITE_CONFIG_WORD - * Arguments: %eax address to write to (includes bus, device, function, &offset) - * %ecx word to write - * - * Results: none - * - * Trashed: %eax, %edx - * Preserved: %ecx - * Effects: writes a single byte to pci config space - * - * Notes: This routine is optimized for minimal register usage. - * - * What it does is almost simple. - * It preserves %eax (baring special bits) until it is written - * out to the appropriate port. And hides the least significant - * bits of the address in the high half of edx. - * - * In %edx[2] it stores the lower three bits of the address. - */ - - -#define PCI_WRITE_CONFIG_WORD \ - movb %al, %dl ; \ - andl $0x3, %edx ; \ - shll $16, %edx ; \ - \ - orl $0x80000000, %eax ; \ - andl $0xfffffffc, %eax ; \ - movw $0xcf8, %dx ; \ - outl %eax, %dx ; \ - \ - shrl $16, %edx ; \ - movl %ecx, %eax ; \ - addl $0xcfc, %edx ; \ - outw %ax, %dx - - - - /* - * Macro: PCI_WRITE_CONFIG_DWORD - * Arguments: %eax address to write to (includes bus, device, function, &offset) - * %ecx dword to write - * - * Results: none - * - * Trashed: %eax, %edx - * Preserved: %ecx - * Effects: writes a single byte to pci config space - * - * Notes: This routine is optimized for minimal register usage. - * - * What it does is almost simple. - * It preserves %eax (baring special bits) until it is written - * out to the appropriate port. And hides the least significant - * bits of the address in the high half of edx. - * - * In %edx[2] it stores the lower three bits of the address. - */ - - -#define PCI_WRITE_CONFIG_DWORD \ - movb %al, %dl ; \ - andl $0x3, %edx ; \ - shll $16, %edx ; \ - \ - orl $0x80000000, %eax ; \ - andl $0xfffffffc, %eax ; \ - movw $0xcf8, %dx ; \ - outl %eax, %dx ; \ - \ - shrl $16, %edx ; \ - movl %ecx, %eax ; \ - addl $0xcfc, %edx ; \ - outl %eax, %dx - - - - - /* - * Macro: PCI_READ_CONFIG_BYTE - * Arguments: %eax address to read from (includes bus, device, function, &offset) - * - * Results: %al Byte read - * - * Trashed: %eax, %edx - * Effects: reads a single byte from pci config space - * - * Notes: This routine is optimized for minimal register usage. - * - * What it does is almost simple. - * It preserves %eax (baring special bits) until it is written - * out to the appropriate port. And hides the least significant - * bits of the address in the high half of edx. - * - * In %edx[2] it stores the lower three bits of the address. - */ - - -#define PCI_READ_CONFIG_BYTE \ - movb %al, %dl ; \ - andl $0x3, %edx ; \ - shll $16, %edx ; \ - \ - orl $0x80000000, %eax ; \ - andl $0xfffffffc, %eax ; \ - movw $0xcf8, %dx ; \ - outl %eax, %dx ; \ - \ - shrl $16, %edx ; \ - addl $0xcfc, %edx ; \ - inb %dx, %al - - - - /* - * Macro: PCI_READ_CONFIG_WORD - * Arguments: %eax address to read from (includes bus, device, function, &offset) - * - * Results: %ax word read - * - * Trashed: %eax, %edx - * Effects: reads a 2 bytes from pci config space - * - * Notes: This routine is optimized for minimal register usage. - * - * What it does is almost simple. - * It preserves %eax (baring special bits) until it is written - * out to the appropriate port. And hides the least significant - * bits of the address in the high half of edx. - * - * In %edx[2] it stores the lower three bits of the address. - */ - - -#define PCI_READ_CONFIG_WORD \ - movb %al, %dl ; \ - andl $0x3, %edx ; \ - shll $16, %edx ; \ - \ - orl $0x80000000, %eax ; \ - andl $0xfffffffc, %eax ; \ - movw $0xcf8, %dx ; \ - outl %eax, %dx ; \ - \ - shrl $16, %edx ; \ - addl $0xcfc, %edx ; \ - inw %dx, %ax - - - - /* - * Macro: PCI_READ_CONFIG_DWORD - * Arguments: %eax address to read from (includes bus, device, function, &offset) - * - * Results: %eax - * - * Trashed: %edx - * Effects: reads 4 bytes from pci config space - * - * Notes: This routine is optimized for minimal register usage. - * - * What it does is almost simple. - * It preserves %eax (baring special bits) until it is written - * out to the appropriate port. And hides the least significant - * bits of the address in the high half of edx. - * - * In %edx[2] it stores the lower three bits of the address. - */ - - -#define PCI_READ_CONFIG_DWORD \ - movb %al, %dl ; \ - andl $0x3, %edx ; \ - shll $16, %edx ; \ - \ - orl $0x80000000, %eax ; \ - andl $0xfffffffc, %eax ; \ - movw $0xcf8, %dx ; \ - outl %eax, %dx ; \ - \ - shrl $16, %edx ; \ - addl $0xcfc, %edx ; \ - inl %dx, %eax - - - diff --git a/src/arch/x86/llshell/ramtest.inc b/src/arch/x86/llshell/ramtest.inc deleted file mode 100644 index 49abd4a..0000000 --- a/src/arch/x86/llshell/ramtest.inc +++ /dev/null @@ -1,127 +0,0 @@ - /* - * This is much more of a "Is my SDRAM properly configured?" - * test than a "Is my SDRAM faulty?" test. Not all bits - * are tested. -Tyson - */ - - jmp rt_skip -#define RAMTEST 1 -#if RAMTEST - .section ".rom.data" - -rt_test: .string "Testing SDRAM : " -rt_fill: .string "SDRAM fill:\r\n" -rt_verify: .string "SDRAM verify:\r\n" -rt_toomany: .string "Too many errors.\r\n" -rt_done: .string "Done.\r\n" - .previous -#endif - -ramtest: -#if RAMTEST - mov %eax, %esi - mov %ebx, %edi - mov %esp, %ebp - - CONSOLE_INFO_TX_STRING($rt_test) - CONSOLE_INFO_TX_HEX32(%esi) - CONSOLE_INFO_TX_CHAR($'-') - CONSOLE_INFO_TX_HEX32(%edi) - CONSOLE_INFO_TX_CHAR($'\r') - CONSOLE_INFO_TX_CHAR($'\n') - - /* ============== Fill ram block ==== */ - - CONSOLE_INFO_TX_STRING($rt_fill) - - mov %esi, %ebx -1: - cmp $0, %bx - jne 2f - - /* Display address being filled */ - /* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */ - - CONSOLE_INFO_TX_HEX32(%ebx) - CONSOLE_INFO_TX_CHAR($'\r') -2: -#if i786 - /* Use a non temporal store to go faster and - * to bypass the cache. - */ - movnti %ebx, (%ebx) -#else - mov %ebx, (%ebx) -#endif - add $4, %ebx - cmp %edi, %ebx - jl 1b - - /* Display final address */ - - CONSOLE_INFO_TX_HEX32(%edi) - CONSOLE_INFO_TX_CHAR($'\r') - CONSOLE_INFO_TX_CHAR($'\n') - - /* ========= Verify ram block ========== */ - - CONSOLE_INFO_TX_STRING($rt_verify) - mov %esi, %ebx - -1: - cmp $0, %bx - jne 2f - - /* Display address being tested */ - - CONSOLE_INFO_TX_HEX32(%ebx) - CONSOLE_INFO_TX_CHAR($'\r') -2: - cmp %ebx, (%ebx) - jne 4f -3: - add $4, %ebx - cmp %edi, %ebx - jl 1b - - /* Display final address */ - CONSOLE_INFO_TX_HEX32(%edi) - CONSOLE_INFO_TX_CHAR($'\r') - CONSOLE_INFO_TX_CHAR($'\n') - jmp 6f - -4: - /* Display address with error */ - - CONSOLE_INFO_TX_HEX32(%ebx) - CONSOLE_INFO_TX_CHAR($':') - - /* Display data in address with error */ - - /* CONSOLE_INFO_TX_HEX32(arg) will overwrite %ebx with arg */ - - mov %ebx, %esi - mov 0(%ebx), %eax - CONSOLE_INFO_TX_HEX32(%eax) - mov %esi, %ebx - - CONSOLE_INFO_TX_CHAR($'\r') - CONSOLE_INFO_TX_CHAR($'\n') - sub $1, %ecx - jz 5f - jmp 3b -5: - CONSOLE_INFO_TX_STRING($rt_toomany) -#if CONFIG_ROMCC - post_code(0xf1) - jmp .Lhlt -#endif - -6: - CONSOLE_INFO_TX_STRING($rt_done) - mov %ebp, %esp - -#endif - RETSP - -rt_skip: diff --git a/src/arch/x86/llshell/readme.coreboot b/src/arch/x86/llshell/readme.coreboot deleted file mode 100644 index ae7dcbe..0000000 --- a/src/arch/x86/llshell/readme.coreboot +++ /dev/null @@ -1,25 +0,0 @@ - -1) Include llshell.inc in your northbridge Config file -2) In raminit.inc (or whatever), make a jmp out to low_level_shell, setting - a return label in %esp. -For example: -ram_set_registers: - - mov $llshell_ret1,%esp - jmp low_level_shell -llshell_ret1: - - /* Disable and invalidate the cache */ - invd - mov %cr0, %eax - .... -3) Optionally, comment out two lines in ramtest.inc: -5: - CONSOLE_INFO_TX_STRING($rt_toomany) - // post_code(0xf1) - // jmp .Lhlt -otherwise, a ramtest failure will hang - -4) build and flash as normal -If it worked, the speaker will beep, and you'll get a shell. -Type help or ? at the prompt for a list of commands. diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index c8cb363..3011ab6 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -23,7 +23,6 @@ #include <spd.h> #include <arch/io.h> #include <arch/hlt.h> -#include <arch/llshell.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index 77dfd5d..8a41f7c 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -24,7 +24,6 @@ #include <spd.h> #include <arch/io.h> #include <arch/hlt.h> -#include <arch/llshell.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index 1e05d63..30ea8bd 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <arch/hlt.h> -#include <arch/llshell.h> #include "drivers/pc80/udelay_io.c" #include <console/console.h> #include <lib.h> @@ -117,8 +116,4 @@ void main(unsigned long bist) /* Initialize memory */ sdram_initialize(); - -#if CONFIG_LLSHELL - llshell(); -#endif }

1 0

Patch set updated for coreboot: ba7f7d0 northbridge/amd/amdmct: Use `static const` instead of `const static`
by Paul Menzel 16 May '13

16 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3197 -gerrit commit ba7f7d01bd1ff32af1d7a616a636c95337f9d816 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat May 4 18:07:13 2013 +0200 northbridge/amd/amdmct: Use `static const` instead of `const static` From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. The following command was used to make the change. $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/' As asked by Bruce Griffith, the changes in `src/vendorcode` were reverted as that is what AMD prefers. The same change was done already for AMD Persimmon in the following commit. commit 824e192809e021b3cdee947a44b3a18d276bdb35 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 Persimmon: platform_cfg.h: Declare codec arrays as `static const` Reviewed-on: http://review.coreboot.org/2474 Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/amd/amdmct/mct/mctdqs_d.c | 4 ++-- src/northbridge/amd/amdmct/mct/mctsrc.c | 6 +++--- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 0e2a43f..ab1347a 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -84,7 +84,7 @@ static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 } /*Warning: These must be located so they do not cross a logical 16-bit segment boundary!*/ -const static u32 TestPatternJD1a_D[] = { +static const u32 TestPatternJD1a_D[] = { 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW0-1, ALL-EVEN */ 0x00000000,0x00000000,0x00000000,0x00000000, /* QW2-3, ALL-EVEN */ 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW4-5, ALL-EVEN */ @@ -122,7 +122,7 @@ const static u32 TestPatternJD1a_D[] = { 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW4-5, DQ7-ODD */ 0x80808080,0x80808080,0x80808080,0x80808080 /* QW6-7, DQ7-ODD */ }; -const static u32 TestPatternJD1b_D[] = { +static const u32 TestPatternJD1b_D[] = { 0x00000000,0x00000000,0x00000000,0x00000000, /* QW0,CHA-B, ALL-EVEN */ 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, /* QW1,CHA-B, ALL-EVEN */ 0x00000000,0x00000000,0x00000000,0x00000000, /* QW2,CHA-B, ALL-EVEN */ diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 4280645..feb4170 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -50,19 +50,19 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat); /* Warning: These must be located so they do not cross a logical 16-bit segment boundary! */ -const static u32 TestPattern0_D[] = { +static const u32 TestPattern0_D[] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, }; -const static u32 TestPattern1_D[] = { +static const u32 TestPattern1_D[] = { 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, }; -const static u32 TestPattern2_D[] = { +static const u32 TestPattern2_D[] = { 0x12345678, 0x87654321, 0x23456789, 0x98765432, 0x59385824, 0x30496724, 0x24490795, 0x99938733, 0x40385642, 0x38465245, 0x29432163, 0x05067894, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 4f4870c..76d01da 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -92,7 +92,7 @@ static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 } /*Warning: These must be located so they do not cross a logical 16-bit segment boundary!*/ -const static u32 TestPatternJD1a_D[] = { +static const u32 TestPatternJD1a_D[] = { 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW0-1, ALL-EVEN */ 0x00000000,0x00000000,0x00000000,0x00000000, /* QW2-3, ALL-EVEN */ 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, /* QW4-5, ALL-EVEN */ @@ -130,7 +130,7 @@ const static u32 TestPatternJD1a_D[] = { 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, /* QW4-5, DQ7-ODD */ 0x80808080,0x80808080,0x80808080,0x80808080 /* QW6-7, DQ7-ODD */ }; -const static u32 TestPatternJD1b_D[] = { +static const u32 TestPatternJD1b_D[] = { 0x00000000,0x00000000,0x00000000,0x00000000, /* QW0,CHA-B, ALL-EVEN */ 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, /* QW1,CHA-B, ALL-EVEN */ 0x00000000,0x00000000,0x00000000,0x00000000, /* QW2,CHA-B, ALL-EVEN */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index c60cefb..6189608 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -49,19 +49,19 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat); /* Warning: These must be located so they do not cross a logical 16-bit segment boundary! */ -const static u32 TestPattern0_D[] = { +static const u32 TestPattern0_D[] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, }; -const static u32 TestPattern1_D[] = { +static const u32 TestPattern1_D[] = { 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, }; -const static u32 TestPattern2_D[] = { +static const u32 TestPattern2_D[] = { 0x12345678, 0x87654321, 0x23456789, 0x98765432, 0x59385824, 0x30496724, 0x24490795, 0x99938733, 0x40385642, 0x38465245, 0x29432163, 0x05067894,

1 0

Patch set updated for coreboot: 7b4bd87 AMD Trinity boards: Use `sizeof(var)` to get its size
by Paul Menzel 16 May '13

16 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3247 -gerrit commit 7b4bd871faa5f10317a53716cbe6b73ce6d970c6 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat May 4 00:08:34 2013 +0200 AMD Trinity boards: Use `sizeof(var)` to get its size Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR? These changes are based on Rudolf’s original patch »ASUS F2A85-M: Correct and clean up PCIe config« [1], where it was just done for the ASUS board. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I4aa4c6cde5a27b7f335a71afc21d1603f2ae814b Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/parmer/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 20 +++++++++----------- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 20 +++++++++----------- 3 files changed, 27 insertions(+), 33 deletions(-) diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index d3d66a3..1925db8 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -183,9 +183,7 @@ OemCustomizeInitEarly ( /* */ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */ /* */ - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR) * 3; + AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -198,30 +196,30 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Trinity); TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof(PortList); TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (TrinityPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Trinity), &InitEarly->StdHeader); LibAmdMemFill (TrinityPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 3, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index 3837341..ec5d68d 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -182,9 +182,7 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR) * 3; + AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -197,30 +195,30 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Trinity); TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof(PortList); TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (TrinityPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Trinity), &InitEarly->StdHeader); LibAmdMemFill (TrinityPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 3, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr; diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 8907c13..fff40a8 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -204,9 +204,7 @@ OemCustomizeInitEarly ( // // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR // - AllocHeapParams.RequestedBufferSize = sizeof (PCIe_COMPLEX_DESCRIPTOR) + - sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR) * 6; + AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList); AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -219,30 +217,30 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + AllocHeapParams.BufferPtr += sizeof(Trinity); TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + AllocHeapParams.BufferPtr += sizeof(PortList); TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemFill (TrinityPcieComplexListPtr, 0, - sizeof (PCIe_COMPLEX_DESCRIPTOR), + sizeof(Trinity), &InitEarly->StdHeader); LibAmdMemFill (TrinityPciePortPtr, 0, - sizeof (PCIe_PORT_DESCRIPTOR) * 7, + sizeof(PortList), &InitEarly->StdHeader); LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof(DdiList), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;

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coreboot-gerrit May 2013