coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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593 discussions

Patch merged into coreboot/master: adc300d libpayload: Fix the logic for hardware-less serial consoles
by gerrit＠coreboot.org 15 May '13

15 May '13

the following patch was just integrated into master: commit adc300d88b35ceafafb4d4b6426c6458dc46b685 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue May 14 08:43:25 2013 -0600 libpayload: Fix the logic for hardware-less serial consoles This fixes the configuration where serial console output is being sent to non-existant hardware to be captured with I/O trapping. In this configuration where there isn't serial hardware present we still want to init the consoles. We just never want to read non-existant hardware. Change-Id: Ic51dc574b9c0df3f6ed071086b0fb2119afedc44 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3249 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3249 for details. -gerrit

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Patch set updated for coreboot: caefe20 haswell: enable cache-as-ram migration
by Aaron Durbin 15 May '13

15 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3236 -gerrit commit caefe206ae31bc3301ba60805cc792024214dbc0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:51:43 2013 -0500 haswell: enable cache-as-ram migration The haswell code allows for vboot ramstage verification. However, that code path relies on accessing global cache-as-ram variables after cache-as-ram is torn down. In order to avoid that situation enable cache-as-ram migration. cbmemc_reinit() no longer needs to be called from romstage because it is invoked automatically by the cache-as-ram migration infrastructure. Change-Id: I08998dca579c167699030e1e24ea0af8802c0758 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/haswell/romstage.c | 5 ----- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 152059f..4c61b2d 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CAR_MIGRATION config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1093e6b..8196273 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -188,11 +188,6 @@ void * asmlinkage romstage_main(unsigned long bist) /* Get the stack to use after cache-as-ram is torn down. */ romstage_stack_after_car = setup_romstage_stack_after_car(); -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif - return romstage_stack_after_car; }

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Patch set updated for coreboot: 50d9a4e x86: add cache-as-ram migration option
by Aaron Durbin 15 May '13

15 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3232 -gerrit commit 50d9a4ea30261b8edacc4e921ebfe5ae19f7251e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:33:32 2013 -0500 x86: add cache-as-ram migration option There are some boards that do a significant amount of work after cache-as-ram is torn down but before ramstage is loaded. For example, using vboot to verify the ramstage is one such operation. However, there are pieces of code that are executed that reference global variables that are linked in the cache-as-ram region. If those variables are referenced after cache-as-ram is torn down then the values observed will most likely be incorrect. Therefore provide a Kconfig option to select cache-as-ram migration to memory using cbmem. This option is named CAR_MIGRATION. When enabled, the address of cache-as-ram variables may be obtained dynamically. Additionally, when cache-as-ram migration occurs the cache-as-ram data region for global variables is copied into cbmem. There are also automatic callbacks for other modules to perform their own migration, if necessary. Change-Id: I2e77219647c2bd2b1aa845b262be3b2543f1fcb7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/init/romstage.ld | 12 +++++ src/cpu/Makefile.inc | 1 + src/cpu/x86/Kconfig | 9 ++++ src/cpu/x86/Makefile.inc | 1 + src/cpu/x86/car.c | 101 ++++++++++++++++++++++++++++++++++++++++++ src/include/cbmem.h | 1 + src/include/cpu/x86/car.h | 29 ++++++++++++ src/lib/cbmem.c | 4 ++ src/lib/cbmem_info.c | 1 + src/lib/dynamic_cbmem.c | 9 ++++ 10 files changed, 168 insertions(+) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 88c5657..f44185f 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -35,6 +35,10 @@ SECTIONS *(.rodata.*); *(.rom.data.*); . = ALIGN(16); + _car_migrate_start = .; + *(.car.migrate); + _car_migrate_end = .; + . = ALIGN(16); _erom = .; } @@ -48,8 +52,16 @@ SECTIONS . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { + _car_data_start = .; *(.car.global_data); + /* The cbmem_console section comes last to take advantage of + * a zero-sized array to hold the memconsole contents that + * grows to a bound of CONFIG_CONSOLE_CAR_BUFFER_SIZE. However, + * collisions within the cache-as-ram region cannot be + * statically checked because the cache-as-ram region usage is + * cpu/chipset dependent. */ *(.car.cbmem_console); + _car_data_end = .; } _bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index b48a803..8d93756 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -6,6 +6,7 @@ subdirs-y += armltd subdirs-y += intel subdirs-y += samsung subdirs-y += via +subdirs-y += x86 ################################################################################ ## Rules for building the microcode blob in CBFS diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index c64a8e4..c10dd15 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -115,3 +115,12 @@ config X86_AMD_FIXED_MTRRS help This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs. + +config CAR_MIGRATION + def_bool n + depends on DYNAMIC_CBMEM || EARLY_CBMEM_INIT + help + Migrate the cache-as-ram variables to CBMEM once CBMEM is set up + in romstage. This option is only needed if one will be doing more + work in romstage after the cache-as-ram is torn down aside from + loading ramstage. diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc new file mode 100644 index 0000000..fe8648c --- /dev/null +++ b/src/cpu/x86/Makefile.inc @@ -0,0 +1 @@ +romstage-$(CONFIG_CAR_MIGRATION) += car.c diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c new file mode 100644 index 0000000..31fc67c --- /dev/null +++ b/src/cpu/x86/car.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <stddef.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/car.h> + +typedef void (* const car_migration_func_t)(void); + +extern car_migration_func_t _car_migrate_start; +extern car_migration_func_t _car_migrate_end; + +extern char _car_data_start[]; +extern char _car_data_end[]; + +/* + * The car_migrated global variable determines if the cache-as-ram space has + * been migrated to real RAM. It does this by asumming the following things: + * 1. cache-as-ram space is zero'd out once it is set up. + * 2. Either the cache-as-ram space is memory-backed after getting torn down + * or the space returns 0xff's for each byte read. + * Based on these 2 attributes there is the ability to tell when the + * cache-as-ram region has been migrated. + */ +static int car_migrated CAR_GLOBAL; + + +void *car_get_var_ptr(void *var) +{ + char *migrated_base; + int offset; + void * _car_start = &_car_data_start; + void * _car_end = &_car_data_end; + + /* If the cache-as-ram has not been migrated return the pointer + * passed in. */ + if (!car_migrated) + return var; + + if (var < _car_start || var >= _car_end) { + printk(BIOS_ERR, + "Requesting CAR variable outside of CAR region: %p\n", + var); + return var; + } + + migrated_base = cbmem_find(CBMEM_ID_CAR_GLOBALS); + + if (migrated_base == NULL) { + printk(BIOS_ERR, "CAR: Could not find migration base!\n"); + return var; + } + + offset = (char *)var - (char *)_car_start; + + return &migrated_base[offset]; +} + +void car_migrate_variables(void) +{ + void *migrated_base; + car_migration_func_t *migrate_func; + size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; + + migrated_base = cbmem_add(CBMEM_ID_CAR_GLOBALS, car_data_size); + + if (migrated_base == NULL) { + printk(BIOS_ERR, "Could not migrate CAR data!\n"); + return; + } + + memcpy(migrated_base, &_car_data_start[0], car_data_size); + + /* Mark that the data has been moved. */ + car_migrated = ~0; + + /* Call all the migration functions. */ + migrate_func = &_car_migrate_start; + while (migrate_func != &_car_migrate_end) { + (*migrate_func)(); + migrate_func++; + } +} diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 67cb1cb..baec780 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -69,6 +69,7 @@ #define CBMEM_ID_RAMSTAGE_CACHE 0x9a3ca54e #define CBMEM_ID_ROOT 0xff4007ff #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 +#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_NONE 0x00000000 #ifndef __ASSEMBLER__ diff --git a/src/include/cpu/x86/car.h b/src/include/cpu/x86/car.h index 2d2af03..7b5cedf 100644 --- a/src/include/cpu/x86/car.h +++ b/src/include/cpu/x86/car.h @@ -28,4 +28,33 @@ #define CAR_CBMEM #endif +#if CONFIG_CAR_MIGRATION && defined(__PRE_RAM__) +#define CAR_MIGRATE_ATTR __attribute__ ((used,section (".car.migrate"))) + +/* Call migrate_fn_() when CAR globals are migrated. */ +#define CAR_MIGRATE(migrate_fn_) \ + static void (* const migrate_fn_ ## _ptr)(void) CAR_MIGRATE_ATTR = \ + migrate_fn_; + +/* Get the correct pointer for the CAR global variable. */ +void *car_get_var_ptr(void *var); + +/* Get and set a primitive type global variable. */ +#define car_get_var(var) \ + *(typeof(var) *)car_get_var_ptr(&(var)) +#define car_set_var(var, val) \ + do { car_get_var(var) = (val); } while(0) + +/* Migrate the CAR variables to memory. */ +void car_migrate_variables(void); + +#else +#define CAR_MIGRATE(migrate_fn_) +static inline void *car_get_var_ptr(void *var) { return var; } +#define car_get_var(var) (var) +#define car_set_var(var, val) do { (var) = (val); } while (0) +static inline void car_migrate_variables(void) { } +#endif + + #endif diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index e8200b6..3702da1 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -22,6 +22,7 @@ #include <bootstate.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/car.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) #include <arch/acpi.h> #endif @@ -228,6 +229,9 @@ int cbmem_initialize(void) #ifndef __PRE_RAM__ cbmem_arch_init(); #endif + /* Migrate cache-as-ram variables. */ + car_migrate_variables(); + return rv; } #endif diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index ad8c890..7031a70 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -46,6 +46,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_RAMSTAGE_CACHE, "RAMSTAGE $ " }, { CBMEM_ID_ROOT, "CBMEM ROOT " }, { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, + { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, }; void cbmem_print_entry(int n, u32 id, u64 base, u64 size) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 5c269a0..ba7760d 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -23,6 +23,7 @@ #include <cbmem.h> #include <string.h> #include <stdlib.h> +#include <cpu/x86/car.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) #include <arch/acpi.h> #endif @@ -182,12 +183,17 @@ void cbmem_initialize_empty(void) root, root->max_entries); cbmem_arch_init(); + + /* Migrate cache-as-ram variables. */ + car_migrate_variables(); } static inline int cbmem_fail_recovery(void) { cbmem_initialize_empty(); cbmem_handle_acpi_resume(); + /* Migrate cache-as-ram variables. */ + car_migrate_variables(); return 1; } @@ -256,6 +262,9 @@ int cbmem_initialize(void) cbmem_arch_init(); + /* Migrate cache-as-ram variables. */ + car_migrate_variables(); + /* Recovery successful. */ return 0; }

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Patch set updated for coreboot: 02c3aa8 pc80/tpm: allow for cache-as-ram migration
by Aaron Durbin 15 May '13

15 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3233 -gerrit commit 02c3aa82589329ca0eb8f468eca478106fff0430 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:40:56 2013 -0500 pc80/tpm: allow for cache-as-ram migration As the TPM driver can be accessed in romstage after cache-as-ram is torn down use the cache-as-ram migration API to dynamically determine the global variable address. Change-Id: I149d7c130bc3677ed52282095670c07a76c34439 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/pc80/tpm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/pc80/tpm.c b/src/drivers/pc80/tpm.c index c7b5081..9a4fc09 100644 --- a/src/drivers/pc80/tpm.c +++ b/src/drivers/pc80/tpm.c @@ -278,7 +278,7 @@ static u32 tis_probe(void) u16 vid, did; int i; - if (vendor_dev_id) + if (car_get_var(vendor_dev_id)) return 0; /* Already probed. */ didvid = tpm_read(0, TIS_REG_DID_VID); @@ -287,7 +287,7 @@ static u32 tis_probe(void) return TPM_DRIVER_ERR; } - vendor_dev_id = didvid; + car_set_var(vendor_dev_id, didvid); vid = didvid & 0xffff; did = (didvid >> 16) & 0xffff;

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Patch set updated for coreboot: 4ee4f5e chromeos: use cache-as-ram migration API for vbnv
by Aaron Durbin 15 May '13

15 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3234 -gerrit commit 4ee4f5e8fbd614efc4c495f7d454a1d2c5d6f2e3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:42:14 2013 -0500 chromeos: use cache-as-ram migration API for vbnv It's possible that the vbnv global variables may be accessed in romstage after cache-as-ram is torn down. Therefore use the cache-as-ram migration API. Wrappers were written to wrap the API to keep the existing code as close as possible. Change-Id: Ia1d8932f98e00def0a44444a1ead0018a59d3d98 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/vbnv.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c index 2a2faf9..d94203a 100644 --- a/src/vendorcode/google/chromeos/vbnv.c +++ b/src/vendorcode/google/chromeos/vbnv.c @@ -53,7 +53,25 @@ #define CRC_OFFSET 15 static int vbnv_initialized CAR_GLOBAL; -uint8_t vbnv[CONFIG_VBNV_SIZE] CAR_GLOBAL; +static uint8_t vbnv[CONFIG_VBNV_SIZE] CAR_GLOBAL; + +/* Wrappers for accessing the variables marked as CAR_GLOBAL. */ +static inline int is_vbnv_initialized(void) +{ + return car_get_var(vbnv_initialized); +} + +static inline uint8_t *vbnv_data_addr(int index) +{ + uint8_t *vbnv_arr = car_get_var_ptr(vbnv); + + return &vbnv_arr[index]; +} + +static inline uint8_t vbnv_data(int index) +{ + return *vbnv_data_addr(index); +} /* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. A * table-based algorithm would be faster, but for only 15 bytes isn't @@ -109,20 +127,20 @@ void save_vbnv(const uint8_t *vbnv_copy) static void vbnv_setup(void) { - read_vbnv(vbnv); - vbnv_initialized = 1; + read_vbnv(vbnv_data_addr(0)); + car_set_var(vbnv_initialized, 1); } int get_recovery_mode_from_vbnv(void) { - if (!vbnv_initialized) + if (!is_vbnv_initialized()) vbnv_setup(); - return vbnv[RECOVERY_OFFSET]; + return vbnv_data(RECOVERY_OFFSET); } int vboot_wants_oprom(void) { - if (!vbnv_initialized) + if (!is_vbnv_initialized()) vbnv_setup(); /* FIXME(crosbug.com/p/8789). The following commented-out line does the @@ -130,6 +148,6 @@ int vboot_wants_oprom(void) * rebooted if it finds that it's needed but not loaded. At the moment, * it doesn't yet do that, so we must always say we want it. */ - /* return (vbnv[BOOT_OFFSET] & BOOT_OPROM_NEEDED) ? 1 : 0; */ + /* return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0; */ return 1; }

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Patch set updated for coreboot: 288dbaf cbmem console: use cache-as-ram API and cleanup
by Aaron Durbin 15 May '13

15 May '13

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3235 -gerrit commit 288dbafc23538326b7d23aa49972190340c0ceb0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 10 00:45:37 2013 -0500 cbmem console: use cache-as-ram API and cleanup Allow for automatic cache-as-ram migration for the cbmem console. The code was refactored in the thought of making it easier to read. The #ifdefs still exist, but they are no longer sprinkled throughout the code. The cbmem_console_p variable now exists globally in both romstage and ramstage. However, the cbmem_console_p is referenced using the cache-as-ram API. When cbmem is initialized the console is automatically copied over by calling cbmemc_reinit() through a callback. Change-Id: I9f4a64e33c58b8b7318db27942e37c13804e6f2c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/cbmem_console.c | 93 +++++++++++++++++++++++++++++++------------------ 1 file changed, 60 insertions(+), 33 deletions(-) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 2e22dec..efb8e86 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -34,6 +34,8 @@ struct cbmem_console { u8 buffer_body[0]; } __attribute__ ((__packed__)); +static struct cbmem_console *cbmem_console_p CAR_GLOBAL; + #ifdef __PRE_RAM__ /* * While running from ROM, before DRAM is initialized, some area in cache as @@ -42,7 +44,6 @@ struct cbmem_console { */ static struct cbmem_console car_cbmem_console CAR_CBMEM; -#define cbmem_console_p (&car_cbmem_console) /* * Once DRAM is initialized and the cache as ram mode is disabled, while still @@ -54,6 +55,7 @@ static struct cbmem_console car_cbmem_console CAR_CBMEM; * find out where the actual console log buffer is. */ #define CBMEM_CONSOLE_REDIRECT (*((struct cbmem_console **)0x600)) + #else /* @@ -63,41 +65,64 @@ static struct cbmem_console car_cbmem_console CAR_CBMEM; * during the ROM stage, once CBMEM becomes available at RAM stage. */ static u8 static_console[40000]; -static struct cbmem_console *cbmem_console_p; #endif +static inline struct cbmem_console *current_console(void) +{ +#if CONFIG_CAR_MIGRATION || !defined(__PRE_RAM__) + return car_get_var(cbmem_console_p); +#else + /* + * This check allows to tell if the cache as RAM mode has been exited + * or not. If it has been exited, the real memory is being used + * (resulting in the variable on the stack located below + * DCACHE_RAM_BASE), use the redirect pointer to find out where the + * actual console buffer is. + */ + if ((uintptr_t)__builtin_frame_address(0) < + (uintptr_t)CONFIG_DCACHE_RAM_BASE) + return CBMEM_CONSOLE_REDIRECT; + return car_get_var(cbmem_console_p); +#endif /* CONFIG_CAR_MIGRATION */ +} + +static inline void current_console_set(struct cbmem_console *new_console_p) +{ +#if CONFIG_CAR_MIGRATION || !defined(__PRE_RAM__) + car_set_var(cbmem_console_p, new_console_p); +#else + CBMEM_CONSOLE_REDIRECT = new_console_p; +#endif +} + +static inline void init_console_ptr(void *storage, u32 total_space) +{ + struct cbmem_console *cbm_cons_p = storage; + + /* Initialize the cache-as-ram pointer and underlying structure. */ + car_set_var(cbmem_console_p, cbm_cons_p); + cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); + cbm_cons_p->buffer_cursor = 0; +} + void cbmemc_init(void) { #ifdef __PRE_RAM__ - cbmem_console_p->buffer_size = CONFIG_CONSOLE_CAR_BUFFER_SIZE - - sizeof(struct cbmem_console); + init_console_ptr(&car_cbmem_console, CONFIG_CONSOLE_CAR_BUFFER_SIZE); #else /* * Initializing before CBMEM is available, use static buffer to store * the log. */ - cbmem_console_p = (struct cbmem_console *) static_console; - cbmem_console_p->buffer_size = sizeof(static_console) - - sizeof(struct cbmem_console); + init_console_ptr(static_console, sizeof(static_console)); #endif - cbmem_console_p->buffer_cursor = 0; } void cbmemc_tx_byte(unsigned char data) { - struct cbmem_console *cbm_cons_p = cbmem_console_p; + struct cbmem_console *cbm_cons_p = current_console(); u32 cursor; -#ifdef __PRE_RAM__ - /* - * This check allows to tell if the cache as RAM mode has been exited - * or not. If it has been exited, the real memory is being used - * (resulting in the variable on the stack located below - * DCACHE_RAM_BASE), use the redirect pointer to find out where the - * actual console buffer is. - */ - if ((uintptr_t)&cursor < (uintptr_t)&car_cbmem_console) - cbm_cons_p = CBMEM_CONSOLE_REDIRECT; -#endif + if (!cbm_cons_p) return; @@ -119,14 +144,17 @@ static void copy_console_buffer(struct cbmem_console *new_cons_p) { u32 copy_size; u32 cursor = new_cons_p->buffer_cursor; - int overflow = cbmem_console_p->buffer_cursor > - cbmem_console_p->buffer_size; + struct cbmem_console *old_cons_p; + int overflow; + + old_cons_p = current_console(); + + overflow = old_cons_p->buffer_cursor > old_cons_p->buffer_size; copy_size = overflow ? - cbmem_console_p->buffer_size : cbmem_console_p->buffer_cursor; + old_cons_p->buffer_size : old_cons_p->buffer_cursor; - memcpy(new_cons_p->buffer_body + cursor, - cbmem_console_p->buffer_body, + memcpy(new_cons_p->buffer_body + cursor, old_cons_p->buffer_body, copy_size); cursor += copy_size; @@ -134,7 +162,7 @@ static void copy_console_buffer(struct cbmem_console *new_cons_p) if (overflow) { const char loss_str1[] = "\n\n*** Log truncated, "; const char loss_str2[] = " characters dropped. ***\n\n"; - u32 dropped_chars = cbmem_console_p->buffer_cursor - copy_size; + u32 dropped_chars = old_cons_p->buffer_cursor - copy_size; /* * When running from ROM sprintf is not available, a simple @@ -173,7 +201,7 @@ void cbmemc_reinit(void) cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); if (!cbm_cons_p) { - CBMEM_CONSOLE_REDIRECT = NULL; + current_console_set(NULL); return; } @@ -181,18 +209,17 @@ void cbmemc_reinit(void) sizeof(struct cbmem_console); cbm_cons_p->buffer_cursor = 0; - - copy_console_buffer(cbm_cons_p); - - CBMEM_CONSOLE_REDIRECT = cbm_cons_p; #else cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); if (!cbm_cons_p) return; +#endif copy_console_buffer(cbm_cons_p); - cbmem_console_p = cbm_cons_p; -#endif + current_console_set(cbm_cons_p); } + +/* Call cbmemc_reinit() at CAR migration time. */ +CAR_MIGRATE(cbmemc_reinit)

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Patch merged into coreboot/master: 4bd7b0c EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1.
by gerrit＠coreboot.org 14 May '13

14 May '13

the following patch was just integrated into master: commit 4bd7b0cbadabb45f9131da03121a6ca284f24f35 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri May 10 22:18:09 2013 +0200 EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1. build-snow got broken when the snow makefile improved. So fix it. While we're at it, create a script like the update-microcode scripts that gets the bl1. I thought about making this a common script but the various names and paths always evolve, leaving me thinking it's not worth it. This script is just a piece of the snow build script. Change-Id: I65c0f8697a978c62fe12533c4f0152d14dbaefda Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/3238 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/3238 for details. -gerrit

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Patch set updated for coreboot: ba39ab7 EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1.
by Ronald G. Minnich 14 May '13

14 May '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3238 -gerrit commit ba39ab7711777b15e5ae04515534827cdcb45525 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri May 10 22:18:09 2013 +0200 EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1. build-snow got broken when the snow makefile improved. So fix it. While we're at it, create a script like the update-microcode scripts that gets the bl1. I thought about making this a common script but the various names and paths always evolve, leaving me thinking it's not worth it. This script is just a piece of the snow build script. Change-Id: I65c0f8697a978c62fe12533c4f0152d14dbaefda Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/update-bl1.sh | 26 ++++++++++++++++++++++++++ src/vendorcode/google/chromeos/build-snow | 21 ++++----------------- 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/src/cpu/samsung/exynos5250/update-bl1.sh b/src/cpu/samsung/exynos5250/update-bl1.sh new file mode 100644 index 0000000..e47b25d --- /dev/null +++ b/src/cpu/samsung/exynos5250/update-bl1.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +BL1_NAME="E5250.nbl1.bin" +BL1_PATH="3rdparty/cpu/samsung/exynos5250/" +BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exyn…" + +get_bl1() { + mkdir -p "${BL1_PATH}" + cd "${BL1_PATH}" + wget "${BL1_URL}" -O bl1.tbz2 + tar jxvf bl1.tbz2 + mv "exynos-pre-boot/firmware/${BL1_NAME}" . + rm -rf exynos-pre-boot + if [ ! -e "${BL1_NAME}" ]; then + echo "Error getting BL1" + fi +} + +main() { + if [ ! -e ${BL1_PATH}/${BL1_NAME} ]; then + get_bl1 + fi +} + +set -e +main "$@" diff --git a/src/vendorcode/google/chromeos/build-snow b/src/vendorcode/google/chromeos/build-snow index a749ba5..da1566b 100755 --- a/src/vendorcode/google/chromeos/build-snow +++ b/src/vendorcode/google/chromeos/build-snow @@ -44,29 +44,16 @@ get_bl1() { fi } -merge_bl1() { - local outfile="$1" - local bl1="${BL1_PATH}/${BL1_NAME}" - - if [ ! -e "$bl1" ]; then - get_bl1 - fi - - # use the new BL1 which supports 30KB BL2/SPL/Coreboot - local size="$(stat -c "%s" "$outfile")" - local bl1_size="$(stat -c "%s" "$bl1")" - - [ "$bl1_size" = "$((0x2000))" ] || die "Incorrect BL1 input file." - dd if="$bl1" of=${outfile} conv=notrunc -} - is_servod_ready() { ps -C servod >/dev/null 2>&1 } main() { + if [ ! -e "$bl1" ]; then + get_bl1 + fi + make - merge_bl1 "$OUTPUT" create_diff_192k "$OUTPUT" "$TMP_DIFF" echo "OK: Generated image (with BL1) in $OUTPUT" if is_servod_ready; then

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Patch set updated for coreboot: e235fd0 Clean up usage of multiply_to_tsc
by Ronald G. Minnich 14 May '13

14 May '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3242 -gerrit commit e235fd0d72dbdc18294256dfb05ccc5000884200 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 8 17:08:55 2013 +0200 Clean up usage of multiply_to_tsc multiply_to_tsc was being copied everywhere, which is bad practice. Put it in the tsc.h include file where it belongs. Delete the copies of it. Per secunet, no copyright notice is needed. This might be a good time to get a copyright notice into tsc.h anyway. Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/include/cpu/x86/tsc.h | 13 +++++++++++++ src/northbridge/intel/gm45/delay.c | 12 ------------ src/northbridge/intel/i5000/udelay.c | 12 ------------ src/northbridge/intel/i945/udelay.c | 12 ------------ src/northbridge/intel/sandybridge/udelay.c | 13 ------------- 5 files changed, 13 insertions(+), 49 deletions(-) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8e49a66..66451ad 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -27,6 +27,19 @@ static inline tsc_t rdtsc(void) } #if !defined(__ROMCC__) +/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. + * This code is used to prevent use of libgcc's umoddi3. + */ +static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) +{ + tsc->lo = (a & 0xffff) * (b & 0xffff); + tsc->hi = ((tsc->lo >> 16) + + ((a & 0xffff) * (b >> 16)) + + ((b & 0xffff) * (a >> 16))); + tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); + tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); +} + /* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index 9f49c6e..a861e25 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/intel/speedstep.h> #include "delay.h" -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c index 3768e16..f57f320 100644 --- a/src/northbridge/intel/i5000/udelay.c +++ b/src/northbridge/intel/i5000/udelay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 780c730..3d5d6c6 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 3edd69d..a2ce0d8 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -26,19 +26,6 @@ * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz */ -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. - * This code is used to prevent use of libgcc's umoddi3. - */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - void udelay(u32 us) { u32 dword;

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New patch to review for coreboot: 7eed6d2 libpayload: Fix the logic for hardware-less serial consoles
by Dave Frodin 14 May '13

14 May '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3249 -gerrit commit 7eed6d2f3449636fc56c371f5c539fa1e676ee6e Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue May 14 08:43:25 2013 -0600 libpayload: Fix the logic for hardware-less serial consoles This fixes the configuration where serial console output is being sent to non-existant hardware to be captured with I/O trapping. In this configuration where there isn't serial hardware present we still want to init the consoles. We just never want to read non-existant hardware. Change-Id: Ic51dc574b9c0df3f6ed071086b0fb2119afedc44 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- payloads/libpayload/drivers/serial.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/payloads/libpayload/drivers/serial.c b/payloads/libpayload/drivers/serial.c index df0f2e3..a4cd6d0 100644 --- a/payloads/libpayload/drivers/serial.c +++ b/payloads/libpayload/drivers/serial.c @@ -34,7 +34,7 @@ #define IOBASE lib_sysinfo.serial->baseaddr #define MEMBASE (phys_to_virt(IOBASE)) -static int serial_hardware_is_present = 0; +static int serial_hardware_is_present = 1; static int serial_is_mem_mapped = 0; static uint8_t serial_read_reg(int offset) @@ -105,7 +105,7 @@ void serial_init(void) #ifdef CONFIG_IO_ADDRESS_SPACE if ((inb(IOBASE + 0x05) == 0xFF) && (inb(IOBASE + 0x06) == 0xFF)) { - return; + serial_hardware_is_present = 0; } #else printf("IO space mapped serial not supported."); @@ -113,9 +113,6 @@ void serial_init(void) #endif } - - serial_hardware_is_present = 1; - #ifdef CONFIG_SERIAL_SET_SPEED serial_hardware_init(CONFIG_SERIAL_BAUD_RATE, 8, 0, 1); #endif @@ -125,9 +122,8 @@ void serial_init(void) void serial_putchar(unsigned int c) { - if (!serial_hardware_is_present) - return; - while ((serial_read_reg(0x05) & 0x20) == 0) ; + if (serial_hardware_is_present) + while ((serial_read_reg(0x05) & 0x20) == 0) ; serial_write_reg(c, 0x00); }

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coreboot-gerrit May 2013