coreboot-gerrit May 2013

coreboot-gerrit@coreboot.org

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593 discussions

Patch set updated for coreboot: 8311c9c Make: Use unaltered object list for dependency inclusion
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3258 -gerrit commit 8311c9c1db9626f8f420986beb9b98d64313b5ea Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed May 15 11:47:51 2013 +0200 Make: Use unaltered object list for dependency inclusion It looks like the inclusion of dependency files was broken for all ramstage objects since the list of those gets processed through the ramstage-postprocess macro. Fix that by taking the unaltered list for dependency files. The output of `make printall` (look for DEPENDENCIES=) shows which dependency files will be included. See also: commit 79f9010e80a04f2e0fb0cca5759e3215dff79aff Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Nov 25 14:31:08 2012 +0100 build system: Add hook to postprocess classes (object lists) and: commit f33e395213f0516a9256f33ede4c6bba3babb0e9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Nov 25 17:10:47 2012 +0100 build system: Split linking into multiple steps Change-Id: If93b1773c5d53240f98382aab11bf7f5a4649ee8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9aafe7c..dec32e5 100644 --- a/Makefile +++ b/Makefile @@ -242,6 +242,9 @@ $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs)))) src-to-obj=$(addsuffix .$(1).o, $(basename $(patsubst src/%, $(obj)/%, $($(1)-srcs)))) $(foreach class,$(classes),$(eval $(class)-objs:=$(call src-to-obj,$(class)))) +# Save all objs before processing them (for dependency inclusion) +originalobjs:=$(foreach var, $(addsuffix -objs,$(classes)), $($(var))) + # Call post-processors if they're defined $(foreach class,$(classes),\ $(if $(value $(class)-postprocess),$(eval $(call $(class)-postprocess,$($(class)-objs))))) @@ -273,7 +276,7 @@ $(foreach class,$(classes), \ foreach-src=$(foreach file,$($(1)-srcs),$(eval $(call $(1)-objs_$(subst .,,$(suffix $(file)))_template,$(subst src/,,$(basename $(file)))))) $(eval $(foreach class,$(classes),$(call foreach-src,$(class)))) -DEPENDENCIES = $(allobjs:.o=.d) +DEPENDENCIES = $(originalobjs:.o=.d) -include $(DEPENDENCIES) printall:

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Patch merged into coreboot/master: d433acb AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
by gerrit＠coreboot.org 17 May '13

17 May '13

the following patch was just integrated into master: commit d433acb8164aa836aadd14e00d11ed4dc31b029d Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed May 15 23:31:56 2013 -0600 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer The following commit commit 05f3b117dd44776ed17bc57318f260766039b7e8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue May 14 09:28:26 2013 +0200 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer Reviewed-on: http://review.coreboot.org/3246 changed one calculation for the size of the array PortList[] to reflect only four elements, but neglected three additional calculations of the size of the same table. Correct that by setting the size for four array elements in all four calculations. [1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbP… Change-Id: Ib66b7b2b388d847888663e9eb6d1c8c9d50b9939 Reported-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3250 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/3250 for details. -gerrit

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New patch to review for coreboot: 01bf702 Intel Sandy Bridge: udelay.c: Change comparison from <= to <
by Paul Menzel 17 May '13

17 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3259 -gerrit commit 01bf702129e14941f6fc8692c6110a7bf5a56f1f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 17 17:25:25 2013 +0200 Intel Sandy Bridge: udelay.c: Change comparison from <= to < Currently code in `udelay.c` differs between the Intel northbridges GM45, 945 on the one hand and Sandy Bridge on the other hand. The reason for this is that a wrong comparison > was used. The following commit commit 784ffb3db694dd2c964d9a4e1c6657a835b2d141 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 10 12:16:38 2012 +0100 i945: fix tsc udelay() Reviewed-on: http://review.coreboot.org/530 fixed the sign from > to <, whereas Stefan Reinauer changed it from > to <= before adding the Sandy Bridge port in the following commit. commit 00636b0daefc3c499990744226a0e1a316d71731 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:08:51 2012 +0200 Add support for Intel Sandybridge CPU (northbridge part) Reviewed-on: http://review.coreboot.org/854 As there are no technical reasons for this difference, unify this between the chipsets. See the discussion of the other patch set in Gerrit [1]. [1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/sandybridge/udelay.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 670898a..608726c 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -51,5 +51,5 @@ void udelay(u32 us) do { tsc = rdtsc(); } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); }

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Patch set updated for coreboot: 552292a Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`
by Paul Menzel 17 May '13

17 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3242 -gerrit commit 552292a5ad80c3fd37dcb001bce254a4211ed796 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed May 8 17:08:55 2013 +0200 Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h` multiply_to_tsc was being copied everywhere, which is bad practice. Put it in the tsc.h include file where it belongs. Delete the copies of it. Per secunet, no copyright notice is needed. This might be a good time to get a copyright notice into tsc.h anyway. Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/include/cpu/x86/tsc.h | 13 +++++++++++++ src/northbridge/intel/gm45/delay.c | 12 ------------ src/northbridge/intel/i945/udelay.c | 12 ------------ src/northbridge/intel/sandybridge/udelay.c | 13 ------------- 4 files changed, 13 insertions(+), 37 deletions(-) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8e49a66..66451ad 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -27,6 +27,19 @@ static inline tsc_t rdtsc(void) } #if !defined(__ROMCC__) +/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. + * This code is used to prevent use of libgcc's umoddi3. + */ +static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) +{ + tsc->lo = (a & 0xffff) * (b & 0xffff); + tsc->hi = ((tsc->lo >> 16) + + ((a & 0xffff) * (b >> 16)) + + ((b & 0xffff) * (a >> 16))); + tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); + tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); +} + /* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index 9f49c6e..a861e25 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/intel/speedstep.h> #include "delay.h" -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 780c730..3d5d6c6 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 3edd69d..a2ce0d8 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -26,19 +26,6 @@ * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz */ -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. - * This code is used to prevent use of libgcc's umoddi3. - */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - void udelay(u32 us) { u32 dword;

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Patch set updated for coreboot: 63a0f2f Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`
by Paul Menzel 17 May '13

17 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3220 -gerrit commit 63a0f2f0b6b1a3271e1d5bb9c3415d795f863edb Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 8 17:08:55 2013 +0200 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c` Use the same indentation, comment placement and spelling of words. Run `indent -linux …`. Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/gm45/delay.c | 5 ++--- src/northbridge/intel/i945/udelay.c | 5 ++--- src/northbridge/intel/sandybridge/udelay.c | 4 ++-- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index a861e25..0b5ecd9 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -24,7 +24,7 @@ #include "delay.h" /** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */ static void _udelay(const u32 us, const u32 numerator, const int total) { @@ -62,8 +62,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f; - /* CPU clock is always a quarter. */ - d = ((fsb * divisor) / numerator) / 4; + d = ((fsb * divisor) / numerator) / 4; /* CPU clock is always a quarter. */ multiply_to_tsc(&tscd, us, d); diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 3d5d6c6..60ca9fb 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -24,7 +24,7 @@ #include <cpu/intel/speedstep.h> /** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */ void udelay(u32 us) @@ -63,7 +63,7 @@ void udelay(u32 us) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f; - d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ multiply_to_tsc(&tscd, us, d); @@ -79,5 +79,4 @@ void udelay(u32 us) tsc = rdtsc(); } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); - } diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index a2ce0d8..670898a 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -23,7 +23,7 @@ #include <cpu/x86/msr.h> /** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz */ void udelay(u32 us) @@ -37,7 +37,7 @@ void udelay(u32 us) msr = rdmsr(0xce); divisor = (msr.lo >> 8) & 0xff; - d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ multiply_to_tsc(&tscd, us, d); tsc1 = rdtsc();

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Patch set updated for coreboot: 81fbdcb intel/i5000: Remove unused copy of udelay.c
by Paul Menzel 17 May '13

17 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3219 -gerrit commit 81fbdcb5f7bea6ff74695f1d9f91f7b454bf66a3 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri May 17 15:58:35 2013 +0200 intel/i5000: Remove unused copy of udelay.c It's a copy from i945 and looks like not beeing included in a build at all. If you should ever want to use that file for the Intel 5000, please copy it from another chipset like the Intel 945 as it is going to be improved. Change-Id: I5c113bb0b2fed7b93feb3dcb1b5d962e1442963a Reported-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/i5000/udelay.c | 85 ------------------------------------ 1 file changed, 85 deletions(-) diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c deleted file mode 100644 index ce4c7b3..0000000 --- a/src/northbridge/intel/i5000/udelay.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include <cpu/intel/speedstep.h> - -/** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock - */ - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 0, divisor; - u32 d; /* ticks per us */ - u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ - - msr = rdmsr(MSR_FSB_FREQ); - switch (msr.lo & 0x07) { - case 5: - fsb = 400; - break; - case 1: - fsb = 533; - break; - case 3: - fsb = 667; - break; - case 2: - fsb = 800; - break; - case 0: - fsb = 1067; - break; - case 4: - fsb = 1333; - break; - case 6: - fsb = 1600; - break; - } - - msr = rdmsr(0x198); - divisor = (msr.hi >> 8) & 0x1f; - - d = fsb * divisor; - - tscd.hi = us / dn; - tscd.lo = (us - tscd.hi * dn) * d; - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - tsc = rdtsc(); - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); -}

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Patch set updated for coreboot: c3eab9c Clean up usage of multiply_to_tsc
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3242 -gerrit commit c3eab9c9dea878409c265ce6d64f7d7611d87729 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 8 17:08:55 2013 +0200 Clean up usage of multiply_to_tsc multiply_to_tsc was being copied everywhere, which is bad practice. Put it in the tsc.h include file where it belongs. Delete the copies of it. Per secunet, no copyright notice is needed. This might be a good time to get a copyright notice into tsc.h anyway. Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/include/cpu/x86/tsc.h | 13 +++++++++++++ src/northbridge/intel/gm45/delay.c | 12 ------------ src/northbridge/intel/i945/udelay.c | 12 ------------ src/northbridge/intel/sandybridge/udelay.c | 13 ------------- 4 files changed, 13 insertions(+), 37 deletions(-) diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8e49a66..66451ad 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -27,6 +27,19 @@ static inline tsc_t rdtsc(void) } #if !defined(__ROMCC__) +/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. + * This code is used to prevent use of libgcc's umoddi3. + */ +static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) +{ + tsc->lo = (a & 0xffff) * (b & 0xffff); + tsc->hi = ((tsc->lo >> 16) + + ((a & 0xffff) * (b >> 16)) + + ((b & 0xffff) * (a >> 16))); + tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); + tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); +} + /* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index 9f49c6e..a861e25 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/intel/speedstep.h> #include "delay.h" -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 780c730..3d5d6c6 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 3edd69d..a2ce0d8 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -26,19 +26,6 @@ * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz */ -/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. - * This code is used to prevent use of libgcc's umoddi3. - */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - void udelay(u32 us) { u32 dword;

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Patch set updated for coreboot: b180dd9 Intel 945, 5000, Sandy Bridge: Unify `udelay.c`
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3220 -gerrit commit b180dd9fe8a75173c73858a46a1bff348affd44d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed May 8 17:08:55 2013 +0200 Intel 945, 5000, Sandy Bridge: Unify `udelay.c` 1. Change the comparison from < to <= as done for Sandy Bridge. This is quite controversial and is going to get split out, when Stefan enlightens us all, why he used <= instead of <. 2. Use the same indentation and comment placement. (Run `indent -linux …` too.) 3. Use the same spelling of words. Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/i945/udelay.c | 7 +++---- src/northbridge/intel/sandybridge/udelay.c | 4 ++-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 3d5d6c6..b342222 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -24,7 +24,7 @@ #include <cpu/intel/speedstep.h> /** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */ void udelay(u32 us) @@ -63,7 +63,7 @@ void udelay(u32 us) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f; - d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ multiply_to_tsc(&tscd, us, d); @@ -78,6 +78,5 @@ void udelay(u32 us) do { tsc = rdtsc(); } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); - + || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); } diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index a2ce0d8..670898a 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -23,7 +23,7 @@ #include <cpu/x86/msr.h> /** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz */ void udelay(u32 us) @@ -37,7 +37,7 @@ void udelay(u32 us) msr = rdmsr(0xce); divisor = (msr.lo >> 8) & 0xff; - d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ multiply_to_tsc(&tscd, us, d); tsc1 = rdtsc();

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Patch set updated for coreboot: e6aaf2f intel/i5000: Remove unused copy of udelay.c
by Paul Menzel 17 May '13

17 May '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3219 -gerrit commit e6aaf2fcd8b15753575ab0c068d2465e07df1845 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri May 17 15:58:35 2013 +0200 intel/i5000: Remove unused copy of udelay.c It's a copy from i945 and looks like not being included in a build at all although some changes were made to it. If you should ever want to use that file for the Intel 5000, please copy it from another chipset like the Intel 945 as it is going to be improved. Change-Id: I5c113bb0b2fed7b93feb3dcb1b5d962e1442963a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/i5000/udelay.c | 85 ------------------------------------ 1 file changed, 85 deletions(-) diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c deleted file mode 100644 index ce4c7b3..0000000 --- a/src/northbridge/intel/i5000/udelay.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include <cpu/intel/speedstep.h> - -/** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock - */ - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 0, divisor; - u32 d; /* ticks per us */ - u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ - - msr = rdmsr(MSR_FSB_FREQ); - switch (msr.lo & 0x07) { - case 5: - fsb = 400; - break; - case 1: - fsb = 533; - break; - case 3: - fsb = 667; - break; - case 2: - fsb = 800; - break; - case 0: - fsb = 1067; - break; - case 4: - fsb = 1333; - break; - case 6: - fsb = 1600; - break; - } - - msr = rdmsr(0x198); - divisor = (msr.hi >> 8) & 0x1f; - - d = fsb * divisor; - - tscd.hi = us / dn; - tscd.lo = (us - tscd.hi * dn) * d; - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - tsc = rdtsc(); - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); -}

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Patch set updated for coreboot: 743d55f intel/i5000: Remove unused copy of udelay.c
by Nico Huber 17 May '13

17 May '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3219 -gerrit commit 743d55fd878811d38528a746fb375a5aa1acf794 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri May 17 15:58:35 2013 +0200 intel/i5000: Remove unused copy of udelay.c It's a copy from i945 and looks like not beeing included in a build at all. Change-Id: I5c113bb0b2fed7b93feb3dcb1b5d962e1442963a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/i5000/udelay.c | 85 ------------------------------------ 1 file changed, 85 deletions(-) diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c deleted file mode 100644 index ce4c7b3..0000000 --- a/src/northbridge/intel/i5000/udelay.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <delay.h> -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include <cpu/intel/speedstep.h> - -/** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock - */ - -void udelay(u32 us) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 0, divisor; - u32 d; /* ticks per us */ - u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ - - msr = rdmsr(MSR_FSB_FREQ); - switch (msr.lo & 0x07) { - case 5: - fsb = 400; - break; - case 1: - fsb = 533; - break; - case 3: - fsb = 667; - break; - case 2: - fsb = 800; - break; - case 0: - fsb = 1067; - break; - case 4: - fsb = 1333; - break; - case 6: - fsb = 1600; - break; - } - - msr = rdmsr(0x198); - divisor = (msr.hi >> 8) & 0x1f; - - d = fsb * divisor; - - tscd.hi = us / dn; - tscd.lo = (us - tscd.hi * dn) * d; - - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - - tsc = rdtsc(); - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); -}

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coreboot-gerrit May 2013