coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

1 participants
856 discussions

Patch merged into coreboot/master: 0ce5ebf northbridge/intel/i945/raminit.c: Remove set but unused variable `reg16`
by gerrit＠coreboot.org 05 Nov '13

05 Nov '13

the following patch was just integrated into master: commit 0ce5ebf0a09bfdc7f93737d441cf46899ed1cc79 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Oct 21 21:22:09 2013 +0200 northbridge/intel/i945/raminit.c: Remove set but unused variable `reg16` Change-Id: Id4a758644a7b799e7662113c07d395e053525934 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3984 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3984 for details. -gerrit

1 0

Patch merged into coreboot/master: bf22338 southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3`
by gerrit＠coreboot.org 05 Nov '13

05 Nov '13

the following patch was just integrated into master: commit bf22338a0957bb7af765e112dc0c892b119ee525 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Oct 20 00:41:28 2013 +0200 southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3` Change-Id: I6bb652419a54b7b7190e417346581f38335425ae Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3985 for details. -gerrit

1 0

Patch merged into coreboot/master: b0aec8f usbdebug: Fix build for ROMCC boards
by gerrit＠coreboot.org 05 Nov '13

05 Nov '13

the following patch was just integrated into master: commit b0aec8f070053284a750f07d0fe6f1b37bac83d1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Oct 30 15:03:25 2013 +0200 usbdebug: Fix build for ROMCC boards Header file is not compatible with romcc, just drop it as a romstage built with romcc cannot use usbdebug anyway. Change-Id: If7f8f22d6a8fa1f02157df281f82f02b72b6a609 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/4006 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4006 for details. -gerrit

1 0

Patch set updated for coreboot: 18f1aae AMD Hudson: Move function s3_resume_init_data to southbridge
by Zheng Bao 05 Nov '13

05 Nov '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3932 -gerrit commit 18f1aaead80acd6e2c81f41f8fc6178781c62f8c Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 5 13:58:50 2013 +0800 AMD Hudson: Move function s3_resume_init_data to southbridge Besides the AGESA static settings, the settings in mainboard/buildOpt.c also change the final configuration. We need to make sure the settings in FchParam in resume stage are the same as they were in cold boot stage, otherwise the board can not wake up more than once. Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180. (USB keyboard doesn't work when board wakes up. It is not introduced by this patch. It needs more debugging.) Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/mainboard/amd/olivehill/agesawrapper.c | 56 +---------- src/mainboard/amd/parmer/agesawrapper.c | 58 +----------- src/mainboard/amd/thatcher/agesawrapper.c | 56 +---------- src/mainboard/asrock/imb-a180/agesawrapper.c | 56 +---------- src/mainboard/asus/f2a85-m/agesawrapper.c | 57 +----------- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/hudson.h | 3 + src/southbridge/amd/agesa/hudson/resume.c | 128 ++++++++++++++++++++++++++ 8 files changed, 144 insertions(+), 271 deletions(-) diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index 06405ad..f0ad493 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -43,6 +43,8 @@ #include <cbmem.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/device.h> +#include "hudson.h" VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -523,58 +525,6 @@ UINT32 agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ - -extern FCH_DATA_BLOCK InitEnvCfgDefault; -STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) -{ - FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; - FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; - FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; - FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; - FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; - FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; - FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; - FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; - FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; - FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ - FchParams->Gpp.GppPhyPllPowerDown = TRUE; - FchParams->Gpp.GppDynamicPowerSaving = TRUE; - FchParams->Gpp.UmiPhyPllPowerDown = TRUE; - FchParams->Gpp.NewGppAlgorithm = TRUE; - FchParams->Gpp.GppPortMinPollingTime = 40; - - FchParams->Spi.SpiSpeed = 2; - FchParams->Ir.IrConfig = 3; - - FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; - FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; - FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; - FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; - FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; - FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; - FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; - FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; - FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; - FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; - FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; - FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; - FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; - FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; - FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; - FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; - FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; - FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; - FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; - FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; - FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; - FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; - FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; - FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; - FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; - FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; -} - UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS; @@ -589,7 +539,6 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); @@ -657,7 +606,6 @@ UINT32 agesawrapper_fchs3laterestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); FchInitS3LateRestore(&FchParams); diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index c160106..013df13 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -43,6 +43,8 @@ #include <cbmem.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/device.h> +#include "hudson.h" VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -523,58 +525,6 @@ UINT32 agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ - -extern FCH_DATA_BLOCK InitEnvCfgDefault; -STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) -{ - FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; - FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; - FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; - FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; - FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; - FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; - FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; - FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; - FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; - FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ - FchParams->Gpp.GppPhyPllPowerDown = TRUE; - FchParams->Gpp.GppDynamicPowerSaving = TRUE; - FchParams->Gpp.UmiPhyPllPowerDown = TRUE; - FchParams->Gpp.NewGppAlgorithm = TRUE; - FchParams->Gpp.GppPortMinPollingTime = 40; - - FchParams->Spi.SpiSpeed = 2; - FchParams->Ir.IrConfig = 3; - - FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; - FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; - FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; - FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; - FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; - FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; - FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; - FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; - FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; - FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; - FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; - FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; - FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; - FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; - FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; - FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; - FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; - FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; - FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; - FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; - FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; - FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; - FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; - FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; - FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; - FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; -} - UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS; @@ -589,7 +539,7 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; + //FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); @@ -657,7 +607,7 @@ UINT32 agesawrapper_fchs3laterestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; + //FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); FchInitS3LateRestore(&FchParams); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 9480bdc..6b71ef64 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -43,6 +43,8 @@ #include <cbmem.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/device.h> +#include "hudson.h" VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -523,58 +525,6 @@ UINT32 agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ - -extern FCH_DATA_BLOCK InitEnvCfgDefault; -STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) -{ - FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; - FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; - FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; - FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; - FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; - FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; - FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; - FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; - FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; - FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ - FchParams->Gpp.GppPhyPllPowerDown = TRUE; - FchParams->Gpp.GppDynamicPowerSaving = TRUE; - FchParams->Gpp.UmiPhyPllPowerDown = TRUE; - FchParams->Gpp.NewGppAlgorithm = TRUE; - FchParams->Gpp.GppPortMinPollingTime = 40; - - FchParams->Spi.SpiSpeed = 2; - FchParams->Ir.IrConfig = 3; - - FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; - FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; - FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; - FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; - FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; - FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; - FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; - FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; - FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; - FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; - FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; - FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; - FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; - FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; - FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; - FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; - FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; - FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; - FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; - FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; - FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; - FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; - FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; - FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; - FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; - FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; -} - UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS; @@ -589,7 +539,6 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); @@ -659,7 +608,6 @@ UINT32 agesawrapper_fchs3laterestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); FchInitS3LateRestore(&FchParams); diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 06405ad..f0ad493 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -43,6 +43,8 @@ #include <cbmem.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/device.h> +#include "hudson.h" VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -523,58 +525,6 @@ UINT32 agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ - -extern FCH_DATA_BLOCK InitEnvCfgDefault; -STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) -{ - FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; - FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; - FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; - FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; - FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; - FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; - FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; - FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; - FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; - FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ - FchParams->Gpp.GppPhyPllPowerDown = TRUE; - FchParams->Gpp.GppDynamicPowerSaving = TRUE; - FchParams->Gpp.UmiPhyPllPowerDown = TRUE; - FchParams->Gpp.NewGppAlgorithm = TRUE; - FchParams->Gpp.GppPortMinPollingTime = 40; - - FchParams->Spi.SpiSpeed = 2; - FchParams->Ir.IrConfig = 3; - - FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; - FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; - FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; - FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; - FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; - FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; - FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; - FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; - FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; - FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; - FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; - FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; - FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; - FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; - FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; - FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; - FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; - FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; - FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; - FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; - FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; - FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; - FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; - FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; - FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; - FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; -} - UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS; @@ -589,7 +539,6 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); @@ -657,7 +606,6 @@ UINT32 agesawrapper_fchs3laterestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); FchInitS3LateRestore(&FchParams); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 66b8d4f..b1d6279 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -43,6 +43,8 @@ #include <cbmem.h> #include <arch/acpi.h> #include <arch/io.h> +#include <device/device.h> +#include "hudson.h" VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -525,59 +527,6 @@ UINT32 agesawrapper_amdinitresume(VOID) } #ifndef __PRE_RAM__ - -extern FCH_DATA_BLOCK InitEnvCfgDefault; -STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams) -{ - FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; - FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; - FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; - FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; - FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; - FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; - FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; - FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; - FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; - FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */ - FchParams->Gpp.GppPhyPllPowerDown = TRUE; - FchParams->Gpp.GppDynamicPowerSaving = TRUE; - FchParams->Gpp.UmiPhyPllPowerDown = TRUE; - FchParams->Gpp.NewGppAlgorithm = TRUE; - FchParams->Gpp.GppPortMinPollingTime = 40; - - FchParams->Spi.SpiSpeed = 2; - FchParams->Ir.IrConfig = 3; - - FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; - FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; - FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; - FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; - FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; - FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; - FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; - FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; - FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; - FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; - FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; - FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; - FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; - FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; - FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase; - FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; - FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; - FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; - FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; - FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; - FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; - FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; - FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; - FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; - FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; - FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; - FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; -} - UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS; @@ -592,7 +541,6 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); @@ -662,7 +610,6 @@ UINT32 agesawrapper_fchs3laterestore (VOID) StdHeader.Func = 0; StdHeader.ImageBasePtr = 0; - FchParams = InitEnvCfgDefault; FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); FchInitS3LateRestore(&FchParams); diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index d50d09e..6a097fc 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,6 +17,7 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 686dbb5..e8f80aa 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -21,6 +21,7 @@ #define HUDSON_H #include <device/pci_ids.h> +#include <device/device.h> #include "chip.h" /* Power management index/data registers */ @@ -69,6 +70,8 @@ int acpi_is_wakeup_early(void); #else void hudson_enable(device_t dev); void __attribute__((weak)) hudson_setup_sata_phys(struct device *dev); +void s3_resume_init_data(void *FchParams); + #endif #endif /* HUDSON_H */ diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c new file mode 100644 index 0000000..0d40d6c --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <device/device.h> +#include "hudson.h" +#include "AGESA.h" + +extern FCH_DATA_BLOCK InitEnvCfgDefault; +extern FCH_INTERFACE FchInterfaceDefault; +extern FCH_RESET_DATA_BLOCK InitResetCfgDefault; +extern FCH_RESET_INTERFACE FchResetInterfaceDefault; + +#define DUMP_FCH_SETTING 0 + +void s3_resume_init_data(void *data) +{ + FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)data; + AMD_CONFIG_PARAMS *StdHeader = FchParams->StdHeader; + + *FchParams = InitEnvCfgDefault; + FchParams->StdHeader = StdHeader; + + FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable; + FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable; + FchParams->Spi.SpiFastSpeed = InitResetCfgDefault.FastSpeed; + FchParams->Spi.WriteSpeed = InitResetCfgDefault.WriteSpeed; + FchParams->Spi.SpiMode = InitResetCfgDefault.Mode; + FchParams->Spi.AutoMode = InitResetCfgDefault.AutoMode; + FchParams->Spi.SpiBurstWrite = InitResetCfgDefault.BurstWrite; + FchParams->Sata.SataMode.Sata6AhciCap = (UINT8) InitResetCfgDefault.Sata6AhciCap; + FchParams->Misc.Cg2Pll = InitResetCfgDefault.Cg2Pll; + FchParams->Sata.SataMode.SataSetMaxGen2 = InitResetCfgDefault.SataSetMaxGen2; + FchParams->Sata.SataMode.SataClkMode = InitResetCfgDefault.SataClkMode; + FchParams->Sata.SataMode.SataModeReg = InitResetCfgDefault.SataModeReg; + FchParams->Sata.SataInternal100Spread = (UINT8) InitResetCfgDefault.SataInternal100Spread; + FchParams->Spi.SpiSpeed = InitResetCfgDefault.SpiSpeed; + FchParams->Gpp = InitResetCfgDefault.Gpp; + FchParams->Gpp.GppFunctionEnable = FchResetInterfaceDefault.GppEnable; + + FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; + FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; + FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; + FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; + FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; + FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; + FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; + FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; + FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; + + FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; + FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; + FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; + FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; + FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; + FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; + FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; + FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; + FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; + FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; + FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; + FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; + FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; + FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; + FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; + FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; + FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; + FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; + FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; + FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; + FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; + FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; + FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; + FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; + FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; + FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; + FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; + + FchParams->Sd.SdConfig = FchInterfaceDefault.SdConfig; + FchParams->Azalia.AzaliaEnable = FchInterfaceDefault.AzaliaController; + FchParams->Ir.IrConfig = FchInterfaceDefault.IrConfig; + FchParams->Ab.NbSbGen2 = FchInterfaceDefault.UmiGen2; + FchParams->Sata.SataClass = FchInterfaceDefault.SataClass; + FchParams->Sata.SataMode.SataEnable = FchInterfaceDefault.SataEnable; + FchParams->Sata.SataMode.IdeEnable = FchInterfaceDefault.IdeEnable; + FchParams->Sata.SataIdeMode = FchInterfaceDefault.SataIdeMode; + FchParams->Usb.Ohci1Enable = FchInterfaceDefault.Ohci1Enable; + FchParams->Usb.Ehci1Enable = FchInterfaceDefault.Ohci1Enable; + FchParams->Usb.Ohci2Enable = FchInterfaceDefault.Ohci2Enable; + FchParams->Usb.Ehci2Enable = FchInterfaceDefault.Ohci2Enable; + FchParams->Usb.Ohci3Enable = FchInterfaceDefault.Ohci3Enable; + FchParams->Usb.Ehci3Enable = FchInterfaceDefault.Ohci3Enable; + FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; + FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; + +#if !CONFIG_HUDSON_XHCI_ENABLE + FchParams->Usb.Xhci0Enable = FALSE; +#endif + FchParams->Usb.Xhci1Enable = FALSE; + +#if DUMP_FCH_SETTING + int i; + + for (i = 0; i < sizeof(FchParams); i++) { + printk(BIOS_DEBUG, " %02x", ((u8 *) FchParams)[i]); + if ((i % 16) == 15) + printk(BIOS_DEBUG, "\n"); + } +#endif +}

1 0

Patch merged into coreboot/master: 6583a81 Another pass at board status script
by gerrit＠coreboot.org 04 Nov '13

04 Nov '13

the following patch was just integrated into master: commit 6583a8108ca2cbcb2f363d50bd234e60bc3f4f3e Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Nov 1 19:37:44 2013 -0700 Another pass at board status script This reports relevant bits of information about a machine which is running coreboot. This also includes a script to get revision info from git, which we may want to split out into another patch. A remote target can be specified since it is likely that the machine used to develop the code is not the same machine being developed for. The remote host must be set up for non-interactive root login. Example: sh util/status/status.sh -r gizmoboard -u Change-Id: Ief0a85faca2ec9ce2d270e1e5b09e74836ab0c97 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/4021 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4021 for details. -gerrit

1 0

New patch to review for coreboot: e69ed98 Add imc fan control to Parmer
by WANG Siyuan 04 Nov '13

04 Nov '13

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4025 -gerrit commit e69ed984876cbf5beb8bdc94070cc54f08e1c23f Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Nov 4 18:00:06 2013 +0800 Add imc fan control to Parmer imc can control fan automatically on Parmer. Change-Id: I2609ca6b41cf0b8dec497488344d23f150910622 Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/parmer/Makefile.inc | 1 + src/mainboard/amd/parmer/get_bus_conf.c | 5 +++ src/mainboard/amd/parmer/imc_fan_control.c | 57 ++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc index 3103f70..cfcff53 100644 --- a/src/mainboard/amd/parmer/Makefile.inc +++ b/src/mainboard/amd/parmer/Makefile.inc @@ -26,3 +26,4 @@ ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c +ramstage-y += imc_fan_control.c diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index c92fea9..83e33e7 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" +#include "imc.h" /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. @@ -134,4 +135,8 @@ void get_bus_conf(void) bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_hudson = apicid_base; + +#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) + imc_fan_control(); +#endif } diff --git a/src/mainboard/amd/parmer/imc_fan_control.c b/src/mainboard/amd/parmer/imc_fan_control.c new file mode 100644 index 0000000..6d56d75 --- /dev/null +++ b/src/mainboard/amd/parmer/imc_fan_control.c @@ -0,0 +1,57 @@ +#include <delay.h> +#include "imc.h" + +void imc_func_0x81(void) +{ + write_imc_msg(MSG_REG0, 0x00); + write_imc_msg(MSG_REG1, 0x00); + write_imc_msg(MSG_REG2, 0x3d); + write_imc_msg(MSG_REG3, 0x0e); + write_imc_msg(MSG_REG4, 0x00); + write_imc_msg(MSG_REG5, 0x54); + write_imc_msg(MSG_REG6, 0x98); + write_imc_msg(MSG_REG7, 0x02); + write_imc_msg(MSG_REG8, 0x01); + write_imc_msg(MSG_REG9, 0x00); + write_imc_msg(MSG_SYS_TO_IMC, Fun_81); + mdelay(50); +} + +void imc_func_0x83(void) +{ + write_imc_msg(MSG_REG0, 0x00); + write_imc_msg(MSG_REG1, 0x00); + write_imc_msg(MSG_REG2, 0x46); + write_imc_msg(MSG_REG3, 0x3c); + write_imc_msg(MSG_REG4, 0x32); + write_imc_msg(MSG_REG5, 0xff); + write_imc_msg(MSG_REG6, 0xff); + write_imc_msg(MSG_REG7, 0xff); + write_imc_msg(MSG_REG8, 0xff); + write_imc_msg(MSG_REG9, 0xff); + write_imc_msg(MSG_REGA, 0x4b); + write_imc_msg(MSG_REGB, 0x00); + write_imc_msg(MSG_SYS_TO_IMC, Fun_83); + mdelay(50); +} + +void imc_func_0x85(void) +{ + write_imc_msg(MSG_REG0, 0x00); + write_imc_msg(MSG_REG1, 0x00); + write_imc_msg(MSG_REG2, 0x5a); + write_imc_msg(MSG_REG3, 0x46); + write_imc_msg(MSG_REG4, 0x28); + write_imc_msg(MSG_REG5, 0xff); + write_imc_msg(MSG_REG6, 0xff); + write_imc_msg(MSG_REG7, 0xff); + write_imc_msg(MSG_REG8, 0xff); + write_imc_msg(MSG_REG9, 0xff); + write_imc_msg(MSG_SYS_TO_IMC, Fun_85); + mdelay(50); +} + +void imc_func_0x89(void) +{ + /* not use */ +}

1 0

New patch to review for coreboot: 1bdaa70 Add imc fan control to Olive Hill
by WANG Siyuan 04 Nov '13

04 Nov '13

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4024 -gerrit commit 1bdaa7074c243d6e44e3270ce4184840ab655a33 Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Nov 4 17:57:37 2013 +0800 Add imc fan control to Olive Hill imc can control fan automatically on Olive Hill. Change-Id: I36c7ded4cd9ac0f3ffd75d3f08f94492eb0050ce Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/olivehill/BiosCallOuts.c | 122 +------------------------- src/mainboard/amd/olivehill/Makefile.inc | 1 + src/mainboard/amd/olivehill/get_bus_conf.c | 5 ++ src/mainboard/amd/olivehill/imc_fan_control.c | 57 ++++++++++++ 4 files changed, 64 insertions(+), 121 deletions(-) diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 3fd3684..c142023 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -127,21 +127,8 @@ static const CODEC_TBL_LIST OlivehillCodecTableList[] = * if other software switch the I2C switch by mistake or intention. * We recommend to using IMC to control Fans, instead of HWM. */ -#if 0 static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - FCH_HWM_FAN_CTR oem_factl[5] = { - /*temperatuer input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ - /* Olivehill FanOUT0 Fan header J32 */ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - /* Olivehill FanOUT1 Fan header J31*/ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); - /* Enable IMC fan control. the recommand way */ #if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ @@ -152,112 +139,6 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; - - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; - - /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. - */ - #else /* HWM fan control, the way not recommand */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; @@ -265,7 +146,6 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) #endif /* CONFIG_HUDSON_IMC_FWM */ } -#endif /** * Fch Oem setting callback @@ -290,7 +170,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) /* Azalia Controller Front Panel OEM Table Pointer */ /* Fan Control */ - //oem_fan_control(FchParams_env); + oem_fan_control(FchParams_env); /* XHCI configuration */ #if CONFIG_HUDSON_XHCI_ENABLE diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc index a83297a..fc4b335 100644 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ b/src/mainboard/amd/olivehill/Makefile.inc @@ -26,3 +26,4 @@ ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c +ramstage-y += imc_fan_control.c diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index a380872..aec8b02 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -25,6 +25,7 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" +#include "imc.h" /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. @@ -145,4 +146,8 @@ void get_bus_conf(void) bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_yangtze = apicid_base; + +#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) + imc_fan_control(); +#endif } diff --git a/src/mainboard/amd/olivehill/imc_fan_control.c b/src/mainboard/amd/olivehill/imc_fan_control.c new file mode 100644 index 0000000..85735ba --- /dev/null +++ b/src/mainboard/amd/olivehill/imc_fan_control.c @@ -0,0 +1,57 @@ +#include <delay.h> +#include "imc.h" + +void imc_func_0x81(void) +{ + write_imc_msg(MSG_REG0, 0x00); + write_imc_msg(MSG_REG1, 0x00); + write_imc_msg(MSG_REG2, 0x3d); + write_imc_msg(MSG_REG3, 0x4e); + write_imc_msg(MSG_REG4, 0x00); + write_imc_msg(MSG_REG5, 0x04); + write_imc_msg(MSG_REG6, 0x9a); + write_imc_msg(MSG_REG7, 0x01); + write_imc_msg(MSG_REG8, 0x01); + write_imc_msg(MSG_REG9, 0x00); + write_imc_msg(MSG_SYS_TO_IMC, Fun_81); + mdelay(50); +} + +void imc_func_0x83(void) +{ + write_imc_msg(MSG_REG0, 0x00); + write_imc_msg(MSG_REG1, 0x00); + write_imc_msg(MSG_REG2, 0x46); + write_imc_msg(MSG_REG3, 0x3c); + write_imc_msg(MSG_REG4, 0x32); + write_imc_msg(MSG_REG5, 0xff); + write_imc_msg(MSG_REG6, 0xff); + write_imc_msg(MSG_REG7, 0xff); + write_imc_msg(MSG_REG8, 0xff); + write_imc_msg(MSG_REG9, 0xff); + write_imc_msg(MSG_REGA, 0x4b); + write_imc_msg(MSG_REGB, 0x00); + write_imc_msg(MSG_SYS_TO_IMC, Fun_83); + mdelay(50); +} + +void imc_func_0x85(void) +{ + write_imc_msg(MSG_REG0, 0x00); + write_imc_msg(MSG_REG1, 0x00); + write_imc_msg(MSG_REG2, 0x5a); + write_imc_msg(MSG_REG3, 0x46); + write_imc_msg(MSG_REG4, 0x28); + write_imc_msg(MSG_REG5, 0xff); + write_imc_msg(MSG_REG6, 0xff); + write_imc_msg(MSG_REG7, 0xff); + write_imc_msg(MSG_REG8, 0xff); + write_imc_msg(MSG_REG9, 0xff); + write_imc_msg(MSG_SYS_TO_IMC, Fun_85); + mdelay(50); +} + +void imc_func_0x89(void) +{ + /* not use */ +}

1 0

New patch to review for coreboot: 0115898 AMD hudson: add imc fan control
by WANG Siyuan 04 Nov '13

04 Nov '13

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4023 -gerrit commit 0115898369726593ff6e484504cbe2ece283e1fa Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Mon Nov 4 17:49:07 2013 +0800 AMD hudson: add imc fan control Add fan control related registers initialization in southbridge. Change-Id: Iaf287aeb84b033f14620fad76665d74f5551fe7e Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/imc.c | 40 +++++++++++++++++++++++++++ src/southbridge/amd/agesa/hudson/imc.h | 14 ++++++++++ 3 files changed, 55 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index d50d09e..3d4d995 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -9,6 +9,7 @@ ramstage-y += hda.c ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += imc.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c new file mode 100644 index 0000000..57b3fee --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -0,0 +1,40 @@ +#include "imc.h" +#include "amdlib.h" + +void imc_fan_control(void) +{ + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff); + +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff); + write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff); +#endif + +#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE + UINT8 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 0x3, 0x1E4); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); + PciData &= (UINT8)0x8F; + PciData |= 0x10; + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); +#endif + + imc_func_0x83(); + imc_func_0x85(); + imc_func_0x81(); +} + +void write_imc_msg(u8 idx, u8 val) +{ + outb(idx, 0x3e); + outb(val, 0x3f); +} diff --git a/src/southbridge/amd/agesa/hudson/imc.h b/src/southbridge/amd/agesa/hudson/imc.h new file mode 100644 index 0000000..c7a134b --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/imc.h @@ -0,0 +1,14 @@ +#ifndef _IMC_FAN_CONTROL_H_ +#define _IMC_FAN_CONTROL_H_ + +#include <arch/io.h> +#include "FchPlatform.h" + +void imc_fan_control(void); +void write_imc_msg(u8 idx, u8 val); +void imc_func_0x81(void); +void imc_func_0x83(void); +void imc_func_0x85(void); +void imc_func_0x89(void); + +#endif

1 0

Patch set updated for coreboot: 0e43c0e lenovo/x60: export reboot_bits nvram configuration.
by Denis Carikli 03 Nov '13

03 Nov '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3992 -gerrit commit 0e43c0e8d36a83fa46e62d5ef6c008ff5e9ead0d Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat Oct 26 22:35:46 2013 +0200 lenovo/x60: export reboot_bits nvram configuration. This permits any software running after the ramstage to tell coreboot that the boot was successfull. Change-Id: I6b19160dcf1ea1948360db71d02e344a3bcb44ef Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/cmos.layout | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index ab51a84..a6e1a4c 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -71,7 +71,7 @@ entries # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 385 1 e 4 last_boot -388 4 r 0 reboot_bits +388 4 h 0 reboot_bits #390 2 r 0 unused? # -----------------------------------------------------------------

1 0

Patch set updated for coreboot: 8611263 X86 Kconfig: Make the MAX_REBOOT_CNT selectable in X86_BOOTBLOCK_NORMAL mode.
by Denis Carikli 03 Nov '13

03 Nov '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3991 -gerrit commit 861126370589f69af0bb46c3748cc90ced3f7fb2 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Oct 20 23:37:35 2013 +0200 X86 Kconfig: Make the MAX_REBOOT_CNT selectable in X86_BOOTBLOCK_NORMAL mode. src/arch/x86/Kconfig defined MAX_REBOOT_CNT as 3. In the bootblock, the reboot_bits cmos option is increased by one at each boot. If the boot is successful, the respective nvram settings have to be reset to boot on the normal/ prefix next time. If KEEP_BOOT_COUNT is selected, it has to be done after the ramstage, if not, it's done in the ramstage. In case of a failed boot, the reboot_bits keeps increasing until it reach KEEP_BOOT_COUNT. Once it is reached, it will swtich to fallback/ at next boot. With KEEP_BOOT_COUNT beeing hidden in make menuconfig, and set to 3, the user probably won't know that coreboot will only switch to fallback after 3 failed boots, and will act as if the computer will not boot anymore with its current coreboot image. This patch makes KEEP_BOOT_COUNT with a default of 1. This patch was tested on the Lenovo X60. Change-Id: I746df11c933dfe62e01e1591479ca96a84907dc0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index b4e8eb0..9cf1e17 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -42,12 +42,6 @@ config STACK_SIZE hex default 0x1000 -# Maximum reboot count -# TODO: Improve description. -config MAX_REBOOT_CNT - int - default 3 - # This is something you almost certainly don't want to mess with. # How many SIPIs do we send when starting up APs and cores? # The answer in 2000 or so was '2'. Nowadays, on many systems, @@ -72,6 +66,20 @@ config X86_BOOTBLOCK_NORMAL endchoice +# Maximum reboot count +config MAX_REBOOT_CNT + int "Number of failed boot attempts before switching back to fallback/" + default 1 + depends on X86_BOOTBLOCK_NORMAL + help + Note that the minimum number of reset a machine has to do to boot + can vary across machines. + If you set it to a number that is less that the machine minimum, + the machine will then switch to fallback/ during the next boot. + Once in fallback/, the machine will keep that settings unless + the nvram is reset, which will make it switch to fallback/ + again during the next boot. + config KEEP_BOOT_COUNT bool "Keep boot count" default n

1 0

← Newer
1
...
78
79
80
81
82
83
84
85
86
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2013