coreboot-gerrit November 2013

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 8edc447 intel/2065x: Use TSC for udelay()
by Vladimir Serbinenko 12 Nov '13

12 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4043 -gerrit commit 8edc4473487357698c0889f85ba60e21069bc666 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 12 21:59:10 2013 +0100 intel/2065x: Use TSC for udelay() For the ram init of Intel Nehalem ram init we need a udelay implementation. Use common TSC framework for it as Intel Haswell already does. Change-Id: I360a6db1ec1ba32c92698a7d6f6968c93ead5c52 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/model_2065x/Kconfig | 3 ++- src/cpu/intel/model_2065x/Makefile.inc | 6 ++++++ src/cpu/intel/model_2065x/tsc_freq.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 019309d..b0f4e65 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select HAVE_INIT_TIMER select CPU_MICROCODE_IN_CBFS diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 963fb1b..3b3fc4e 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -3,10 +3,16 @@ subdirs-y += ../../x86/name subdirs-y += ../../x86/cache subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/tsc subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode subdirs-y += ../../x86/smm + +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c + ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/cpu/intel/model_2065x/tsc_freq.c b/src/cpu/intel/model_2065x/tsc_freq.c new file mode 100644 index 0000000..7d388be --- /dev/null +++ b/src/cpu/intel/model_2065x/tsc_freq.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "model_2065x.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff); +}

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New patch to review for coreboot: 062b82c Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.
by Vladimir Serbinenko 12 Nov '13

12 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4045 -gerrit commit 062b82c0deba7c9633ca54aebefbf972d6b490d2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 12 23:32:52 2013 +0100 Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x. 2065x is with nehalem and not sandybridge. I don't care much eitherway but it clears some confusion. Change-Id: I0ce8574db66990f529a123ae984a4ecda497f5a1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/model_2065x/acpi.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x.h | 2 +- src/cpu/intel/model_2065x/model_2065x_init.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 8483812..fa0dc95 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -237,7 +237,7 @@ static int generate_P_state_entries(int core, int cores_per_package) /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * SANDYBRIDGE_BCLK + ratio_max / 3; + clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3; /* Calculate CPU TDP in mW */ power_max = 25000; @@ -298,7 +298,7 @@ static int generate_P_state_entries(int core, int cores_per_package) /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * SANDYBRIDGE_BCLK + ratio / 3; + clock = ratio * NEHALEM_BCLK + ratio / 3; len_pss += acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 18a45d8..813548e 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -23,7 +23,7 @@ #define _CPU_INTEL_MODEL_2065X_H /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ -#define SANDYBRIDGE_BCLK 133 +#define NEHALEM_BCLK 133 #define IA32_FEATURE_CONTROL 0x3a #define CPUID_VMX (1 << 5) diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 4c88e44..0fd1bf0 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -311,7 +311,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK); } static void set_energy_perf_bias(u8 policy)

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Patch set updated for coreboot: 5bb4493 intel/2065x: Use TSC for udelay()
by Paul Menzel 12 Nov '13

12 Nov '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4043 -gerrit commit 5bb4493032e6b238fcdcafd721d3a4088b18bfe3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 12 21:59:10 2013 +0100 intel/2065x: Use TSC for udelay() For the ram init of Intel Nehalem ram init we need a udelay implementation. Use common TSC framework for it as Intel Haswell already does. Change-Id: I360a6db1ec1ba32c92698a7d6f6968c93ead5c52 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/model_2065x/Kconfig | 3 ++- src/cpu/intel/model_2065x/Makefile.inc | 6 ++++++ src/cpu/intel/model_2065x/tsc_freq.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 019309d..b0f4e65 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select HAVE_INIT_TIMER select CPU_MICROCODE_IN_CBFS diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 963fb1b..3b3fc4e 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -3,10 +3,16 @@ subdirs-y += ../../x86/name subdirs-y += ../../x86/cache subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/tsc subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode subdirs-y += ../../x86/smm + +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c + ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/cpu/intel/model_2065x/tsc_freq.c b/src/cpu/intel/model_2065x/tsc_freq.c new file mode 100644 index 0000000..7d388be --- /dev/null +++ b/src/cpu/intel/model_2065x/tsc_freq.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "model_2065x.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff); +}

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New patch to review for coreboot: 727e444 Support for nehalem northbridge
by Vladimir Serbinenko 12 Nov '13

12 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4044 -gerrit commit 727e444f797fd017f1b96813c7e3c27182fcb1ed Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 12 22:32:08 2013 +0100 Support for nehalem northbridge Including raminit. Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/x86/smm/smmhandler_tseg.S | 3 + src/cpu/x86/smm/smmrelocate.S | 3 + src/northbridge/intel/Kconfig | 1 + src/northbridge/intel/Makefile.inc | 1 + src/northbridge/intel/nehalem/Kconfig | 82 + src/northbridge/intel/nehalem/Makefile.inc | 33 + src/northbridge/intel/nehalem/acpi.c | 197 + src/northbridge/intel/nehalem/acpi/hostbridge.asl | 350 ++ src/northbridge/intel/nehalem/acpi/igd.asl | 341 ++ src/northbridge/intel/nehalem/acpi/nehalem.asl | 59 + src/northbridge/intel/nehalem/chip.h | 42 + src/northbridge/intel/nehalem/early_init.c | 167 + src/northbridge/intel/nehalem/fake_vbios.c | 1818 +++++++ src/northbridge/intel/nehalem/finalize.c | 56 + src/northbridge/intel/nehalem/gma.c | 785 +++ src/northbridge/intel/nehalem/gma.h | 168 + src/northbridge/intel/nehalem/nehalem.h | 628 +++ src/northbridge/intel/nehalem/northbridge.c | 446 ++ src/northbridge/intel/nehalem/raminit.c | 5276 +++++++++++++++++++++ src/northbridge/intel/nehalem/raminit.h | 28 + src/northbridge/intel/nehalem/raminit_fake.c | 2056 ++++++++ src/northbridge/intel/nehalem/raminit_tables.c | 1278 +++++ 22 files changed, 13818 insertions(+) diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index eb5d63c..fdc5053 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -60,6 +60,9 @@ #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE #include <northbridge/intel/sandybridge/sandybridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM +#include <northbridge/intel/nehalem/nehalem.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #elif CONFIG_NORTHBRIDGE_INTEL_HASWELL #include <northbridge/intel/haswell/haswell.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 16d4b9f..6a9fae9 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -48,6 +48,9 @@ #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE #include <northbridge/intel/sandybridge/sandybridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM +#include <northbridge/intel/nehalem/nehalem.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #else #error "Northbridge must define TSEG_BAR." #endif diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index a20f7b0..2a40c15 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -12,5 +12,6 @@ source src/northbridge/intel/i945/Kconfig source src/northbridge/intel/gm45/Kconfig source src/northbridge/intel/sch/Kconfig source src/northbridge/intel/i5000/Kconfig +source src/northbridge/intel/nehalem/Kconfig source src/northbridge/intel/sandybridge/Kconfig source src/northbridge/intel/haswell/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 62e427d..9156b99 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -12,6 +12,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_GM45) += gm45 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += nehalem subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig new file mode 100644 index 0000000..9851061 --- /dev/null +++ b/src/northbridge/intel/nehalem/Kconfig @@ -0,0 +1,82 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_NEHALEM + bool + select CPU_INTEL_MODEL_2065X + select VGA + +if NORTHBRIDGE_INTEL_NEHALEM + +config VGA_BIOS_ID + string + default "8086,0046" + +config CACHE_MRC_SIZE_KB + int + default 256 + +# FIXME: build from rom size +config MRC_CACHE_BASE + hex + default 0xff800000 + +config MRC_CACHE_LOCATION + hex + depends on !CHROMEOS + default 0x500000 + +config MRC_CACHE_SIZE + hex + depends on !CHROMEOS + default 0x10000 + +config DCACHE_RAM_BASE + hex + default 0xff7f0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x4000 + +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 + help + On Sandybridge and Ivybridge systems the firmware image has to + store a lot more than just coreboot, including: + - a firmware descriptor + - Intel Management Engine firmware + - MRC cache information + This option allows to limit the size of the CBFS portion in the + firmware image. + +endif diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc new file mode 100644 index 0000000..d0c7f61 --- /dev/null +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += northbridge.c +ramstage-y += gma.c + +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-y += ../sandybridge/mrccache.c + +romstage-y += raminit.c +romstage-y += early_init.c +romstage-y += ../sandybridge/mrccache.c +romstage-y += ../../../arch/x86/lib/walkcbfs.S + +smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c + +$(obj)/northbridge/intel/calpella/acpi.ramstage.o : $(obj)/build.h diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c new file mode 100644 index 0000000..960a983 --- /dev/null +++ b/src/northbridge/intel/nehalem/acpi.c @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <build.h> +#include "nehalem.h" + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 pciexbar = 0; + u32 pciexbar_reg; + int max_buses; + + dev = dev_find_slot(0xff, PCI_DEVFN(0, 1)); + + pciexbar_reg = read32(0xeff01050); + + // MMCFG not supported or not enabled. + if (!(pciexbar_reg & (1 << 0))) + return current; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + pciexbar = + pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28)); + max_buses = 256; + break; + case 1: // 128M + pciexbar = + pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27)); + max_buses = 128; + break; + case 2: // 64M + pciexbar = + pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27) | (1 << 26)); + max_buses = 64; + break; + default: // RSVD + return current; + } + + if (!pciexbar) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + pciexbar, 0x0, 0x0, max_buses - 1); + + return current; +} + +static void *get_intel_vbios(void) +{ + /* This should probably be looking at CBFS or we should always + * deploy the VBIOS on Intel systems, even if we don't run it + * in coreboot (e.g. SeaBIOS only scenarios). + */ + u8 *vbios = (u8 *) 0xc0000; + + optionrom_header_t *oprom = (optionrom_header_t *) vbios; + optionrom_pcir_t *pcir = (optionrom_pcir_t *) (vbios + + oprom->pcir_offset); + + printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n", + oprom->signature, pcir->vendor, pcir->classcode[0], + pcir->classcode[1], pcir->classcode[2]); + + if ((oprom->signature == OPROM_SIGNATURE) && + (pcir->vendor == PCI_VENDOR_ID_INTEL) && + (pcir->classcode[0] == 0x00) && + (pcir->classcode[1] == 0x00) && (pcir->classcode[2] == 0x03)) + return (void *)vbios; + + return NULL; +} + +static int init_opregion_vbt(igd_opregion_t * opregion) +{ + void *vbios; + vbios = get_intel_vbios(); + if (!vbios) { + printk(BIOS_DEBUG, "VBIOS not found.\n"); + return 1; + } + + printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios); + optionrom_header_t *oprom = (optionrom_header_t *) vbios; + optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset); + + if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) { + printk(BIOS_DEBUG, "VBT not found!\n"); + return 1; + } + + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ? + vbt->hdr_vbt_size : 7168); + + return 0; +} + +/* Initialize IGD OpRegion, called from ACPI code */ +int init_igd_opregion(igd_opregion_t * opregion) +{ + device_t igd; + u16 reg16; + + memset((void *)opregion, 0, sizeof(igd_opregion_t)); + + // FIXME if IGD is disabled, we should exit here. + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8kb */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + // FIXME We just assume we're mobile for now + opregion->header.mailboxes = MAILBOXES_MOBILE; + + // TODO Initialize Mailbox 1 + + // TODO Initialize Mailbox 3 + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + init_opregion_vbt(opregion); + + /* TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + + pci_write_config32(igd, ASLS, (u32) opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + /* clear dmisci status */ + reg16 = inw(DEFAULT_PMBASE + TCO1_STS); + reg16 |= DMISCI_STS; // reference code does an &= + outw(DEFAULT_PMBASE + TCO1_STS, reg16); + + /* clear acpi tco status */ + outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); + + /* enable acpi tco scis */ + reg16 = inw(DEFAULT_PMBASE + GPE0_EN); + reg16 |= TCOSCI_EN; + outw(DEFAULT_PMBASE + GPE0_EN, reg16); + + return 0; +} diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl new file mode 100644 index 0000000..ded393b --- /dev/null +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -0,0 +1,350 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Device (MCHC) +{ + Name(_ADR, 0x00000000) // 0:0.0 + + OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset (0x40), // EPBAR + EPEN, 1, // Enable + , 11, // + EPBR, 24, // EPBAR + + Offset (0x48), // MCHBAR + MHEN, 1, // Enable + , 13, // + MHBR, 22, // MCHBAR + + Offset (0x60), // PCIe BAR + PXEN, 1, // Enable + PXSZ, 2, // BAR size + , 23, // + PXBR, 10, // PCIe BAR + + Offset (0x68), // DMIBAR + DMEN, 1, // Enable + , 11, // + DMBR, 24, // DMIBAR + + + Offset (0xa0), + TOM, 16, + TUUD, 16, + + Offset (0xb0), // Top of Low Used Memory + TLUD, 16, + } + + Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ + Name (CTCC, 0) /* CTDP Current Selection */ + Name (CTCN, 0) /* CTDP Nominal Select */ + Name (CTCD, 1) /* CTDP Down Select */ + Name (CTCU, 2) /* CTDP Up Select */ + + OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + Field (MCHB, DWordAcc, Lock, Preserve) + { + Offset (0x5930), + CTDN, 15, /* CTDP Nominal PL1 */ + Offset (0x59a0), + PL1V, 15, /* Power Limit 1 Value */ + PL1E, 1, /* Power Limit 1 Enable */ + PL1C, 1, /* Power Limit 1 Clamp */ + PL1T, 7, /* Power Limit 1 Time */ + Offset (0x59a4), + PL2V, 15, /* Power Limit 2 Value */ + PL2E, 1, /* Power Limit 2 Enable */ + PL2C, 1, /* Power Limit 2 Clamp */ + PL2T, 7, /* Power Limit 2 Time */ + Offset (0x5f3c), + TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ + Offset (0x5f40), + CTDD, 15, /* CTDP Down PL1 */ + , 1, + TARD, 8, /* CTDP Down Turbo Activation Ratio */ + Offset (0x5f48), + CTDU, 15, /* CTDP Up PL1 */ + , 1, + TARU, 8, /* CTDP Up Turbo Activation Ratio */ + Offset (0x5f50), + CTCS, 2, /* CTDP Select */ + Offset (0x5f54), + TARS, 8, /* Turbo Activation Ratio Select */ + } + + /* + * Search CPU0 _PSS looking for control=arg0 and then + * return previous P-state entry number for new _PPC + * + * Format of _PSS: + * Name (_PSS, Package () { + * Package (6) { freq, power, tlat, blat, control, status } + * } + */ + External (\_PR.CPU0._PSS) + Method (PSSS, 1, NotSerialized) + { + Store (One, Local0) /* Start at P1 */ + Store (SizeOf (\_PR.CPU0._PSS), Local1) + + While (LLess (Local0, Local1)) { + /* Store _PSS entry Control value to Local2 */ + ShiftRight (DeRefOf (Index (DeRefOf (Index + (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + If (LEqual (Local2, Arg0)) { + Return (Subtract (Local0, 1)) + } + Increment (Local0) + } + + Return (0) + } + + /* Set TDP Down */ + Method (STND, 0, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (LEqual (CTCD, CTCC)) { + Release (CTCM) + Return (0) + } + + Store ("Set TDP Down", Debug) + + /* Set CTC */ + Store (CTCD, CTCS) + + /* Set TAR */ + Store (TARD, TARS) + + /* Set PPC limit and notify OS */ + Store (PSSS (TARD), PPCM) + PPCN () + + /* Set PL2 to 1.25 * PL1 */ + Divide (Multiply (CTDD, 125), 100, Local0, PL2V) + + /* Set PL1 */ + Store (CTDD, PL1V) + + /* Store the new TDP Down setting */ + Store (CTCD, CTCC) + + Release (CTCM) + Return (1) + } + + /* Set TDP Nominal from Down */ + Method (STDN, 0, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (LEqual (CTCN, CTCC)) { + Release (CTCM) + Return (0) + } + + Store ("Set TDP Nominal", Debug) + + /* Set PL1 */ + Store (CTDN, PL1V) + + /* Set PL2 to 1.25 * PL1 */ + Divide (Multiply (CTDN, 125), 100, Local0, PL2V) + + /* Set PPC limit and notify OS */ + Store (PSSS (TARN), PPCM) + PPCN () + + /* Set TAR */ + Store (TARN, TARS) + + /* Set CTC */ + Store (CTCN, CTCS) + + /* Store the new TDP Nominal setting */ + Store (CTCN, CTCC) + + Release (CTCM) + Return (1) + } +} + +// Current Resource Settings + +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + 0xfec00000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) + }) + + // Find PCI resource area in MCRS + CreateDwordField(MCRS, PM01._MIN, PMIN) + CreateDwordField(MCRS, PM01._MAX, PMAX) + CreateDwordField(MCRS, PM01._LEN, PLEN) + + // Fix up PCI memory region + // Start with Top of Lower Usable DRAM + Store (^MCHC.TLUD, Local0) + ShiftRight (Local0, 4, Local0) + Store (^MCHC.TUUD, Local1) + + // Check if ME base is equal + If (LEqual (Local0, Local1)) { + // Use Top Of Memory instead + Store (^MCHC.TOM, Local0) + ShiftRight (Local0, 6, Local0) + } + + ShiftLeft (Local0, 20, Local0) + Store (Local0, PMIN) + Add(Subtract(PMAX, PMIN), 1, PLEN) + + Return (MCRS) +} + +/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ +#include "acpi/sandybridge_pci_irqs.asl" + + diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl new file mode 100644 index 0000000..7d3d4db --- /dev/null +++ b/src/northbridge/intel/nehalem/acpi/igd.asl @@ -0,0 +1,341 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64 + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0x48254), + BCLV, 16, + Offset (0xc8250), + CR1, 32, + CR2, 32 + } + + /* Display Output Switching */ + Method (_DOS, 1) + { + /* Windows 2000 and Windows XP call _DOS to enable/disable + * Display Output Switching during init and while a switch + * is already active + */ + Store (And(Arg0, 7), DSEN) + } + + /* We try to support as many i945 systems as possible, + * so keep the number of DIDs flexible. + */ + Method (_DOD, 0) + { + If (LEqual(NDID, 1)) { + Name(DOD1, Package() { + 0xffffffff + }) + Store (Or(0x00010000, DID1), Index(DOD1, 0)) + Return(DOD1) + } + + If (LEqual(NDID, 2)) { + Name(DOD2, Package() { + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID2), Index(DOD2, 0)) + Store (Or(0x00010000, DID2), Index(DOD2, 1)) + Return(DOD2) + } + + If (LEqual(NDID, 3)) { + Name(DOD3, Package() { + 0xffffffff, + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID3), Index(DOD3, 0)) + Store (Or(0x00010000, DID3), Index(DOD3, 1)) + Store (Or(0x00010000, DID3), Index(DOD3, 2)) + Return(DOD3) + } + + If (LEqual(NDID, 4)) { + Name(DOD4, Package() { + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID4), Index(DOD4, 0)) + Store (Or(0x00010000, DID4), Index(DOD4, 1)) + Store (Or(0x00010000, DID4), Index(DOD4, 2)) + Store (Or(0x00010000, DID4), Index(DOD4, 3)) + Return(DOD4) + } + + If (LGreater(NDID, 4)) { + Name(DOD5, Package() { + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff + }) + Store (Or(0x00010000, DID5), Index(DOD5, 0)) + Store (Or(0x00010000, DID5), Index(DOD5, 1)) + Store (Or(0x00010000, DID5), Index(DOD5, 2)) + Store (Or(0x00010000, DID5), Index(DOD5, 3)) + Store (Or(0x00010000, DID5), Index(DOD5, 4)) + Return(DOD5) + } + + /* Some error happened, but we have to return something */ + Return (Package() {0x00000400}) + } + + Device(DD01) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID1, 0)) { + Return (1) + } Else { + Return (And(0xffff, DID1)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 1)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 1)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + Device(DD02) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID2, 0)) { + Return (2) + } Else { + Return (And(0xffff, DID2)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 2)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 2)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + + Device(DD03) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID3, 0)) { + Return (3) + } Else { + Return (And(0xffff, DID3)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 4)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 4)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + + Device(DD04) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID4, 0)) { + Return (4) + } Else { + Return (And(0xffff, DID4)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 8)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 4)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + + + Device(DD05) + { + /* Device Unique ID */ + Method(_ADR, 0, Serialized) + { + If(LEqual(DID5, 0)) { + Return (5) + } Else { + Return (And(0xffff, DID5)) + } + } + + /* Device Current Status */ + Method(_DCS, 0) + { + TRAP(1) + If (And(CSTE, 16)) { + Return (0x1f) + } + Return(0x1d) + } + + /* Query Device Graphics State */ + Method(_DGS, 0) + { + If (And(NSTE, 4)) { + Return(1) + } + Return(0) + } + + /* Device Set State */ + Method(_DSS, 1) + { + /* If Parameter Arg0 is (1 << 31) | (1 << 30), the + * display switch was completed + */ + If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) { + Store (NSTE, CSTE) + } + } + } + +} + diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl new file mode 100644 index 0000000..aa74d0d --- /dev/null +++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "../nehalem.h" +#include "hostbridge.asl" + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + +#if CONFIG_CHROMEOS_RAMOOPS + Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) +#endif + + /* Required for SandyBridge sighting 3715511 */ + Memory32Fixed(ReadWrite, 0x20000000, 0x00200000) + Memory32Fixed(ReadWrite, 0x40000000, 0x00200000) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +// Integrated graphics 0:2.0 +#include "igd.asl" diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h new file mode 100644 index 0000000..16df91b --- /dev/null +++ b/src/northbridge/intel/nehalem/chip.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Digital Port Hotplug Enable: + * 0x04 = Enabled, 2ms short pulse + * 0x05 = Enabled, 4.5ms short pulse + * 0x06 = Enabled, 6ms short pulse + * 0x07 = Enabled, 100ms short pulse + */ +struct northbridge_intel_sandybridge_config { + u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ + u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ + u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ + + u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + + u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ + u32 gpu_pch_backlight; /* PCH Backlight PWM value */ +}; + diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c new file mode 100644 index 0000000..187b4df --- /dev/null +++ b/src/northbridge/intel/nehalem/early_init.c @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <console/console.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <elog.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> +#include <cpu/intel/turbo.h> +#include <arch/cpu.h> + +#include "nehalem.h" + +static void nehalem_setup_bars(void) +{ + /* Setting up Southbridge. In the northbridge code. */ + printk(BIOS_DEBUG, "Setting up static southbridge registers..."); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); + + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + printk(BIOS_DEBUG, " done.\n"); + + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); /* halt timer */ + printk(BIOS_DEBUG, " done.\n"); + + printk(BIOS_DEBUG, "Setting up static northbridge registers..."); + /* Set up all hardcoded northbridge BARs */ + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, + (0LL + DEFAULT_EPBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, + (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ + pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + pci_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, DEFAULT_PCIEXBAR | 1); + + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, + (0LL + DEFAULT_DMIBAR) >> 32); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); + pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33); + pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33); + pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33); + pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33); + pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); + pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); + +#if CONFIG_ELOG_BOOT_COUNT + /* Increment Boot Counter for non-S3 resume */ + if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && + ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) + boot_count_increment(); +#endif + + printk(BIOS_DEBUG, " done.\n"); + +#if CONFIG_ELOG_BOOT_COUNT + /* Increment Boot Counter except when resuming from S3 */ + if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && + ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) + return; + boot_count_increment(); +#endif +} + +static void early_cpu_init (void) +{ + msr_t m; + + /* bit 0 = disable multicore, + bit 1 = disable quadcore, + bit 8 = disable hyperthreading. */ + pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80, + (pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000); + + u8 reg8; + struct cpuid_result result; + result = cpuid_ext(0x6, 0x8b); + if (!(result.eax & 0x2)) { + m = rdmsr(MSR_FSB_CLOCK_VCC); + reg8 = ((m.lo & 0xff00) >> 8) + 1; + m = rdmsr (IA32_PERF_CTL); + m.lo = (m.lo & ~0xff) | reg8; + wrmsr(IA32_PERF_CTL, m); + + m = rdmsr(MSR_IA32_MISC_ENABLES); + m.hi &= ~0x00000040; + m.lo |= 0x10000; + + wrmsr(MSR_IA32_MISC_ENABLES, m); + } + + m = rdmsr(MSR_FSB_CLOCK_VCC); + reg8 = ((m.lo & 0xff00) >> 8) + 1; + + m = rdmsr (IA32_PERF_CTL); + m.lo = (m.lo & ~0xff) | reg8; + wrmsr(IA32_PERF_CTL, m); + + m = rdmsr(MSR_IA32_MISC_ENABLES); + m.lo |= 0x10000; + wrmsr(MSR_IA32_MISC_ENABLES, m); + + m = rdmsr(0x1f1); + m.lo |= 1; + wrmsr(0x1f1, m); + +} + +void nehalem_early_initialization(int chipset_type) +{ + u32 capid0_a; + u8 reg8; + + /* Device ID Override Enable should be done very early */ + capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); + if (capid0_a & (1 << 10)) { + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == NEHALEM_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); + } + + /* Setup all BARs required for early PCIe and raminit */ + nehalem_setup_bars(); + + /* Device Enable */ + pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, 9 | 2); + + early_cpu_init(); + + pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR); + pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} diff --git a/src/northbridge/intel/nehalem/fake_vbios.c b/src/northbridge/intel/nehalem/fake_vbios.c new file mode 100644 index 0000000..e10d52d --- /dev/null +++ b/src/northbridge/intel/nehalem/fake_vbios.c @@ -0,0 +1,1818 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +my_outb (0x03c2, 0x23); // Device I/O <-- +my_outb (0x03da, 0x02); // Device I/O <-- +my_inb (0x03c2); // Device I/O --> 10 +my_outb (0x03da, 0x01); // Device I/O <-- +my_inb (0x03c2); // Device I/O --> 10 +my_outl (0x1040, 0x00070080); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x00070180); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x00071180); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x00041000); // Device I/O +my_inl (0x1044); // Device I/O --> 00002900 +my_outl (0x1044, 0x8000298e); // Device I/O +my_outl (0x1040, 0x0007019c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0007119c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x00000000); // Device I/O +my_inl (0x1044); // Device I/O --> ffffffff +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x00000000); // Device I/O +my_inl (0x1044); // Device I/O --> ffffffff +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x00000000); // Device I/O +my_inl (0x1044); // Device I/O --> ffffffff +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x00000000); // Device I/O +my_inl (0x1044); // Device I/O --> ffffffff +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x00000000); // Device I/O +my_inl (0x1044); // Device I/O --> ffffffff +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x000fc008); // Device I/O +my_inl (0x1044); // Device I/O --> 2c010757 +my_outl (0x1044, 0x2c010000); // Device I/O +my_outl (0x1040, 0x000fc020); // Device I/O +my_inl (0x1044); // Device I/O --> 2c010757 +my_outl (0x1044, 0x2c010000); // Device I/O +my_outl (0x1040, 0x000fc038); // Device I/O +my_inl (0x1044); // Device I/O --> 2c010757 +my_outl (0x1044, 0x2c010000); // Device I/O +my_outl (0x1040, 0x000fc050); // Device I/O +my_inl (0x1044); // Device I/O --> 2c010757 +my_outl (0x1044, 0x2c010000); // Device I/O +my_outl (0x1040, 0x000fc408); // Device I/O +my_inl (0x1044); // Device I/O --> 2c010757 +my_outl (0x1044, 0x2c010000); // Device I/O +my_outl (0x1040, 0x000fc420); // Device I/O +my_inl (0x1044); // Device I/O --> 2c010757 +my_outl (0x1044, 0x2c010000); // Device I/O +my_outl (0x1040, 0x000fc438); // Device I/O +my_inl (0x1044); // Device I/O --> 2c010757 +my_outl (0x1044, 0x2c010000); // Device I/O +my_outl (0x1040, 0x000fc450); // Device I/O +my_inl (0x1044); // Device I/O --> 2c010757 +my_outl (0x1044, 0x2c010000); // Device I/O +my_outw (0x03ce, 0x0018); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x01000001); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f048); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x03030000); // Device I/O +my_outl (0x1040, 0x0004f050); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f054); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000001); // Device I/O +my_outl (0x1040, 0x0004f058); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1044, 0x03030000); // Device I/O +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1044, 0x03030000); // Device I/O +my_outl (0x1040, 0x00042004); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x02000000); // Device I/O +my_outl (0x1040, 0x000fd034); // Device I/O +my_inl (0x1044); // Device I/O --> 39cfffe0 +my_outl (0x1044, 0x8421ffe0); // Device I/O +int i; +for (i = 0; i < 0x1fff; i++) + { + my_outl (0x1040, 0x00000001 | (i << 2)); // Device I/O + my_outl (0x1044, 0xc2000001 | (i << 12)); // Device I/O + } + +my_outw (0x03c4, 0x0302); // Device I/O +my_outw (0x03c4, 0x0003); // Device I/O +my_outw (0x03c4, 0x0204); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outw (0x03c4, 0x0300); // Device I/O +my_outb (0x03c2, 0x67); // Device I/O <-- +my_outb (0x03d4, 0x11); // Device I/O <-- +my_inw (0x03d4); // Device I/O --> 0x0011 +my_outw (0x03d4, 0x0011); // Device I/O +my_outw (0x03d4, 0x5f00); // Device I/O +my_outw (0x03d4, 0x4f01); // Device I/O +my_outw (0x03d4, 0x5002); // Device I/O +my_outw (0x03d4, 0x8203); // Device I/O +my_outw (0x03d4, 0x5504); // Device I/O +my_outw (0x03d4, 0x8105); // Device I/O +my_outw (0x03d4, 0xbf06); // Device I/O +my_outw (0x03d4, 0x1f07); // Device I/O +my_outw (0x03d4, 0x0008); // Device I/O +my_outw (0x03d4, 0x4f09); // Device I/O +my_outw (0x03d4, 0x0d0a); // Device I/O +my_outw (0x03d4, 0x0e0b); // Device I/O +my_outw (0x03d4, 0x000c); // Device I/O +my_outw (0x03d4, 0x000d); // Device I/O +my_outw (0x03d4, 0x000e); // Device I/O +my_outw (0x03d4, 0x000f); // Device I/O +my_outw (0x03d4, 0x9c10); // Device I/O +my_outw (0x03d4, 0x8e11); // Device I/O +my_outw (0x03d4, 0x8f12); // Device I/O +my_outw (0x03d4, 0x2813); // Device I/O +my_outw (0x03d4, 0x1f14); // Device I/O +my_outw (0x03d4, 0x9615); // Device I/O +my_outw (0x03d4, 0xb916); // Device I/O +my_outw (0x03d4, 0xa317); // Device I/O +my_outw (0x03d4, 0xff18); // Device I/O +my_inb (0x03da); // Device I/O --> 31 +my_inb (0x03ba); // Device I/O --> ff +my_inb (0x03da); // Device I/O --> 21 +my_inb (0x03ba); // Device I/O --> ff +my_inb (0x03da); // Device I/O --> 01 +my_inb (0x03ba); // Device I/O --> ff +my_outw (0x03ce, 0x0000); // Device I/O +my_outw (0x03ce, 0x0001); // Device I/O +my_outw (0x03ce, 0x0002); // Device I/O +my_outw (0x03ce, 0x0003); // Device I/O +my_outw (0x03ce, 0x0004); // Device I/O +my_outw (0x03ce, 0x1005); // Device I/O +my_outw (0x03ce, 0x0e06); // Device I/O +my_outw (0x03ce, 0x0007); // Device I/O +my_outw (0x03ce, 0xff08); // Device I/O +my_outl (0x1040, 0x000e1100); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000e1100); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x000e1100); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00010000); // Device I/O +my_outl (0x1040, 0x000e1100); // Device I/O +my_inl (0x1044); // Device I/O --> 00010000 +my_outl (0x1040, 0x000e1100); // Device I/O +my_inl (0x1044); // Device I/O --> 00010000 +my_outl (0x1040, 0x000e1100); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000e1100); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x000e1100); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f054); // Device I/O +my_inl (0x1044); // Device I/O --> 00000001 +my_outl (0x1040, 0x0004f054); // Device I/O +my_inl (0x1044); // Device I/O --> 00000001 +my_outl (0x1044, 0x00000001); // Device I/O +my_outl (0x1040, 0x000e4200); // Device I/O +my_inl (0x1044); // Device I/O --> 0000001c +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 00050000 +my_outl (0x1044, 0x8004003e); // Device I/O +my_outl (0x1040, 0x000e4214); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x80060002); // Device I/O +my_outl (0x1040, 0x000e4218); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x01000000); // Device I/O +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1044, 0x5344003e); // Device I/O +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 0144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 0144003e +my_outl (0x1044, 0x8074003e); // Device I/O +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1044, 0x5344003e); // Device I/O +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 0144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 0144003e +my_outl (0x1044, 0x8074003e); // Device I/O +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1044, 0x5344003e); // Device I/O +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 0144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 0144003e +my_outl (0x1044, 0x8074003e); // Device I/O +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1040, 0x000e4210); // Device I/O +my_inl (0x1044); // Device I/O --> 5144003e +my_outl (0x1044, 0x5344003e); // Device I/O +my_outl (0x1040, 0x000e4f00); // Device I/O +my_inl (0x1044); // Device I/O --> 0100038e +my_outl (0x1044, 0x0100030c); // Device I/O +my_outl (0x1040, 0x000e4f04); // Device I/O +my_inl (0x1044); // Device I/O --> 00b8338e +my_outl (0x1044, 0x00b8230c); // Device I/O +my_outl (0x1040, 0x000e4f08); // Device I/O +my_inl (0x1044); // Device I/O --> 0178838e +my_outl (0x1044, 0x06f8930c); // Device I/O +my_outl (0x1040, 0x000e4f0c); // Device I/O +my_inl (0x1044); // Device I/O --> 09f8e38e +my_outl (0x1044, 0x09f8e38e); // Device I/O +my_outl (0x1040, 0x000e4f10); // Device I/O +my_inl (0x1044); // Device I/O --> 00b8038e +my_outl (0x1044, 0x00b8030c); // Device I/O +my_outl (0x1040, 0x000e4f14); // Device I/O +my_inl (0x1044); // Device I/O --> 0978838e +my_outl (0x1044, 0x0b78830c); // Device I/O +my_outl (0x1040, 0x000e4f18); // Device I/O +my_inl (0x1044); // Device I/O --> 09f8b38e +my_outl (0x1044, 0x0ff8d3cf); // Device I/O +my_outl (0x1040, 0x000e4f1c); // Device I/O +my_inl (0x1044); // Device I/O --> 0178038e +my_outl (0x1044, 0x01e8030c); // Device I/O +my_outl (0x1040, 0x000e4f20); // Device I/O +my_inl (0x1044); // Device I/O --> 09f8638e +my_outl (0x1044, 0x0ff863cf); // Device I/O +my_outl (0x1040, 0x000e4f24); // Device I/O +my_inl (0x1044); // Device I/O --> 09f8038e +my_outl (0x1044, 0x0ff803cf); // Device I/O +my_outl (0x1040, 0x000c4030); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00001000); // Device I/O +my_outl (0x1040, 0x000c4000); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000c4030); // Device I/O +my_inl (0x1044); // Device I/O --> 00001000 +my_outl (0x1044, 0x00001000); // Device I/O +my_outl (0x1040, 0x000e1150); // Device I/O +my_inl (0x1044); // Device I/O --> 0000001c +my_outl (0x1040, 0x000e1150); // Device I/O +my_inl (0x1044); // Device I/O --> 0000001c +my_outl (0x1044, 0x0000089c); // Device I/O +my_outl (0x1040, 0x000fcc00); // Device I/O +my_inl (0x1044); // Device I/O --> 01773f30 +my_outl (0x1044, 0x01986f00); // Device I/O +my_outl (0x1040, 0x000fcc0c); // Device I/O +my_inl (0x1044); // Device I/O --> 01773f30 +my_outl (0x1044, 0x01986f00); // Device I/O +my_outl (0x1040, 0x000fcc18); // Device I/O +my_inl (0x1044); // Device I/O --> 01773f30 +my_outl (0x1044, 0x01986f00); // Device I/O +my_outl (0x1040, 0x000fcc24); // Device I/O +my_inl (0x1044); // Device I/O --> 01773f30 +my_outl (0x1044, 0x01986f00); // Device I/O +my_outl (0x1040, 0x000c4000); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000e1180); // Device I/O +my_inl (0x1044); // Device I/O --> 40000002 +my_inb (0x03d4); // Device I/O --> 18 +my_inb (0x03d6); // Device I/O --> ff +my_inb (0x03d0); // Device I/O --> ff +my_inb (0x03ce); // Device I/O --> 08 +my_inb (0x03d2); // Device I/O --> ff +my_inb (0x03c4); // Device I/O --> 00 +my_inb (0x03c7); // Device I/O --> 00 +my_inb (0x03c8); // Device I/O --> 00 +my_outb (0x03c4, 0x01); // Device I/O <-- +my_inw (0x03c4); // Device I/O --> 0x2001 +my_outw (0x03c4, 0x2001); // Device I/O +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00000800 +my_outl (0x1040, 0x000c5100); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000003); // Device I/O +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008800 +my_outl (0x1040, 0x000c5120); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x000c5104); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x460000a0); // Device I/O +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 0000ca00 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 0000ca00 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 0000ca00 +my_outl (0x1040, 0x000c5120); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x000c5104); // Device I/O +my_inl (0x1044); // Device I/O --> 060000a0 +my_outl (0x1044, 0x4a8000a1); // Device I/O +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a08 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a08 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> ffffff00 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a0c +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a0c +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 00ffffff +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a10 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a10 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 4011ae30 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a14 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a14 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a18 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a18 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 03011300 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a1c +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a1c +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 78101a80 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a20 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a20 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 9795baea +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a24 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a24 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 278c5559 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a28 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a28 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 00545021 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a2c +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a2c +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 01010000 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a30 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a30 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 01010101 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a34 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a34 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 01010101 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a38 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a38 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 01010101 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a3c +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a3c +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 1b120101 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a40 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a40 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 20508000 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a44 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a44 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 20183014 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a48 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a48 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> a3050044 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a4c +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a4c +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 1f000010 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a50 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a50 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 80001693 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a54 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a54 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 30142050 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a58 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a58 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 00442018 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a5c +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a5c +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 0010a305 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a60 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a60 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 00001f00 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a64 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a64 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 81000f00 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a68 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a68 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 0a813c0a +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a6c +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a6c +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 00091632 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a70 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a70 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 01f0e430 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a74 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a74 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> fe000000 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a78 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a78 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 31504c00 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a7c +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008a7c +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 58573132 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008800 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008800 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> 4c542d33 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008800 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008800 +my_outl (0x1040, 0x000c510c); // Device I/O +my_inl (0x1044); // Device I/O --> ac003143 +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008000 +my_outl (0x1040, 0x000c5104); // Device I/O +my_inl (0x1044); // Device I/O --> 028000a1 +my_outl (0x1044, 0x480000a0); // Device I/O +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008000 +my_outl (0x1040, 0x000c5100); // Device I/O +my_inl (0x1044); // Device I/O --> 00000003 +my_outl (0x1044, 0x48000000); // Device I/O +my_outl (0x1040, 0x000c5108); // Device I/O +my_inl (0x1044); // Device I/O --> 00008000 +my_outl (0x1044, 0x00008000); // Device I/O +my_outb (0x03c4, 0x01); // Device I/O <-- +my_inw (0x03c4); // Device I/O --> 0x2001 +my_outw (0x03c4, 0x0001); // Device I/O +my_outb (0x03d4, 0x18); // Device I/O <-- +my_outb (0x03d6, 0xff); // Device I/O <-- +my_outb (0x03d0, 0xff); // Device I/O <-- +my_outb (0x03ce, 0x08); // Device I/O <-- +my_outb (0x03d2, 0xff); // Device I/O <-- +my_outb (0x03c4, 0x00); // Device I/O <-- +my_outb (0x03c8, 0x00); // Device I/O <-- +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000e1180); // Device I/O +my_inl (0x1044); // Device I/O --> 40000002 +my_outl (0x1044, 0x00000300); // Device I/O +my_outl (0x1040, 0x000c7208); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00fa09c4); // Device I/O +my_outl (0x1040, 0x000c720c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00fa09c4); // Device I/O +my_outl (0x1040, 0x000c7210); // Device I/O +my_inl (0x1044); // Device I/O --> 00186904 +my_outl (0x1044, 0x00186903); // Device I/O +my_outl (0x1040, 0x00048250); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x80000000); // Device I/O +my_outl (0x1040, 0x00048254); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x061a061a); // Device I/O +my_outl (0x1040, 0x000c8254); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x061a061a); // Device I/O +my_outl (0x1040, 0x000c8250); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x000c8250); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x80000000); // Device I/O +my_outl (0x1040, 0x000c7204); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000c4000); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f054); // Device I/O +my_inl (0x1044); // Device I/O --> 00000001 +my_outl (0x1044, 0x0000020d); // Device I/O +my_outl (0x1040, 0x0004f054); // Device I/O +my_inl (0x1044); // Device I/O --> 0000020d +my_outl (0x1040, 0x0004f050); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f050); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f054); // Device I/O +my_inl (0x1044); // Device I/O --> 0000020d +my_outl (0x1044, 0x0000020d); // Device I/O +my_outl (0x1040, 0x0004f050); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0xc0000000); // Device I/O +my_outl (0x1040, 0x0004f054); // Device I/O +my_inl (0x1044); // Device I/O --> 0000020d +my_outl (0x1040, 0x0004f054); // Device I/O +my_inl (0x1044); // Device I/O --> 0000020d +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000400); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000400 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000400 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03c6, 0xff); // Device I/O <-- +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1044, 0x03300000); // Device I/O +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03300000 +my_outl (0x1044, 0x30300000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 30300000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 30300000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 30300000 +my_outl (0x1040, 0x0004f048); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 30300000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 30300000 +my_outl (0x1044, 0x30030000); // Device I/O +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 30030000 +my_outl (0x1044, 0x03030000); // Device I/O + +vga_textmode_init (); + +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000001 +my_outl (0x1044, 0x01000008); // Device I/O +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1044, 0x03030000); // Device I/O +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1044, 0x03030000); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00070080); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000700c0); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outb (0x03c4, 0x01); // Device I/O <-- +my_inw (0x03c4); // Device I/O --> 0x0001 +my_outw (0x03c4, 0x2001); // Device I/O +my_outl (0x1040, 0x00041000); // Device I/O +my_inl (0x1044); // Device I/O --> 8000298e +my_outl (0x1040, 0x00041000); // Device I/O +my_inl (0x1044); // Device I/O --> 8000298e +my_outl (0x1044, 0x8000298e); // Device I/O +my_outl (0x1040, 0x00070180); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00071180); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00068070); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00068080); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00068074); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000400); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000400 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000400 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00041000); // Device I/O +my_inl (0x1044); // Device I/O --> 8000298e +my_outl (0x1044, 0x8020298e); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outw (0x03ce, 0x0010); // Device I/O +my_outw (0x03ce, 0x0011); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outw (0x03c4, 0x0100); // Device I/O +my_outw (0x03c4, 0x2001); // Device I/O +my_outw (0x03c4, 0x0302); // Device I/O +my_outw (0x03c4, 0x0003); // Device I/O +my_outw (0x03c4, 0x0204); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outw (0x03c4, 0x0300); // Device I/O +my_outb (0x03c2, 0x67); // Device I/O <-- +my_outb (0x03d4, 0x11); // Device I/O <-- +my_inw (0x03d4); // Device I/O --> 0x8e11 +my_outw (0x03d4, 0x0e11); // Device I/O +my_outw (0x03d4, 0x5f00); // Device I/O +my_outw (0x03d4, 0x4f01); // Device I/O +my_outw (0x03d4, 0x5002); // Device I/O +my_outw (0x03d4, 0x8203); // Device I/O +my_outw (0x03d4, 0x5504); // Device I/O +my_outw (0x03d4, 0x8105); // Device I/O +my_outw (0x03d4, 0xbf06); // Device I/O +my_outw (0x03d4, 0x1f07); // Device I/O +my_outw (0x03d4, 0x0008); // Device I/O +my_outw (0x03d4, 0x4f09); // Device I/O +my_outw (0x03d4, 0x0d0a); // Device I/O +my_outw (0x03d4, 0x0e0b); // Device I/O +my_outw (0x03d4, 0x000c); // Device I/O +my_outw (0x03d4, 0x000d); // Device I/O +my_outw (0x03d4, 0x000e); // Device I/O +my_outw (0x03d4, 0x000f); // Device I/O +my_outw (0x03d4, 0x9c10); // Device I/O +my_outw (0x03d4, 0x8e11); // Device I/O +my_outw (0x03d4, 0x8f12); // Device I/O +my_outw (0x03d4, 0x2813); // Device I/O +my_outw (0x03d4, 0x1f14); // Device I/O +my_outw (0x03d4, 0x9615); // Device I/O +my_outw (0x03d4, 0xb916); // Device I/O +my_outw (0x03d4, 0xa317); // Device I/O +my_outw (0x03d4, 0xff18); // Device I/O +my_inb (0x03da); // Device I/O --> 01 +my_inb (0x03ba); // Device I/O --> ff +my_inb (0x03da); // Device I/O --> 21 +my_inb (0x03ba); // Device I/O --> ff +my_inb (0x03da); // Device I/O --> 01 +my_inb (0x03ba); // Device I/O --> ff +my_outw (0x03ce, 0x0000); // Device I/O +my_outw (0x03ce, 0x0001); // Device I/O +my_outw (0x03ce, 0x0002); // Device I/O +my_outw (0x03ce, 0x0003); // Device I/O +my_outw (0x03ce, 0x0004); // Device I/O +my_outw (0x03ce, 0x1005); // Device I/O +my_outw (0x03ce, 0x0e06); // Device I/O +my_outw (0x03ce, 0x0007); // Device I/O +my_outw (0x03ce, 0xff08); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03c6, 0xff); // Device I/O <-- +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +vga_textmode_init (); +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03c4, 0x01); // Device I/O <-- +my_inw (0x03c4); // Device I/O --> 0x2001 +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f050); // Device I/O +my_inl (0x1044); // Device I/O --> c0000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03c4, 0x01); // Device I/O <-- +my_inw (0x03c4); // Device I/O --> 0x2001 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03ce, 0x06); // Device I/O <-- +my_inw (0x03ce); // Device I/O --> 0x0e06 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03c4, 0x01); // Device I/O <-- +my_inw (0x03c4); // Device I/O --> 0x2001 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00041000); // Device I/O +my_inl (0x1044); // Device I/O --> 8020298e +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000e1180); // Device I/O +my_inl (0x1044); // Device I/O --> 00000302 +my_outl (0x1044, 0x00008302); // Device I/O +my_outl (0x1040, 0x00048250); // Device I/O +my_inl (0x1044); // Device I/O --> 80000000 +my_outl (0x1044, 0x80000000); // Device I/O +my_outl (0x1040, 0x000e1180); // Device I/O +my_inl (0x1044); // Device I/O --> 00008302 +my_outl (0x1040, 0x000e1180); // Device I/O +my_inl (0x1044); // Device I/O --> 00008302 +my_outl (0x1040, 0x000e1180); // Device I/O +my_inl (0x1044); // Device I/O --> 00008302 +my_outl (0x1040, 0x000c6200); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00001000); // Device I/O +my_outl (0x1040, 0x000c6200); // Device I/O +my_inl (0x1044); // Device I/O --> 00001000 +my_outl (0x1044, 0x00001002); // Device I/O +my_outl (0x1040, 0x000c7204); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000c7204); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0xabcd0000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f00c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000c6040); // Device I/O +my_inl (0x1044); // Device I/O --> 00030d07 +my_outl (0x1044, 0x00021005); // Device I/O +my_outl (0x1040, 0x000c6014); // Device I/O +my_inl (0x1044); // Device I/O --> 04800080 +my_outl (0x1044, 0x88046004); // Device I/O +my_outl (0x1040, 0x000c6014); // Device I/O +my_inl (0x1044); // Device I/O --> 88046004 +my_outl (0x1044, 0x88046004); // Device I/O +my_outl (0x1040, 0x000c7204); // Device I/O +my_inl (0x1044); // Device I/O --> abcd0000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000e1180); // Device I/O +my_inl (0x1044); // Device I/O --> 00008302 +my_outl (0x1044, 0x00008302); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00060000); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x057f04ff); // Device I/O +my_outl (0x1040, 0x00060004); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x057f04ff); // Device I/O +my_outl (0x1040, 0x00060008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x05370517); // Device I/O +my_outl (0x1040, 0x0006000c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x0333031f); // Device I/O +my_outl (0x1040, 0x00060010); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x0333031f); // Device I/O +my_outl (0x1040, 0x00060014); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x03270323); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03c4, 0x01); // Device I/O <-- +my_inw (0x03c4); // Device I/O --> 0x2001 +my_outl (0x1040, 0x0006001c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x02cf018f); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00070008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f050); // Device I/O +my_inl (0x1044); // Device I/O --> c0000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03c4, 0x01); // Device I/O <-- +my_inw (0x03c4); // Device I/O --> 0x2001 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03ce, 0x06); // Device I/O <-- +my_inw (0x03ce); // Device I/O --> 0x0e06 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outb (0x03c4, 0x01); // Device I/O <-- +my_inw (0x03c4); // Device I/O --> 0x2001 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0006001c); // Device I/O +my_inl (0x1044); // Device I/O --> 02cf018f +my_outl (0x1044, 0x027f018f); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00068080); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x80800000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00068070); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00068074); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x05000320); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00070008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00070008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00060030); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x7e127ae1); // Device I/O +my_outl (0x1040, 0x00060034); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00800000); // Device I/O +my_outl (0x1040, 0x00060040); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00020da7); // Device I/O +my_outl (0x1040, 0x00060044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00080000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f000c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000040 +my_outl (0x1044, 0x00002040); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f000c); // Device I/O +my_inl (0x1044); // Device I/O --> 00002040 +my_outl (0x1044, 0x00002050); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00060100); // Device I/O +my_inl (0x1044); // Device I/O --> 00044000 +my_outl (0x1044, 0x00044000); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00070008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000040); // Device I/O +my_outl (0x1040, 0x000f0008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000040); // Device I/O +my_outl (0x1040, 0x000f000c); // Device I/O +my_inl (0x1044); // Device I/O --> 00002050 +my_outl (0x1044, 0x00022050); // Device I/O +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00070008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000040 +my_outl (0x1044, 0x00000050); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00070008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000050 +my_outl (0x1044, 0x80000050); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x00041000); // Device I/O +my_inl (0x1044); // Device I/O --> 8020298e +my_outl (0x1044, 0x0020298e); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000080); // Device I/O +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f0018); // Device I/O +my_inl (0x1044); // Device I/O --> 000007ff +my_outl (0x1044, 0x000000ff); // Device I/O +my_outl (0x1040, 0x000f1018); // Device I/O +my_inl (0x1044); // Device I/O --> 000007ff +my_outl (0x1044, 0x000000ff); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f000c); // Device I/O +my_inl (0x1044); // Device I/O --> 00022050 +my_outl (0x1044, 0x001a2050); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00060100); // Device I/O +my_inl (0x1044); // Device I/O --> 00044000 +my_outl (0x1044, 0x001c4000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00060100); // Device I/O +my_inl (0x1044); // Device I/O --> 001c4000 +my_outl (0x1044, 0x801c4000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f000c); // Device I/O +my_inl (0x1044); // Device I/O --> 001a2050 +my_outl (0x1044, 0x801a2050); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00060100); // Device I/O +my_inl (0x1044); // Device I/O --> 801c4000 +my_outl (0x1044, 0x801c4000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f000c); // Device I/O +my_inl (0x1044); // Device I/O --> 801a2050 +my_outl (0x1044, 0x801a2050); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f0014); // Device I/O +my_inl (0x1044); // Device I/O --> 00000100 +my_outl (0x1040, 0x000f0014); // Device I/O +my_inl (0x1044); // Device I/O --> 00000100 +my_outl (0x1044, 0x00000100); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00060100); // Device I/O +my_inl (0x1044); // Device I/O --> 801c4000 +my_outl (0x1044, 0x901c4000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f000c); // Device I/O +my_inl (0x1044); // Device I/O --> 801a2050 +my_outl (0x1044, 0x901a2050); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f0014); // Device I/O +my_inl (0x1044); // Device I/O --> 00000600 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000e0000); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x057f04ff); // Device I/O +my_outl (0x1040, 0x000e0004); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x057f04ff); // Device I/O +my_outl (0x1040, 0x000e0008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x05370517); // Device I/O +my_outl (0x1040, 0x000e000c); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x0333031f); // Device I/O +my_outl (0x1040, 0x000e0010); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x0333031f); // Device I/O +my_outl (0x1040, 0x000e0014); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x03270323); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00060100); // Device I/O +my_inl (0x1044); // Device I/O --> 901c4000 +my_outl (0x1044, 0xb01c4000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f000c); // Device I/O +my_inl (0x1044); // Device I/O --> 901a2050 +my_outl (0x1044, 0xb01a2050); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000f0008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000040 +my_outl (0x1044, 0x80000040); // Device I/O +my_outl (0x1040, 0x000e1180); // Device I/O +my_inl (0x1044); // Device I/O --> 00008302 +my_outl (0x1044, 0x80008302); // Device I/O +my_outl (0x1040, 0x000c7204); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0xabcd0000); // Device I/O +my_outl (0x1040, 0x000c7204); // Device I/O +my_inl (0x1044); // Device I/O --> abcd0000 +my_outl (0x1044, 0xabcd0002); // Device I/O +my_outl (0x1040, 0x000c7204); // Device I/O +my_inl (0x1044); // Device I/O --> abcd0002 +my_outl (0x1044, 0xabcd0003); // Device I/O +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d000000a +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> d0000009 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> c0000008 +my_outl (0x1040, 0x000c7200); // Device I/O +my_inl (0x1044); // Device I/O --> c0000008 +my_outl (0x1040, 0x000c7204); // Device I/O +my_inl (0x1044); // Device I/O --> abcd0003 +my_outl (0x1044, 0x00000003); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f040); // Device I/O +my_inl (0x1044); // Device I/O --> 01000008 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000400); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000400 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000400 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x0004f044); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x0004f04c); // Device I/O +my_inl (0x1044); // Device I/O --> 03030000 +my_outl (0x1040, 0x000c4030); // Device I/O +my_inl (0x1044); // Device I/O --> 00001000 +my_outl (0x1040, 0x000c4030); // Device I/O +my_inl (0x1044); // Device I/O --> 00001000 +my_outl (0x1044, 0x00001000); // Device I/O +my_outl (0x1040, 0x000c4008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x000c4008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x000c4008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1040, 0x00044008); // Device I/O +my_inl (0x1044); // Device I/O --> 00000000 +my_outl (0x1044, 0x00000000); // Device I/O diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c new file mode 100644 index 0000000..401d9ec --- /dev/null +++ b/src/northbridge/intel/nehalem/finalize.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <stdlib.h> +#include "nehalem.h" + +#define PCI_DEV_SNB PCI_DEV(0, 0, 0) + +void intel_sandybridge_finalize_smm(void) +{ + pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + + MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ + MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ + MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ + MCHBAR32_OR(0x6800, 1 << 31); + MCHBAR32_OR(0x7000, 1 << 31); + MCHBAR32_OR(0x77fc, 1 << 0); + + /* Memory Controller Lockdown */ + MCHBAR8(0x50fc) = 0x8f; + + /* Read+write the following */ + MCHBAR32(0x6030) = MCHBAR32(0x6030); + MCHBAR32(0x6034) = MCHBAR32(0x6034); + MCHBAR32(0x6008) = MCHBAR32(0x6008); +} diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c new file mode 100644 index 0000000..a4fa2cb --- /dev/null +++ b/src/northbridge/intel/nehalem/gma.c @@ -0,0 +1,785 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> + +#include "chip.h" +#include "nehalem.h" + +struct gt_powermeter { + u16 reg; + u32 value; +}; + +static const struct gt_powermeter snb_pm_gt1[] = { + {0xa200, 0xcc000000}, + {0xa204, 0x07000040}, + {0xa208, 0x0000fe00}, + {0xa20c, 0x00000000}, + {0xa210, 0x17000000}, + {0xa214, 0x00000021}, + {0xa218, 0x0817fe19}, + {0xa21c, 0x00000000}, + {0xa220, 0x00000000}, + {0xa224, 0xcc000000}, + {0xa228, 0x07000040}, + {0xa22c, 0x0000fe00}, + {0xa230, 0x00000000}, + {0xa234, 0x17000000}, + {0xa238, 0x00000021}, + {0xa23c, 0x0817fe19}, + {0xa240, 0x00000000}, + {0xa244, 0x00000000}, + {0xa248, 0x8000421e}, + {0} +}; + +static const struct gt_powermeter snb_pm_gt2[] = { + {0xa200, 0x330000a6}, + {0xa204, 0x402d0031}, + {0xa208, 0x00165f83}, + {0xa20c, 0xf1000000}, + {0xa210, 0x00000000}, + {0xa214, 0x00160016}, + {0xa218, 0x002a002b}, + {0xa21c, 0x00000000}, + {0xa220, 0x00000000}, + {0xa224, 0x330000a6}, + {0xa228, 0x402d0031}, + {0xa22c, 0x00165f83}, + {0xa230, 0xf1000000}, + {0xa234, 0x00000000}, + {0xa238, 0x00160016}, + {0xa23c, 0x002a002b}, + {0xa240, 0x00000000}, + {0xa244, 0x00000000}, + {0xa248, 0x8000421e}, + {0} +}; + +static const struct gt_powermeter ivb_pm_gt1[] = { + {0xa800, 0x00000000}, + {0xa804, 0x00021c00}, + {0xa808, 0x00000403}, + {0xa80c, 0x02001700}, + {0xa810, 0x05000200}, + {0xa814, 0x00000000}, + {0xa818, 0x00690500}, + {0xa81c, 0x0000007f}, + {0xa820, 0x01002501}, + {0xa824, 0x00000300}, + {0xa828, 0x01000331}, + {0xa82c, 0x0000000c}, + {0xa830, 0x00010016}, + {0xa834, 0x01100101}, + {0xa838, 0x00010103}, + {0xa83c, 0x00041300}, + {0xa840, 0x00000b30}, + {0xa844, 0x00000000}, + {0xa848, 0x7f000000}, + {0xa84c, 0x05000008}, + {0xa850, 0x00000001}, + {0xa854, 0x00000004}, + {0xa858, 0x00000007}, + {0xa85c, 0x00000000}, + {0xa860, 0x00010000}, + {0xa248, 0x0000221e}, + {0xa900, 0x00000000}, + {0xa904, 0x00001c00}, + {0xa908, 0x00000000}, + {0xa90c, 0x06000000}, + {0xa910, 0x09000200}, + {0xa914, 0x00000000}, + {0xa918, 0x00590000}, + {0xa91c, 0x00000000}, + {0xa920, 0x04002501}, + {0xa924, 0x00000100}, + {0xa928, 0x03000410}, + {0xa92c, 0x00000000}, + {0xa930, 0x00020000}, + {0xa934, 0x02070106}, + {0xa938, 0x00010100}, + {0xa93c, 0x00401c00}, + {0xa940, 0x00000000}, + {0xa944, 0x00000000}, + {0xa948, 0x10000e00}, + {0xa94c, 0x02000004}, + {0xa950, 0x00000001}, + {0xa954, 0x00000004}, + {0xa960, 0x00060000}, + {0xaa3c, 0x00001c00}, + {0xaa54, 0x00000004}, + {0xaa60, 0x00060000}, + {0} +}; + +static const struct gt_powermeter ivb_pm_gt2[] = { + {0xa800, 0x10000000}, + {0xa804, 0x00033800}, + {0xa808, 0x00000902}, + {0xa80c, 0x0c002f00}, + {0xa810, 0x12000400}, + {0xa814, 0x00000000}, + {0xa818, 0x00d20800}, + {0xa81c, 0x00000002}, + {0xa820, 0x03004b02}, + {0xa824, 0x00000600}, + {0xa828, 0x07000773}, + {0xa82c, 0x00000000}, + {0xa830, 0x00010032}, + {0xa834, 0x1520040d}, + {0xa838, 0x00020105}, + {0xa83c, 0x00083700}, + {0xa840, 0x0000151d}, + {0xa844, 0x00000000}, + {0xa848, 0x20001b00}, + {0xa84c, 0x0a000010}, + {0xa850, 0x00000000}, + {0xa854, 0x00000008}, + {0xa858, 0x00000008}, + {0xa85c, 0x00000000}, + {0xa860, 0x00020000}, + {0xa248, 0x0000221e}, + {0xa900, 0x00000000}, + {0xa904, 0x00003500}, + {0xa908, 0x00000000}, + {0xa90c, 0x0c000000}, + {0xa910, 0x12000500}, + {0xa914, 0x00000000}, + {0xa918, 0x00b20000}, + {0xa91c, 0x00000000}, + {0xa920, 0x08004b02}, + {0xa924, 0x00000200}, + {0xa928, 0x07000820}, + {0xa92c, 0x00000000}, + {0xa930, 0x00030000}, + {0xa934, 0x050f020d}, + {0xa938, 0x00020300}, + {0xa93c, 0x00903900}, + {0xa940, 0x00000000}, + {0xa944, 0x00000000}, + {0xa948, 0x20001b00}, + {0xa94c, 0x0a000010}, + {0xa950, 0x00000000}, + {0xa954, 0x00000008}, + {0xa960, 0x00110000}, + {0xaa3c, 0x00003900}, + {0xaa54, 0x00000008}, + {0xaa60, 0x00110000}, + {0} +}; + +static const struct gt_powermeter ivb_pm_gt2_17w[] = { + {0xa800, 0x20000000}, + {0xa804, 0x000e3800}, + {0xa808, 0x00000806}, + {0xa80c, 0x0c002f00}, + {0xa810, 0x0c000800}, + {0xa814, 0x00000000}, + {0xa818, 0x00d20d00}, + {0xa81c, 0x000000ff}, + {0xa820, 0x03004b02}, + {0xa824, 0x00000600}, + {0xa828, 0x07000773}, + {0xa82c, 0x00000000}, + {0xa830, 0x00020032}, + {0xa834, 0x1520040d}, + {0xa838, 0x00020105}, + {0xa83c, 0x00083700}, + {0xa840, 0x000016ff}, + {0xa844, 0x00000000}, + {0xa848, 0xff000000}, + {0xa84c, 0x0a000010}, + {0xa850, 0x00000002}, + {0xa854, 0x00000008}, + {0xa858, 0x0000000f}, + {0xa85c, 0x00000000}, + {0xa860, 0x00020000}, + {0xa248, 0x0000221e}, + {0xa900, 0x00000000}, + {0xa904, 0x00003800}, + {0xa908, 0x00000000}, + {0xa90c, 0x0c000000}, + {0xa910, 0x12000800}, + {0xa914, 0x00000000}, + {0xa918, 0x00b20000}, + {0xa91c, 0x00000000}, + {0xa920, 0x08004b02}, + {0xa924, 0x00000300}, + {0xa928, 0x01000820}, + {0xa92c, 0x00000000}, + {0xa930, 0x00030000}, + {0xa934, 0x15150406}, + {0xa938, 0x00020300}, + {0xa93c, 0x00903900}, + {0xa940, 0x00000000}, + {0xa944, 0x00000000}, + {0xa948, 0x20001b00}, + {0xa94c, 0x0a000010}, + {0xa950, 0x00000000}, + {0xa954, 0x00000008}, + {0xa960, 0x00110000}, + {0xaa3c, 0x00003900}, + {0xaa54, 0x00000008}, + {0xaa60, 0x00110000}, + {0} +}; + +static const struct gt_powermeter ivb_pm_gt2_35w[] = { + {0xa800, 0x00000000}, + {0xa804, 0x00030400}, + {0xa808, 0x00000806}, + {0xa80c, 0x0c002f00}, + {0xa810, 0x0c000300}, + {0xa814, 0x00000000}, + {0xa818, 0x00d20d00}, + {0xa81c, 0x000000ff}, + {0xa820, 0x03004b02}, + {0xa824, 0x00000600}, + {0xa828, 0x07000773}, + {0xa82c, 0x00000000}, + {0xa830, 0x00020032}, + {0xa834, 0x1520040d}, + {0xa838, 0x00020105}, + {0xa83c, 0x00083700}, + {0xa840, 0x000016ff}, + {0xa844, 0x00000000}, + {0xa848, 0xff000000}, + {0xa84c, 0x0a000010}, + {0xa850, 0x00000001}, + {0xa854, 0x00000008}, + {0xa858, 0x00000008}, + {0xa85c, 0x00000000}, + {0xa860, 0x00020000}, + {0xa248, 0x0000221e}, + {0xa900, 0x00000000}, + {0xa904, 0x00003800}, + {0xa908, 0x00000000}, + {0xa90c, 0x0c000000}, + {0xa910, 0x12000800}, + {0xa914, 0x00000000}, + {0xa918, 0x00b20000}, + {0xa91c, 0x00000000}, + {0xa920, 0x08004b02}, + {0xa924, 0x00000300}, + {0xa928, 0x01000820}, + {0xa92c, 0x00000000}, + {0xa930, 0x00030000}, + {0xa934, 0x15150406}, + {0xa938, 0x00020300}, + {0xa93c, 0x00903900}, + {0xa940, 0x00000000}, + {0xa944, 0x00000000}, + {0xa948, 0x20001b00}, + {0xa94c, 0x0a000010}, + {0xa950, 0x00000000}, + {0xa954, 0x00000008}, + {0xa960, 0x00110000}, + {0xaa3c, 0x00003900}, + {0xaa54, 0x00000008}, + {0xaa60, 0x00110000}, + {0} +}; + +/* some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselfes + */ + +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + /* none curently. */ + + return new_vendev; +} + +static struct resource *gtt_res = NULL; + +static inline u32 gtt_read(u32 reg) +{ + return read32(gtt_res->base + reg); +} + +static inline void gtt_write(u32 reg, u32 data) +{ + write32(gtt_res->base + reg, data); +} + +static inline void gtt_write_powermeter(const struct gt_powermeter *pm) +{ + for (; pm && pm->reg; pm++) + gtt_write(pm->reg, pm->value); +} + +#define GTT_RETRY 1000 +static int gtt_poll(u32 reg, u32 mask, u32 value) +{ + unsigned try = GTT_RETRY; + u32 data; + + while (try--) { + data = gtt_read(reg); + if ((data & mask) == value) + return 1; + udelay(10); + } + + printk(BIOS_ERR, "GT init timeout\n"); + return 0; +} + +static void gma_pm_init_pre_vbios(struct device *dev) +{ + u32 reg32; + + printk(BIOS_DEBUG, "GT Power Management Init\n"); + + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!gtt_res || !gtt_res->base) + return; + + if (bridge_silicon_revision() < IVB_STEP_C0) { + /* 1: Enable force wake */ + gtt_write(0xa18c, 0x00000001); + gtt_poll(0x130090, (1 << 0), (1 << 0)); + } else { + gtt_write(0xa180, 1 << 5); + gtt_write(0xa188, 0xffff0001); + gtt_poll(0x130040, (1 << 0), (1 << 0)); + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ + reg32 = gtt_read(0x42004); + reg32 |= (1 << 14) | (1 << 15); + gtt_write(0x42004, reg32); + } + + if (bridge_silicon_revision() >= IVB_STEP_A0) { + /* Display Reset Acknowledge Settings */ + reg32 = gtt_read(0x45010); + reg32 |= (1 << 1) | (1 << 0); + gtt_write(0x45010, reg32); + } + + /* 2: Get GT SKU from GTT+0x911c[13] */ + reg32 = gtt_read(0x911c); + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + if (reg32 & (1 << 13)) { + printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); + gtt_write_powermeter(snb_pm_gt1); + } else { + printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); + gtt_write_powermeter(snb_pm_gt2); + } + } else { + u32 unit = MCHBAR32(0x5938) & 0xf; + + if (reg32 & (1 << 13)) { + /* GT1 SKU */ + printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); + gtt_write_powermeter(ivb_pm_gt1); + } else { + /* GT2 SKU */ + u32 tdp = MCHBAR32(0x5930) & 0x7fff; + tdp /= (1 << unit); + + if (tdp <= 17) { + /* <=17W ULV */ + printk(BIOS_DEBUG, "IVB GT2 17W " + "Power Meter Weights\n"); + gtt_write_powermeter(ivb_pm_gt2_17w); + } else if ((tdp >= 25) && (tdp <= 35)) { + /* 25W-35W */ + printk(BIOS_DEBUG, "IVB GT2 25W-35W " + "Power Meter Weights\n"); + gtt_write_powermeter(ivb_pm_gt2_35w); + } else { + /* All others */ + printk(BIOS_DEBUG, "IVB GT2 35W " + "Power Meter Weights\n"); + gtt_write_powermeter(ivb_pm_gt2_35w); + } + } + } + + /* 3: Gear ratio map */ + gtt_write(0xa004, 0x00000010); + + /* 4: GFXPAUSE */ + gtt_write(0xa000, 0x00070020); + + /* 5: Dynamic EU trip control */ + gtt_write(0xa080, 0x00000004); + + /* 6: ECO bits */ + reg32 = gtt_read(0xa180); + reg32 |= (1 << 26) | (1 << 31); + /* (bit 20=1 for SNB step D1+ / IVB A0+) */ + if (bridge_silicon_revision() >= SNB_STEP_D1) + reg32 |= (1 << 20); + gtt_write(0xa180, reg32); + + /* 6a: for SnB step D2+ only */ + if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && + (bridge_silicon_revision() >= SNB_STEP_D2)) { + reg32 = gtt_read(0x9400); + reg32 |= (1 << 7); + gtt_write(0x9400, reg32); + + reg32 = gtt_read(0x941c); + reg32 &= 0xf; + reg32 |= (1 << 1); + gtt_write(0x941c, reg32); + gtt_poll(0x941c, (1 << 1), (0 << 1)); + } + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + reg32 = gtt_read(0x907c); + reg32 |= (1 << 16); + gtt_write(0x907c, reg32); + + /* 6b: Clocking reset controls */ + gtt_write(0x9424, 0x00000001); + } else { + /* 6b: Clocking reset controls */ + gtt_write(0x9424, 0x00000000); + } + + /* 7 */ + if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { + gtt_write(0x138128, 0x00000029); /* Mailbox Data */ + gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ + if (gtt_poll(0x138124, (1 << 31), (0 << 31))) + gtt_write(0x138124, 0x8000000a); + gtt_poll(0x138124, (1 << 31), (0 << 31)); + } + + /* 8 */ + gtt_write(0xa090, 0x00000000); /* RC Control */ + gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ + gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ + gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ + gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ + gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ + + /* 9 */ + gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ + gtt_write(0x12054, 0x0000000a); /* Video Idle Max Count */ + gtt_write(0x22054, 0x0000000a); /* Blitter Idle Max Count */ + + /* 10 */ + gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ + gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ + gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ + gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ + gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ + + /* 11 */ + gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ + gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ + gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ + gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ + gtt_write(0xa068, 0x000186a0); /* RP Up EI */ + gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ + gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ + + /* 11a: Enable Render Standby (RC6) */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* + * IvyBridge should also support DeepRenderStandby. + * + * Unfortunately it does not work reliably on all SKUs so + * disable it here and it can be enabled by the kernel. + */ + gtt_write(0xa090, 0x88040000); /* HW RC Control */ + } else { + gtt_write(0xa090, 0x88040000); /* HW RC Control */ + } + + /* 12: Normal Frequency Request */ + /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ + reg32 = MCHBAR32(0x5998); + reg32 >>= 16; + reg32 &= 0xef; + reg32 <<= 25; + gtt_write(0xa008, reg32); + + /* 13: RP Control */ + gtt_write(0xa024, 0x00000592); + + /* 14: Enable PM Interrupts */ + gtt_write(0x4402c, 0x03000076); + + /* Clear 0x6c024 [8:6] */ + reg32 = gtt_read(0x6c024); + reg32 &= ~0x000001c0; + gtt_write(0x6c024, reg32); +} + +#if 1 + +static u8 my_inb(u16 addr) +{ + u8 val; + + val = inb(addr); + + return val; +} + +static u16 my_inw(u16 addr) +{ + u16 val; + + val = inw(addr); + + return val; +} + +static u32 my_inl(u16 addr) +{ + u32 val; + + val = inl(addr); + + return val; +} + +static void my_outb(u16 addr, u8 val) +{ + outb(val, addr); +} + +static void my_outw(u16 addr, u16 val) +{ + outw(val, addr); +} + +static void my_outl(u16 addr, u32 val) +{ + outl(val, addr); +} +#endif + +#include <pc80/vga.h> +#include <pc80/vga_io.h> + +static void fake_vbios(void) +{ +#include "fake_vbios.c" +} + +static void gma_pm_init_post_vbios(struct device *dev) +{ + struct northbridge_intel_sandybridge_config *conf = dev->chip_info; + u32 reg32; + + printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); + + /* 15: Deassert Force Wake */ + if (bridge_silicon_revision() < IVB_STEP_C0) { + gtt_write(0xa18c, gtt_read(0xa18c) & ~1); + gtt_poll(0x130090, (1 << 0), (0 << 0)); + } else { + gtt_write(0xa188, 0x1fffe); + if (gtt_poll(0x130040, (1 << 0), (0 << 0))) + gtt_write(0xa188, gtt_read(0xa188) | 1); + } + + /* 16: SW RC Control */ + gtt_write(0xa094, 0x00060000); + + /* Setup Digital Port Hotplug */ + reg32 = gtt_read(0xc4030); + if (!reg32) { + reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; + reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; + reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; + gtt_write(0xc4030, reg32); + } + + /* Setup Panel Power On Delays */ + reg32 = gtt_read(0xc7208); + if (!reg32) { + reg32 = (conf->gpu_panel_port_select & 0x3) << 30; + reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + gtt_write(0xc7208, reg32); + } + + /* Setup Panel Power Off Delays */ + reg32 = gtt_read(0xc720c); + if (!reg32) { + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + gtt_write(0xc720c, reg32); + } + + /* Setup Panel Power Cycle Delay */ + if (conf->gpu_panel_power_cycle_delay) { + reg32 = gtt_read(0xc7210); + reg32 &= ~0xff; + reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + gtt_write(0xc7210, reg32); + } + + /* Enable Backlight if needed */ + if (conf->gpu_cpu_backlight) { + gtt_write(0x48250, (1 << 31)); + gtt_write(0x48254, conf->gpu_cpu_backlight); + } + if (conf->gpu_pch_backlight) { + gtt_write(0xc8250, (1 << 31)); + gtt_write(0xc8254, conf->gpu_pch_backlight); + } +} + +static void gma_func0_init(struct device *dev) +{ + u32 reg32; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Init graphics power management */ + gma_pm_init_pre_vbios(dev); + +#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); +#else + printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); +#endif + fake_vbios(); + + /* Linux relies on VBT for panel info. */ + if (read16(0xc0000) != 0xaa55) { + optionrom_header_t *oh = (void *)0xc0000; + optionrom_pcir_t *pcir; + int sz; + + memset(oh->reserved, 0, 8192); + + sz = (0x80 + sizeof(fake_vbt) + 511) / 512; + oh->signature = 0xaa55; + oh->size = sz; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)0xc0040; + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->imagelength = sz; + pcir->indicator = 0x80; + + memcpy((void *)0xc0080, fake_vbt, sizeof(fake_vbt)); + } + + + /* Post VBIOS init */ + gma_pm_init_post_vbios(dev); + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* This should probably run before post VBIOS init. */ + u32 iobase, mmiobase, physbase, graphics_base; + iobase = dev->resource_list[2].base; + mmiobase = dev->resource_list[0].base; + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + graphics_base = dev->resource_list[1].base; + + int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + i915lightup(physbase, iobase, mmiobase, graphics_base); +#endif +} + +static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & + 0xffff)); + } +} + +static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + +static struct pci_operations gma_pci_ops = { + .set_subsystem = gma_set_subsystem, +}; + +static struct device_operations gma_func0_ops = { + .read_resources = gma_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &gma_pci_ops, +}; + +static const unsigned short pci_device_ids[] = + { 0x0046, 0x0102, 0x0106, 0x010a, 0x0112, + 0x0116, 0x0122, 0x0126, 0x0156, + 0x0166, + 0 +}; + +static const struct pci_driver gma __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h new file mode 100644 index 0000000..bfa43ef --- /dev/null +++ b/src/northbridge/intel/nehalem/gma.h @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h new file mode 100644 index 0000000..6f05791 --- /dev/null +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -0,0 +1,628 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __NORTHBRIDGE_INTEL_CALPELLA_CALPELLA_H__ +#define __NORTHBRIDGE_INTEL_CALPELLA_CALPELLA_H__ 1 + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +extern unsigned char fake_vbt[4096]; + +typedef enum { + FSB_CLOCK_1067MHz = 0, + FSB_CLOCK_800MHz = 1, + FSB_CLOCK_667MHz = 2, +} fsb_clock_t; + +typedef enum { /* Steppings below B1 were pre-production, + conversion stepping A1 is... ? + We'll support B1, B2, B3, and conversion stepping A1. */ + STEPPING_A0 = 0, + STEPPING_A1 = 1, + STEPPING_A2 = 2, + STEPPING_A3 = 3, + STEPPING_B0 = 4, + STEPPING_B1 = 5, + STEPPING_B2 = 6, + STEPPING_B3 = 7, + STEPPING_CONVERSION_A1 = 9, +} stepping_t; + +typedef enum { + GMCH_GM45 = 0, + GMCH_GM47, + GMCH_GM49, + GMCH_GE45, + GMCH_GL40, + GMCH_GL43, + GMCH_GS40, + GMCH_GS45, + GMCH_PM45, + GMCH_UNKNOWN +} gmch_gfx_t; + +typedef enum { + MEM_CLOCK_533MHz = 0, + MEM_CLOCK_400MHz = 1, + MEM_CLOCK_333MHz = 2, + MEM_CLOCK_1067MT = 0, + MEM_CLOCK_800MT = 1, + MEM_CLOCK_667MT = 2, +} mem_clock_t; + +typedef enum { + DDR1 = 1, + DDR2 = 2, + DDR3 = 3, +} ddr_t; + +typedef enum { + CHANNEL_MODE_SINGLE, + CHANNEL_MODE_DUAL_ASYNC, + CHANNEL_MODE_DUAL_INTERLEAVED, +} channel_mode_t; + +typedef enum { /* as in DDR3 spd */ + CHIP_WIDTH_x4 = 0, + CHIP_WIDTH_x8 = 1, + CHIP_WIDTH_x16 = 2, + CHIP_WIDTH_x32 = 3, +} chip_width_t; + +typedef enum { /* as in DDR3 spd */ + CHIP_CAP_256M = 0, + CHIP_CAP_512M = 1, + CHIP_CAP_1G = 2, + CHIP_CAP_2G = 3, + CHIP_CAP_4G = 4, + CHIP_CAP_8G = 5, + CHIP_CAP_16G = 6, +} chip_capacity_t; + +typedef struct { + unsigned int CAS; + fsb_clock_t fsb_clock; + mem_clock_t mem_clock; + channel_mode_t channel_mode; + unsigned int tRAS; + unsigned int tRP; + unsigned int tRCD; + unsigned int tRFC; + unsigned int tWR; + unsigned int tRD; + unsigned int tRRD; + unsigned int tFAW; + unsigned int tWL; +} timings_t; + +typedef struct { + unsigned int card_type; /* 0x0: unpopulated, + 0xa - 0xf: raw card type A - F */ + chip_width_t chip_width; + chip_capacity_t chip_capacity; + unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ + unsigned int banks; + unsigned int ranks; + unsigned int rank_capacity_mb; /* per rank in Mega Bytes */ +} dimminfo_t; + +/* The setup is one DIMM per channel, so there's no need to find a + common timing setup between multiple chips (but chip and controller + still need to be coordinated */ +typedef struct { + stepping_t stepping; + int txt_enabled; + int cores; + gmch_gfx_t gfx_type; + int gs45_low_power_mode; /* low power mode of GMCH_GS45 */ + int max_ddr2_mhz; + int max_ddr3_mt; + fsb_clock_t max_fsb; + int max_fsb_mhz; + int max_render_mhz; + + int spd_type; + timings_t selected_timings; + dimminfo_t dimms[2]; +} sysinfo_t; + +#define TOTAL_CHANNELS 2 +#define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) +#define CHANNEL_IS_CARDF(dimms, idx) (dimms[idx].card_type == 0xf) +#define IF_CHANNEL_POPULATED(dimms, idx) if (dimms[idx].card_type != 0) +#define FOR_EACH_CHANNEL(idx) \ + for (idx = 0; idx < TOTAL_CHANNELS; ++idx) +#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ + FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) + +#define RANKS_PER_CHANNEL 4 /* Only two may be populated */ +#define IF_RANK_POPULATED(dimms, ch, r) \ + if (dimms[ch].card_type && ((r) < dimms[ch].ranks)) +#define FOR_EACH_RANK_IN_CHANNEL(r) \ + for (r = 0; r < RANKS_PER_CHANNEL; ++r) +#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ + FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) +#define FOR_EACH_RANK(ch, r) \ + FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) +#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ + FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) + +#define DDR3_MAX_CAS 18 + + +enum { + VCO_2666 = 4, + VCO_3200 = 0, + VCO_4000 = 1, + VCO_5333 = 2, +}; + +#endif + +/* Offsets of read/write training results in CMOS. + They will be restored upon S3 resumes. */ +#define CMOS_READ_TRAINING 0x80 /* 16 bytes */ +#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes + (could be reduced to 10 bytes) */ + + +#define DEFAULT_HECIBAR 0xfed17000 + + /* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +#define IOMMU_BASE1 0xfed90000 +#define IOMMU_BASE2 0xfed91000 +#define IOMMU_BASE3 0xfed92000 +#define IOMMU_BASE4 0xfed93000 + +/* + * D0:F0 + */ +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define DEVEN_PEG60 (1 << 13) +#define DEVEN_IGD (1 << 4) +#define DEVEN_PEG10 (1 << 3) +#define DEVEN_PEG11 (1 << 2) +#define DEVEN_PEG12 (1 << 1) +#define DEVEN_HOST (1 << 0) +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 +#define QPD0F1_PAM(x) (0x40+(x)) /* 0-6*/ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_IGD_BASE 0xa4 +#define D0F0_GTT_BASE 0xa8 +#define D0F0_TOLUD 0xb0 +#define D0F0_SKPD 0xdc /* Scratchpad Data */ + +#define SKPAD_ACPI_S3_MAGIC 0xcafed00d +#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe + + +#define D0F0_CAPID0 0xe0 + +#define TSEG 0xac /* TSEG base */ + +/* + * D1:F0 PEG + */ +#define PEG_CAP 0xa2 +#define SLOTCAP 0xb4 +#define PEGLC 0xec +#define D1F0_VCCAP 0x104 +#define D1F0_VC0RCTL 0x114 + +/* + * Graphics frequencies + */ +#define GCFGC_PCIDEV PCI_DEV(0, 2, 0) +#define GCFGC_OFFSET 0xf0 +#define GCFGC_CR_SHIFT 0 +#define GCFGC_CR_MASK (0xf << GCFGC_CR_SHIFT) +#define GCFGC_CS_SHIFT 8 +#define GCFGC_CS_MASK (0xf << GCFGC_CS_SHIFT) +#define GCFGC_CD_SHIFT 12 +#define GCFGC_CD_MASK (0x1 << GCFGC_CD_SHIFT) +#define GCFGC_UPDATE_SHIFT 5 +#define GCFGC_UPDATE (0x1 << GCFGC_UPDATE_SHIFT) + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ +#define PMSTS_WARM_RESET (1 << 1) +#define PMSTS_BOTH_SELFREFRESH (1 << 0) + +#define CLKCFG_MCHBAR 0x0c00 +#define CLKCFG_FSBCLK_SHIFT 0 +#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) +#define CLKCFG_MEMCLK_SHIFT 4 +#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) +#define CLKCFG_UPDATE (1 << 12) + +#define SSKPD_MCHBAR 0x0c1c +#define SSKPD_CLK_SHIFT 0 +#define SSKPD_CLK_MASK (7 << SSKPD_CLK_SHIFT) + +#define DCC_MCHBAR 0x200 +#define DCC_NO_CHANXOR (1 << 10) +#define DCC_INTERLEAVED (1 << 1) +#define DCC_CMD_SHIFT 16 +#define DCC_CMD_MASK (7 << DCC_CMD_SHIFT) +#define DCC_CMD_NOP (1 << DCC_CMD_SHIFT) + /* For mode register mr0: */ +#define DCC_SET_MREG (3 << DCC_CMD_SHIFT) + /* For extended mode registers mr1 to mr3: */ +#define DCC_SET_EREG (4 << DCC_CMD_SHIFT) +#define DCC_SET_EREG_SHIFT 21 +#define DCC_SET_EREG_MASK (DCC_CMD_MASK | (3 << DCC_SET_EREG_SHIFT)) +#define DCC_SET_EREGx(x) ((DCC_SET_EREG | \ + ((x - 1) << DCC_SET_EREG_SHIFT)) & \ + DCC_SET_EREG_MASK) + +/* Per channel DRAM Row Attribute registers (32-bit) */ +#define CxDRA_MCHBAR(x) (0x1208 + (x * 0x0100)) +#define CxDRA_PAGESIZE_SHIFT(r) (r * 4) /* Per rank r */ +#define CxDRA_PAGESIZE_MASKr(r) (0x7 << CxDRA_PAGESIZE_SHIFT(r)) +#define CxDRA_PAGESIZE_MASK 0x0000ffff +#define CxDRA_PAGESIZE(r, p) /* for log2(dimm page size in bytes) p */ \ + (((p - 10) << CxDRA_PAGESIZE_SHIFT(r)) & CxDRA_PAGESIZE_MASKr(r)) +#define CxDRA_BANKS_SHIFT(r) ((r * 3) + 16) +#define CxDRA_BANKS_MASKr(r) (0x3 << CxDRA_BANKS_SHIFT(r)) +#define CxDRA_BANKS_MASK 0x07ff0000 +#define CxDRA_BANKS(r, b) /* for number of banks b */ \ + ((b << (CxDRA_BANKS_SHIFT(r) - 3)) & CxDRA_BANKS_MASKr(r)) + +/* + * Per channel DRAM Row Boundary registers (32-bit) + * Every two ranks share one register and must be programmed at the same time. + * All registers (4 ranks per channel) have to be set. + */ +#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r/2) * 4)) +#define CxDRBy_BOUND_SHIFT(r) ((r % 2) * 16) +#define CxDRBy_BOUND_MASK(r) (0x1fc << CxDRBy_BOUND_SHIFT(r)) +#define CxDRBy_BOUND_MB(r, b) /* for boundary in MB b */ \ + (((b >> 5) << CxDRBy_BOUND_SHIFT(r)) & CxDRBy_BOUND_MASK(r)) + +#define CxDRC0_MCHBAR(x) (0x1230 + (x * 0x0100)) +#define CxDRC0_RANKEN0 (1 << 24) /* Rank Enable */ +#define CxDRC0_RANKEN1 (1 << 25) +#define CxDRC0_RANKEN2 (1 << 26) +#define CxDRC0_RANKEN3 (1 << 27) +#define CxDRC0_RANKEN(r) (1 << (24 + r)) +#define CxDRC0_RANKEN_MASK (0xf << 24) +#define CxDRC0_RMS_SHIFT 8 /* Refresh Mode Select */ +#define CxDRC0_RMS_MASK (7 << CxDRC0_RMS_SHIFT) +#define CxDRC0_RMS_78US (2 << CxDRC0_RMS_SHIFT) +#define CxDRC0_RMS_39US (3 << CxDRC0_RMS_SHIFT) + +#define CxDRC1_MCHBAR(x) (0x1234 + (x * 0x0100)) +#define CxDRC1_SSDS_SHIFT 24 +#define CxDRC1_SSDS_MASK (0xff << CxDRC1_SSDS_SHIFT) +#define CxDRC1_DS (0x91 << CxDRC1_SSDS_SHIFT) +#define CxDRC1_SS (0xb1 << CxDRC1_SSDS_SHIFT) +#define CxDRC1_NOTPOP(r) (1 << (16 + r)) /* Write 1 for Not Populated */ +#define CxDRC1_NOTPOP_MASK (0xf << 16) +#define CxDRC1_MUSTWR (3 << 11) + +#define CxDRC2_MCHBAR(x) (0x1238 + (x * 0x0100)) +#define CxDRC2_NOTPOP(r) (1 << (24 + r)) /* Write 1 for Not Populated */ +#define CxDRC2_NOTPOP_MASK (0xf << 24) +#define CxDRC2_MUSTWR (1 << 12) +#define CxDRC2_CLK1067MT (1 << 0) + +/* DRAM Timing registers (32-bit each) */ +#define CxDRT0_MCHBAR(x) (0x1210 + (x * 0x0100)) +#define CxDRT0_BtB_WtP_SHIFT 26 +#define CxDRT0_BtB_WtP_MASK (0x1f << CxDRT0_BtB_WtP_SHIFT) +#define CxDRT0_BtB_WtR_SHIFT 20 +#define CxDRT0_BtB_WtR_MASK (0x1f << CxDRT0_BtB_WtR_SHIFT) +#define CxDRT1_MCHBAR(x) (0x1214 + (x * 0x0100)) +#define CxDRT2_MCHBAR(x) (0x1218 + (x * 0x0100)) +#define CxDRT3_MCHBAR(x) (0x121c + (x * 0x0100)) +#define CxDRT4_MCHBAR(x) (0x1220 + (x * 0x0100)) +#define CxDRT5_MCHBAR(x) (0x1224 + (x * 0x0100)) +#define CxDRT6_MCHBAR(x) (0x1228 + (x * 0x0100)) + +/* Clock disable registers (32-bit each) */ +#define CxDCLKDIS_MCHBAR(x) (0x120c + (x * 0x0100)) +#define CxDCLKDIS_MASK 3 +#define CxDCLKDIS_ENABLE 3 /* Always enable both clock pairs. */ + +/* On-Die-Termination registers (2x 32-bit per channel) */ +#define CxODT_HIGH(x) (0x124c + (x * 0x0100)) +#define CxODT_LOW(x) (0x1248 + (x * 0x0100)) + +/* Write Training registers. */ +#define CxWRTy_MCHBAR(ch, s) (0x1470 + (ch * 0x0100) + ((3 - s) * 4)) + +#define CxGTEW(x) (0x1270+(x*0x100)) +#define CxGTC(x) (0x1274+(x*0x100)) +#define CxDTPEW(x) (0x1278+(x*0x100)) +#define CxDTAEW(x) (0x1280+(x*0x100)) +#define CxDTC(x) (0x1288+(x*0x100)) + + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +#define DMIVC0RCTL 0x14 +#define DMIESD 0x44 + + +/* + * EPBAR + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + + +#ifndef __ASSEMBLER__ +void gm45_early_init(void); +void gm45_early_reset(void); + +void enter_raminit_or_reset(void); +void get_gmch_info(sysinfo_t *); +void raminit_thermal(const sysinfo_t *); +void init_igd(const sysinfo_t *, int no_igd, int no_peg); +void init_pm(const sysinfo_t *); + +int raminit_read_vco_index(void); +u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank); + +void raminit_rcomp_calibration(stepping_t stepping); +void raminit_reset_readwrite_pointers(void); +void raminit_receive_enable_calibration(const timings_t *, const dimminfo_t *); +void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume); +void raminit_read_training(const dimminfo_t *, int s3resume); + +void gm45_late_init(stepping_t); + +u32 decode_igd_memory_size(u32 gms); +u32 decode_igd_gtt_size(u32 gsm); + +void init_iommu(void); +#endif + +/* Chipset types */ +#define NEHALEM_MOBILE 0 +#define NEHALEM_DESKTOP 1 +#define NEHALEM_SERVER 2 + +/* Device ID for SandyBridge and IvyBridge */ +#define BASE_REV_SNB 0x00 +#define BASE_REV_IVB 0x50 +#define BASE_REV_MASK 0x50 + +/* SandyBridge CPU stepping */ +#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ +#define SNB_STEP_D1 (BASE_REV_SNB + 6) +#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ + +/* IvyBridge CPU stepping */ +#define IVB_STEP_A0 (BASE_REV_IVB + 0) +#define IVB_STEP_B0 (BASE_REV_IVB + 2) +#define IVB_STEP_C0 (BASE_REV_IVB + 4) +#define IVB_STEP_K0 (BASE_REV_IVB + 5) +#define IVB_STEP_D0 (BASE_REV_IVB + 6) + +/* Intel Enhanced Debug region must be 4MB */ +#define IED_SIZE 0x400000 + +/* Northbridge BARs */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_RCBABASE 0xfed1c000 + +#define QUICKPATH_BUS 0xff + +#include <southbridge/intel/bd82x6x/pch.h> + +/* Everything below this line is ignored in the DSDT */ +#ifndef __ACPI__ + +/* Device 0:0.0 PCI configuration space (Host Bridge) */ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define X60BAR 0x60 + +#define LAC 0x87 /* Legacy Access Control */ +#define SMRAM 0x88 /* System Management RAM Control */ +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +#define SKPAD 0xdc /* Scratchpad Data */ + +/* Device 0:1.0 PCI configuration space (PCI Express) */ + +#define BCTRL1 0x3e /* 16bit */ + + +/* Device 0:2.0 PCI configuration space (Graphics Device) */ + +#define MSAC 0x62 /* Multi Size Aperture Control */ +#define SWSCI 0xe8 /* SWSCI enable */ +#define ASLS 0xfc /* OpRegion Base */ + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) + +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ + +/* + * EPBAR - Egress Port Root Complex Register Block + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCAP2 0x008 /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1IST 0x038 /* 64bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define PORTARB 0x100 /* 256bit */ + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ +#define DMIPVCCAP2 0x008 /* 32bit */ + +#define DMIPVCCCTL 0x00c /* 16bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL0 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMICTL1 0x0f0 /* 32bit */ +#define DMICTL2 0x0fc /* 32bit */ + +#define DMICC 0x208 /* 32bit */ + +#define DMIDRCCFG 0xeb4 /* 32bit */ + +#ifndef __ASSEMBLER__ +static inline void barrier(void) { asm("" ::: "memory"); } + +struct ied_header { + char signature[10]; + u32 size; + u8 reserved[34]; +} __attribute__ ((packed)); + +#define PCI_DEVICE_ID_SB 0x0104 +#define PCI_DEVICE_ID_IB 0x0154 + +#ifdef __SMM__ +void intel_sandybridge_finalize_smm(void); +#else /* !__SMM__ */ +int bridge_silicon_revision(void); +void nehalem_early_initialization(int chipset_type); +void nehalem_late_initialization(void); + +/* debugging functions */ +void print_pci_devices(void); +void dump_pci_device(unsigned dev); +void dump_pci_devices(void); +void dump_spd_registers(void); +void dump_mem(unsigned start, unsigned end); +void report_platform_info(void); +#endif /* !__SMM__ */ + + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +struct mrc_data_container *find_current_mrc_cache(void); +#if !defined(__PRE_RAM__) +#include "gma.h" +int init_igd_opregion(igd_opregion_t *igd_opregion); +#endif + +#endif +#endif +#endif diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c new file mode 100644 index 0000000..3000fe9 --- /dev/null +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -0,0 +1,446 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <stdint.h> +#include <delay.h> +#include <cpu/intel/model_2065x/model_2065x.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cbmem.h> +#include "chip.h" +#include "nehalem.h" + +static int bridge_revision_id = -1; + +int bridge_silicon_revision(void) +{ + if (bridge_revision_id < 0) { + uint8_t stepping = cpuid_eax(1) & 0xf; + uint8_t bridge_id = + pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), + PCI_DEVICE_ID) & 0xf0; + bridge_revision_id = bridge_id | stepping; + } + return bridge_revision_id; +} + +/* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) + * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI + */ +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 384; + +static int get_pcie_bar(u32 * base, u32 * len) +{ + device_t dev; + u32 pciexbar_reg; + + *base = 0; + *len = 0; + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!dev) + return 0; + + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + *base = + pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28)); + *len = 256 * 1024 * 1024; + return 1; + case 1: // 128M + *base = + pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27)); + *len = 128 * 1024 * 1024; + return 1; + case 2: // 64M + *base = + pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | + (1 << 28) | (1 << 27) | (1 << 26)); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +static void add_fixed_resources(struct device *dev, int index) +{ + struct resource *resource; + u32 pcie_config_base, pcie_config_size; + + if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { + printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " + "size=0x%x\n", pcie_config_base, pcie_config_size); + resource = new_resource(dev, index++); + resource->base = (resource_t) pcie_config_base; + resource->size = (resource_t) pcie_config_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + mmio_resource(dev, index++, legacy_hole_base_k, + (0xc0000 >> 10) - legacy_hole_base_k); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, + (0x100000 - 0xc0000) >> 10); + +#if CONFIG_CHROMEOS_RAMOOPS + reserved_ram_resource(dev, index++, + CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); +#endif + bad_ram_resource(dev, index++, 0x1fc000000ULL >> 10, 0x004000000 >> 10); +} + +static void pci_domain_set_resources(device_t dev) +{ + uint32_t tseg_base; + uint64_t TOUUD; + uint16_t reg16; + + tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); + TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), + D0F0_TOUUD); + + printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); + printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned)TOUUD); + + /* Report the memory regions */ + ram_resource(dev, 3, 0, 640); + ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768)); + + /* Using uma_resource() here would fail as base & size cannot + * be used as-is for a single MTRR. This would cause excessive + * use of MTRRs. + * + * Use of mmio_resource() instead does not create UC holes by using + * MTRRs, but making these regions uncacheable is taken care of by + * making sure they do not overlap with any ram_resource(). + * + * The resources can be changed to use separate mmio_resource() + * calls after MTRR code is able to merge them wisely. + */ + mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); + + reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC); + const int uma_sizes_gtt[16] = + { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; + /* Igd memory */ + const int uma_sizes_igd[16] = { + 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512 + }; + u32 igd_base, gtt_base; + int uma_size_igd, uma_size_gtt; + + uma_size_igd = uma_sizes_igd[(reg16 >> 4) & 0xF]; + uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; + + igd_base = + pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_IGD_BASE); + gtt_base = + pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GTT_BASE); + mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); + mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); + + if (TOUUD > 4096 + 256) + ram_resource(dev, 8, (4096 << 10), ((TOUUD - 4096) << 10)); + + add_fixed_resources(dev, 9); + + assign_resources(dev->link_list); + + /* Leave some space for ACPI, PIRQ and MP tables */ + set_top_of_ram(tseg_base / 1024); +} + + /* TODO We could determine how many PCIe busses we need in + * the bar. For now that number is hardcoded to a max of 64. + * See e7525/northbridge.c for an example. + */ +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static void mc_read_resources(device_t dev) +{ + struct resource *resource; + + pci_dev_read_resources(dev); + + /* So, this is one of the big mysteries in the coreboot resource + * allocator. This resource should make sure that the address space + * of the PCIe memory mapped config space bar. But it does not. + */ + + /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ + resource = new_resource(dev, 0xcf); + resource->base = DEFAULT_PCIEXBAR; + resource->size = 256 * 1024 * 1024; /* 64MB hard coded PCIe config space */ + resource->flags = + IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; + printk(BIOS_DEBUG, + "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", + (unsigned long)(resource->base), + (unsigned long)(resource->base + resource->size)); +} + +static void mc_set_resources(device_t dev) +{ + struct resource *resource; + + /* Report the PCIe BAR */ + resource = find_resource(dev, 0xcf); + if (resource) { + report_resource_stored(dev, resource, "<mmconfig>"); + } + + /* And call the normal set_resources */ + pci_dev_set_resources(dev); +} + +static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & + 0xffff)); + } +} + +static void northbridge_dmi_init(struct device *dev) +{ + u32 reg32; + + /* Clear error status bits */ + DMIBAR32(0x1c4) = 0xffffffff; + DMIBAR32(0x1d0) = 0xffffffff; + + /* Steps prior to DMI ASPM */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + reg32 = DMIBAR32(0x250); + reg32 &= ~((1 << 22) | (1 << 20)); + reg32 |= (1 << 21); + DMIBAR32(0x250) = reg32; + } + + reg32 = DMIBAR32(0x238); + reg32 |= (1 << 29); + DMIBAR32(0x238) = reg32; + + if (bridge_silicon_revision() >= SNB_STEP_D0) { + reg32 = DMIBAR32(0x1f8); + reg32 |= (1 << 16); + DMIBAR32(0x1f8) = reg32; + } else if (bridge_silicon_revision() >= SNB_STEP_D1) { + reg32 = DMIBAR32(0x1f8); + reg32 &= ~(1 << 26); + reg32 |= (1 << 16); + DMIBAR32(0x1f8) = reg32; + + reg32 = DMIBAR32(0x1fc); + reg32 |= (1 << 12) | (1 << 23); + DMIBAR32(0x1fc) = reg32; + } + + /* Enable ASPM on SNB link, should happen before PCH link */ + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { + reg32 = DMIBAR32(0xd04); + reg32 |= (1 << 4); + DMIBAR32(0xd04) = reg32; + } + + reg32 = DMIBAR32(0x88); + reg32 |= (1 << 1) | (1 << 0); + DMIBAR32(0x88) = reg32; +} + +static void northbridge_init(struct device *dev) +{ + u8 bios_reset_cpl; + u32 bridge_type; + + northbridge_dmi_init(dev); + + bridge_type = MCHBAR32(0x5f10); + bridge_type &= ~0xff; + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* Enable Power Aware Interrupt Routing */ + u8 pair = MCHBAR8(0x5418); + pair &= ~0xf; /* Clear 3:0 */ + pair |= 0x4; /* Fixed Priority */ + MCHBAR8(0x5418) = pair; + + /* 30h for IvyBridge */ + bridge_type |= 0x30; + } else { + /* 20h for Sandybridge */ + bridge_type |= 0x20; + } + MCHBAR32(0x5f10) = bridge_type; + + /* + * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management + */ + bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); + bios_reset_cpl |= 1; + MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; + printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); +#ifdef DISABLED + set_power_limits(28); + + /* + * CPUs with configurable TDP also need power limits set + * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. + */ + if (cpu_config_tdp_levels()) { + msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); + MCHBAR32(0x59A0) = msr.lo; + MCHBAR32(0x59A4) = msr.hi; + } +#endif + /* Set here before graphics PM init */ + MCHBAR32(0x5500) = 0x00100001; +} + +static void northbridge_enable(device_t dev) +{ +#if CONFIG_HAVE_ACPI_RESUME + switch (pci_read_config32(dev, SKPAD)) { + case 0xcafebabe: + printk(BIOS_DEBUG, "Normal boot.\n"); + acpi_slp_type = 0; + break; + case 0xcafed00d: + printk(BIOS_DEBUG, "S3 Resume.\n"); + acpi_slp_type = 3; + break; + default: + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + acpi_slp_type = 0; + break; + } +#endif +} + +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + +static struct device_operations mc_ops = { + .read_resources = mc_read_resources, + .set_resources = mc_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = northbridge_enable, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, +}; + +static const struct pci_driver mc_driver_44 __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0044, /* Sandy bridge */ +}; + +static const struct pci_driver mc_driver_0100 __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0100, +}; + +static const struct pci_driver mc_driver __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0104, /* Sandy bridge */ +}; + +static const struct pci_driver mc_driver_1 __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0154, /* Ivy bridge */ +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); + /* Enable ROM caching if option was selected. */ + x86_mtrr_enable_rom_caching(); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_sandybridge_ops = { + CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c new file mode 100644 index 0000000..c98382b --- /dev/null +++ b/src/northbridge/intel/nehalem/raminit.c @@ -0,0 +1,5276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef REAL +#define REAL 1 +#endif + +#if REAL +#include <console/console.h> +#include <string.h> +#include <arch/hlt.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cbmem.h> +#include <arch/cbfs.h> +#include <cbfs.h> +#include <ip_checksum.h> +#include <pc80/mc146818rtc.h> +#include <device/pci_def.h> +#include <arch/cpu.h> +#include <spd.h> +#include "raminit.h" +#include <timestamp.h> +#include <cpu/x86/mtrr.h> +#include <cpu/intel/speedstep.h> +#include <cpu/intel/turbo.h> +#endif + +#if !REAL +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef u32 device_t; +#endif + +#include "nehalem.h" + +#include "southbridge/intel/bd82x6x/me.h" + +#if REAL +#include <delay.h> +#endif + +#define NORTHBRIDGE 0, 0, 0 +#define SOUTHBRIDGE 0, 0x1f, 0 +#define HECIDEV 0, 0x16, 0 +#define HECIBAR 0x10 + +#define FOR_ALL_RANKS \ + for (channel = 0; channel < NUM_CHANNELS; channel++) \ + for (slot = 0; slot < NUM_SLOTS; slot++) \ + for (rank = 0; rank < NUM_RANKS; rank++) + +#define FOR_POPULATED_RANKS \ + for (channel = 0; channel < NUM_CHANNELS; channel++) \ + for (slot = 0; slot < NUM_SLOTS; slot++) \ + for (rank = 0; rank < NUM_RANKS; rank++) \ + if (info->populated_ranks[channel][slot][rank]) + +#define FOR_POPULATED_RANKS_BACKWARDS \ + for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) \ + for (slot = 0; slot < NUM_SLOTS; slot++) \ + for (rank = 0; rank < NUM_RANKS; rank++) \ + if (info->populated_ranks[channel][slot][rank]) + +/* [REG_178][CHANNEL][2 * SLOT + RANK][LANE] */ +typedef struct { + u8 smallest; + u8 largest; +} timing_bounds_t[2][2][2][9]; + +struct ram_training { + /* [TM][CHANNEL][SLOT][RANK][LANE] */ + u16 lane_timings[4][2][2][2][9]; + u16 reg_178; + u16 reg_10b; + + u8 reg178_center; + u8 reg178_smallest; + u8 reg178_largest; + timing_bounds_t timing_bounds[2]; + u16 timing_offset[2][2][2][9]; + u16 timing2_offset[2][2][2][9]; + u16 timing2_bounds[2][2][2][9][2]; +}; + +#if !REAL +#include "raminit_fake.c" +#else + +#include <lib.h> /* Prototypes */ + +static void my_write_msr(u32 addr, u64 val) +{ + msr_t msr = {.lo = val,.hi = val >> 32 }; + + wrmsr(addr, msr); +} + +static inline void write_mchbar32(u32 addr, u32 val) +{ + MCHBAR32(addr) = val; +} + +static inline void write_mchbar16(u32 addr, u16 val) +{ + MCHBAR16(addr) = val; +} + +static inline void write_mchbar8(u32 addr, u8 val) +{ + MCHBAR8(addr) = val; +} + + +static inline u32 read_mchbar32(u32 addr) +{ + return MCHBAR32(addr); +} + +static inline u16 read_mchbar16(u32 addr) +{ + return MCHBAR16(addr); +} + +static inline u8 read_mchbar8(u32 addr) +{ + return MCHBAR8(addr); +} + +static inline u8 read_mchbar8_bypass(u32 addr) +{ + return MCHBAR8(addr); +} + +static void pci_write8(int bus, int dev, int func, u32 addr, u8 val) +{ + pci_write_config8(PCI_DEV(bus, dev, func), addr, val); +} + +static void pci_mm_write8(int bus, int dev, int func, u32 addr, u8 val) +{ + pcie_write_config8(PCI_DEV(bus, dev, func), addr, val); +} + +static void pci_mm_write16(int bus, int dev, int func, u32 addr, u16 val) +{ + pcie_write_config16(PCI_DEV(bus, dev, func), addr, val); +} + +static void pci_mm_write32(int bus, int dev, int func, u32 addr, u32 val) +{ + pcie_write_config32(PCI_DEV(bus, dev, func), addr, val); +} + +static u32 pci_mm_read32(int bus, int dev, int func, u32 addr) +{ + return pcie_read_config32(PCI_DEV(bus, dev, func), addr); +} + +static u16 pci_mm_read16(int bus, int dev, int func, u32 addr) +{ + return pcie_read_config16(PCI_DEV(bus, dev, func), addr); +} + +static u8 pci_mm_read8(int bus, int dev, int func, u32 addr) +{ + return pcie_read_config8(PCI_DEV(bus, dev, func), addr); +} + +static void clflush(u32 addr) +{ + asm volatile ("clflush (%0)"::"r" (addr)); +} + +typedef struct _u128 { + u64 lo; + u64 hi; +} u128; + +static void read128(u32 addr, u64 * out) +{ + u128 ret; + u128 stor; + asm volatile ("movdqu %%xmm0, %0\n" + "movdqa (%2), %%xmm0\n" + "movdqu %%xmm0, %1\n" + "movdqu %0, %%xmm0":"+m" (stor), "=m"(ret):"r"(addr)); + out[0] = ret.lo; + out[1] = ret.hi; +} + +static u64 my_read_msr(u32 addr) +{ + msr_t m = rdmsr(addr); + return (((u64) m.hi) << 32) | m.lo; +} + +#endif + +/* OK */ +static void write_1d0(u32 val, u16 addr, int bits, int flag) +{ + write_mchbar32(0x1d0, 0); + while (read_mchbar32(0x1d0) & 0x800000) ; + write_mchbar32(0x1d4, + (val & ((1 << bits) - 1)) | (2 << bits) | (flag << + bits)); + write_mchbar32(0x1d0, 0x40000000 | addr); + while (read_mchbar32(0x1d0) & 0x800000) ; +} + +/* OK */ +static u16 read_1d0(u16 addr, int split) +{ + u32 val; + write_mchbar32(0x1d0, 0); + while (read_mchbar32(0x1d0) & 0x800000) ; + write_mchbar32(0x1d0, + 0x80000000 | (((read_mchbar8(0x246) >> 2) & 3) + + 0x361 - addr)); + while (read_mchbar32(0x1d0) & 0x800000) ; + val = read_mchbar32(0x1d8); + write_1d0(0, 0x33d, 0, 0); + write_1d0(0, 0x33d, 0, 0); + val &= ((1 << split) - 1); + // printk (BIOS_ERR, "R1D0C [%x] => %x\n", addr, val); + return val; +} + +static void sfence(void) +{ +#if REAL + asm volatile ("sfence"); +#endif +} + +static inline u16 get_lane_offset(int slot, int rank, int lane) +{ + return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - + 0x452 * (lane == 8); +} + +static inline u16 get_timing_register_addr(int lane, int tm, int slot, int rank) +{ + const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c }; + return get_lane_offset(slot, rank, lane) + offs[(tm + 3) % 4]; +} + +#if REAL +static u32 gav_real(int line, u32 in) +{ + // printk (BIOS_DEBUG, "%d: GAV: %x\n", line, in); + return in; +} + +#define gav(x) gav_real (__LINE__, (x)) +#endif +struct raminfo { + u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */ + u16 fsb_frequency; /* in 1.(1)/2 MHz. */ + u8 is_x16_module[2][2]; /* [CHANNEL][SLOT] */ + u8 density[2][2]; /* [CHANNEL][SLOT] */ + u8 populated_ranks[2][2][2]; /* [CHANNEL][SLOT][RANK] */ + int rank_start[2][2][2]; + u8 cas_latency; + u8 board_lane_delay[9]; + u8 use_ecc; + u8 revision; + u8 max_supported_clock_speed_index; + u8 uma_enabled; + u8 spd[2][2][151]; /* [CHANNEL][SLOT][BYTE] */ + u8 silicon_revision; + u8 populated_ranks_mask[2]; + u8 max_slots_used_in_channel; + u8 mode4030[2]; + u16 avg4044[2]; + u16 max4048[2]; + unsigned total_memory_mb; + unsigned interleaved_part_mb; + unsigned non_interleaved_part_mb; + + u32 heci_bar; + u64 heci_uma_addr; + unsigned memory_reserved_for_heci_mb; + + struct ram_training training; + u32 last_500_command[2]; + + u8 reg2ca9_bit0; + u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ + u32 delay46_ps[2]; + u32 delay54_ps[2]; + u8 revision_flag_1; + u8 some_delay_1_cycle_floor; + u8 some_delay_2_halfcycles_ceil; + u8 some_delay_3_ps_rounded; + + const struct ram_training *cached_training; +}; + +static void +write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, + int flag); + +/* OK */ +static u16 +read_500(struct raminfo *info, int channel, u16 addr, int split) +{ + u32 val; + info->last_500_command[channel] = 0x80000000; + write_mchbar32(0x500 + (channel << 10), 0); + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + write_mchbar32(0x500 + (channel << 10), + 0x80000000 | + (((read_mchbar8(0x246 + (channel << 10)) >> 2) & + 3) + 0xb88 - addr)); + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + val = read_mchbar32(0x508 + (channel << 10)); + return val & ((1 << split) - 1); +} + +/* OK */ +static void +write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, + int flag) +{ + if (info->last_500_command[channel] == 0x80000000) { + info->last_500_command[channel] = 0x40000000; + write_500(info, channel, 0, 0xb61, 0, 0); + } + write_mchbar32(0x500 + (channel << 10), 0); + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; + write_mchbar32(0x504 + (channel << 10), + (val & ((1 << bits) - 1)) | (2 << bits) | (flag << + bits)); + write_mchbar32(0x500 + (channel << 10), 0x40000000 | addr); + while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; +} + +static int rw_test(int rank) +{ + const u32 mask = 0xf00fc33c; + int ok = 0xff; + int i; + for (i = 0; i < 64; i++) + write32((rank << 28) | (i << 2), 0); + sfence(); + for (i = 0; i < 64; i++) + gav(read32((rank << 28) | (i << 2))); + sfence(); + for (i = 0; i < 32; i++) { + u32 pat = (((mask >> i) & 1) ? 0xffffffff : 0); + write32((rank << 28) | (i << 3), pat); + write32((rank << 28) | (i << 3) | 4, pat); + } + sfence(); + for (i = 0; i < 32; i++) { + u8 pat = (((mask >> i) & 1) ? 0xff : 0); + int j; + u32 val; + gav(val = read32((rank << 28) | (i << 3))); + for (j = 0; j < 4; j++) + if (((val >> (j * 8)) & 0xff) != pat) + ok &= ~(1 << j); + gav(val = read32((rank << 28) | (i << 3) | 4)); + for (j = 0; j < 4; j++) + if (((val >> (j * 8)) & 0xff) != pat) + ok &= ~(16 << j); + } + sfence(); + for (i = 0; i < 64; i++) + write32((rank << 28) | (i << 2), 0); + sfence(); + for (i = 0; i < 64; i++) + gav(read32((rank << 28) | (i << 2))); + + return ok; +} + +static void +program_timings(struct raminfo *info, u16 base, int channel, int slot, int rank) +{ + int lane; + for (lane = 0; lane < 8; lane++) { + write_500(info, channel, + base + + info->training. + lane_timings[2][channel][slot][rank][lane], + get_timing_register_addr(lane, 2, slot, rank), 9, 0); + write_500(info, channel, + base + + info->training. + lane_timings[3][channel][slot][rank][lane], + get_timing_register_addr(lane, 3, slot, rank), 9, 0); + } +} + +static void write_26c(int channel, u16 si) +{ + write_mchbar32(0x26c + (channel << 10), 0x03243f35); + write_mchbar32(0x268 + (channel << 10), 0xcfc00000 | (si << 9)); + write_mchbar16(0x2b9 + (channel << 10), si); +} + +static u32 get_580(int channel, u8 addr) +{ + u32 ret; + gav(read_1d0(0x142, 3)); + write_mchbar8(0x5ff, 0x0); /* OK */ + write_mchbar8(0x5ff, 0x80); /* OK */ + write_mchbar32(0x580 + (channel << 10), 0x8493c012 | addr); + write_mchbar8(0x580 + (channel << 10), + read_mchbar8(0x580 + (channel << 10)) | 1); + while (!((ret = read_mchbar32(0x580 + (channel << 10))) & 0x10000)) ; + write_mchbar8(0x580 + (channel << 10), + read_mchbar8(0x580 + (channel << 10)) & ~1); + return ret; +} + +const int cached_config = 0; + +#define NUM_CHANNELS 2 +#define NUM_SLOTS 2 +#define NUM_RANKS 2 +#define RANK_SHIFT 28 +#define CHANNEL_SHIFT 10 + +#include "raminit_tables.c" + +static void seq9(struct raminfo *info, int channel, int slot, int rank) +{ + int i, lane; + + for (i = 0; i < 2; i++) + for (lane = 0; lane < 8; lane++) + write_500(info, channel, + info->training.lane_timings[i + + 1][channel][slot] + [rank][lane], get_timing_register_addr(lane, + i + 1, + slot, + rank), + 9, 0); + + write_1d0(1, 0x103, 6, 1); + for (lane = 0; lane < 8; lane++) + write_500(info, channel, + info->training. + lane_timings[0][channel][slot][rank][lane], + get_timing_register_addr(lane, 0, slot, rank), 9, 0); + + for (i = 0; i < 2; i++) { + for (lane = 0; lane < 8; lane++) + write_500(info, channel, + info->training.lane_timings[i + + 1][channel][slot] + [rank][lane], get_timing_register_addr(lane, + i + 1, + slot, + rank), + 9, 0); + gav(get_580(channel, ((i + 1) << 2) | (rank << 5))); + } + + gav(read_1d0(0x142, 3)); // = 0x10408118 + write_mchbar8(0x5ff, 0x0); /* OK */ + write_mchbar8(0x5ff, 0x80); /* OK */ + write_1d0(0x2, 0x142, 3, 1); + for (lane = 0; lane < 8; lane++) { + // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); + info->training.lane_timings[2][channel][slot][rank][lane] = + read_500(info, channel, + get_timing_register_addr(lane, 2, slot, rank), 9); + //printk (BIOS_ERR, "after: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); + info->training.lane_timings[3][channel][slot][rank][lane] = + info->training.lane_timings[2][channel][slot][rank][lane] + + 0x20; + } +} + +static int count_ranks_in_channel(struct raminfo *info, int channel) +{ + int slot, rank; + int res = 0; + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_SLOTS; rank++) + res += info->populated_ranks[channel][slot][rank]; + return res; +} + +static void +config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank) +{ + int add; + + write_1d0(0, 0x178, 7, 1); + seq9(info, channel, slot, rank); + program_timings(info, 0x80, channel, slot, rank); + + if (channel == 0) + add = count_ranks_in_channel(info, 1); + else + add = 0; + if (!s3resume) + gav(rw_test(rank + add)); + program_timings(info, 0x00, channel, slot, rank); + if (!s3resume) + gav(rw_test(rank + add)); + if (!s3resume) + gav(rw_test(rank + add)); + write_1d0(0, 0x142, 3, 1); + write_1d0(0, 0x103, 6, 1); + + gav(get_580(channel, 0xc | (rank << 5))); + gav(read_1d0(0x142, 3)); + + write_mchbar8(0x5ff, 0x0); /* OK */ + write_mchbar8(0x5ff, 0x80); /* OK */ +} + +static void set_4cf(struct raminfo *info, int channel, u8 val) +{ + gav(read_500(info, channel, 0x4cf, 4)); // = 0xc2300cf9 + write_500(info, channel, val, 0x4cf, 4, 1); + gav(read_500(info, channel, 0x659, 4)); // = 0x80300839 + write_500(info, channel, val, 0x659, 4, 1); + gav(read_500(info, channel, 0x697, 4)); // = 0x80300839 + write_500(info, channel, val, 0x697, 4, 1); +} + +static void set_334(int zero) +{ + int j, k, channel; + const u32 val3[] = { 0x2a2b2a2b, 0x26272627, 0x2e2f2e2f, 0x2a2b }; + u32 vd8[2][16]; + + for (channel = 0; channel < NUM_CHANNELS; channel++) { + for (j = 0; j < 4; j++) { + u32 a = (j == 1) ? 0x29292929 : 0x31313131; + u32 lmask = (j == 3) ? 0xffff : 0xffffffff; + u16 c; + if ((j == 0 || j == 3) && zero) + c = 0; + else if (j == 3) + c = 0x5f; + else + c = 0x5f5f; + + for (k = 0; k < 2; k++) { + write_mchbar32(0x138 + 8 * k, + (channel << 26) | (j << 24)); + gav(vd8[1][(channel << 3) | (j << 1) | k] = + read_mchbar32(0x138 + 8 * k)); + gav(vd8[0][(channel << 3) | (j << 1) | k] = + read_mchbar32(0x13c + 8 * k)); + } + + write_mchbar32(0x334 + (channel << 10) + (j * 0x44), + zero ? 0 : val3[j]); + write_mchbar32(0x32c + (channel << 10) + (j * 0x44), + zero ? 0 : (0x18191819 & lmask)); + write_mchbar16(0x34a + (channel << 10) + (j * 0x44), c); + write_mchbar32(0x33c + (channel << 10) + (j * 0x44), + zero ? 0 : (a & lmask)); + write_mchbar32(0x344 + (channel << 10) + (j * 0x44), + zero ? 0 : (a & lmask)); + } + } + + write_mchbar32(0x130, read_mchbar32(0x130) | 1); /* OK */ + while (read_mchbar8(0x130) & 1) ; /* OK */ +} + +static void rmw_1d0(u16 addr, u32 and, u32 or, int split, int flag) +{ + u32 v; + v = read_1d0(addr, split); + write_1d0((v & and) | or, addr, split, flag); +} + +static int find_highest_bit_set(u16 val) +{ + int i; + for (i = 15; i >= 0; i--) + if (val & (1 << i)) + return i; + return -1; +} + +static int find_lowest_bit_set32(u32 val) +{ + int i; + for (i = 0; i < 32; i++) + if (val & (1 << i)) + return i; + return -1; +} + +#define max(a,b) (((a) > (b)) ? (a) : (b)) +#define min(a,b) (((a) < (b)) ? (a) : (b)) + +enum { + DEVICE_TYPE = 2, + MODULE_TYPE = 3, + DENSITY = 4, + RANKS_AND_DQ = 7, + MEMORY_BUS_WIDTH = 8, + TIMEBASE_DIVIDEND = 10, + TIMEBASE_DIVISOR = 11, + CYCLETIME = 12, + + CAS_LATENCIES_LSB = 14, + CAS_LATENCIES_MSB = 15, + CAS_LATENCY_TIME = 16, + THERMAL_AND_REFRESH = 31, + REFERENCE_RAW_CARD_USED = 62, + RANK1_ADDRESS_MAPPING = 63 +}; + +static void calculate_timings(struct raminfo *info) +{ + unsigned cycletime; + unsigned cas_latency_time; + unsigned supported_cas_latencies; + unsigned channel, slot; + unsigned clock_speed_index; + unsigned min_cas_latency; + unsigned cas_latency; + unsigned max_clock_index; + + /* Find common CAS latency */ + supported_cas_latencies = 0x3fe; + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + if (info->populated_ranks[channel][slot][0]) + supported_cas_latencies &= + 2 * + (info-> + spd[channel][slot][CAS_LATENCIES_LSB] | + (info-> + spd[channel][slot][CAS_LATENCIES_MSB] << + 8)); + + max_clock_index = min(3, info->max_supported_clock_speed_index); + + cycletime = min_cycletime[max_clock_index]; + cas_latency_time = min_cas_latency_time[max_clock_index]; + + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + if (info->populated_ranks[channel][slot][0]) { + unsigned timebase; + timebase = + 1000 * + info-> + spd[channel][slot][TIMEBASE_DIVIDEND] / + info->spd[channel][slot][TIMEBASE_DIVISOR]; + cycletime = + max(cycletime, + timebase * + info->spd[channel][slot][CYCLETIME]); + cas_latency_time = + max(cas_latency_time, + timebase * + info-> + spd[channel][slot][CAS_LATENCY_TIME]); + } + for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) { + if (cycletime == min_cycletime[clock_speed_index]) + break; + if (cycletime > min_cycletime[clock_speed_index]) { + clock_speed_index--; + cycletime = min_cycletime[clock_speed_index]; + break; + } + } + min_cas_latency = (cas_latency_time + cycletime - 1) / cycletime; + cas_latency = 0; + while (supported_cas_latencies) { + cas_latency = find_highest_bit_set(supported_cas_latencies) + 3; + if (cas_latency <= min_cas_latency) + break; + supported_cas_latencies &= + ~(1 << find_highest_bit_set(supported_cas_latencies)); + } + + if (cas_latency != min_cas_latency && clock_speed_index) + clock_speed_index--; + + if (cas_latency * min_cycletime[clock_speed_index] > 20000) + die("Couldn't configure DRAM"); + info->clock_speed_index = clock_speed_index; + info->cas_latency = cas_latency; +} + +static void program_base_timings(struct raminfo *info) +{ + unsigned channel; + unsigned slot, rank, lane; + unsigned extended_silicon_revision; + int i; + + extended_silicon_revision = info->silicon_revision; + if (info->silicon_revision == 0) + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + if ((info-> + spd[channel][slot][MODULE_TYPE] & 0xF) == + 3) + extended_silicon_revision = 4; + + for (channel = 0; channel < NUM_CHANNELS; channel++) { + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_SLOTS; rank++) { + int card_timing_2; + if (!info->populated_ranks[channel][slot][rank]) + continue; + + for (lane = 0; lane < 9; lane++) { + int tm_reg; + int card_timing; + + card_timing = 0; + if ((info-> + spd[channel][slot][MODULE_TYPE] & + 0xF) == 3) { + int reference_card; + reference_card = + info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & + 0x1f; + if (reference_card == 3) + card_timing = + u16_ffd1188[0][lane] + [info-> + clock_speed_index]; + if (reference_card == 5) + card_timing = + u16_ffd1188[1][lane] + [info-> + clock_speed_index]; + } + + info->training. + lane_timings[0][channel][slot][rank] + [lane] = + u8_FFFD1218[info-> + clock_speed_index]; + info->training. + lane_timings[1][channel][slot][rank] + [lane] = 256; + + for (tm_reg = 2; tm_reg < 4; tm_reg++) + info->training. + lane_timings[tm_reg] + [channel][slot][rank][lane] + = + u8_FFFD1240[channel] + [extended_silicon_revision] + [lane][2 * slot + + rank][info-> + clock_speed_index] + + info->max4048[channel] + + + u8_FFFD0C78[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][slot] + [rank][info-> + clock_speed_index] + + card_timing; + for (tm_reg = 0; tm_reg < 4; tm_reg++) + write_500(info, channel, + info->training. + lane_timings[tm_reg] + [channel][slot][rank] + [lane], + get_timing_register_addr + (lane, tm_reg, slot, + rank), 9, 0); + } + + card_timing_2 = 0; + if (!(extended_silicon_revision != 4 + || (info-> + populated_ranks_mask[channel] & 5) == + 5)) { + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & 0x1F) + == 3) + card_timing_2 = + u16_FFFE0EB8[0][info-> + clock_speed_index]; + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & 0x1F) + == 5) + card_timing_2 = + u16_FFFE0EB8[1][info-> + clock_speed_index]; + } + + for (i = 0; i < 3; i++) + write_500(info, channel, + (card_timing_2 + + info->max4048[channel] + + + u8_FFFD0EF8[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][info-> + clock_speed_index]), + u16_fffd0c50[i][slot][rank], + 8, 1); + write_500(info, channel, + (info->max4048[channel] + + u8_FFFD0C78[channel] + [extended_silicon_revision][info-> + mode4030 + [channel]] + [slot][rank][info-> + clock_speed_index]), + u16_fffd0c70[slot][rank], 7, 1); + } + if (!info->populated_ranks_mask[channel]) + continue; + for (i = 0; i < 3; i++) + write_500(info, channel, + (info->max4048[channel] + + info->avg4044[channel] + + + u8_FFFD17E0[channel] + [extended_silicon_revision][info-> + mode4030 + [channel]][info-> + clock_speed_index]), + u16_fffd0c68[i], 8, 1); + } +} + +static unsigned int fsbcycle_ps(struct raminfo *info) +{ + return 900000 / info->fsb_frequency; +} + +/* The time of DDR transfer in ps. */ +static unsigned int halfcycle_ps(struct raminfo *info) +{ + return 3750 / (info->clock_speed_index + 3); +} + +/* The time of clock cycle in ps. */ +static unsigned int cycle_ps(struct raminfo *info) +{ + return 2 * halfcycle_ps(info); +} + +/* Frequency in 1.(1)=10/9 MHz units. */ +static unsigned frequency_11(struct raminfo *info) +{ + return (info->clock_speed_index + 3) * 120; +} + +/* Frequency in 0.1 MHz units. */ +static unsigned frequency_01(struct raminfo *info) +{ + return 100 * frequency_11(info) / 9; +} + +static unsigned ps_to_halfcycles(struct raminfo *info, unsigned int ps) +{ + return (frequency_11(info) * 2) * ps / 900000; +} + +static unsigned ns_to_cycles(struct raminfo *info, unsigned int ns) +{ + return (frequency_11(info)) * ns / 900; +} + +static void compute_derived_timings(struct raminfo *info) +{ + unsigned channel, slot, rank; + int extended_silicon_revision; + int some_delay_1_ps; + int some_delay_2_ps; + int some_delay_2_halfcycles_ceil; + int some_delay_2_halfcycles_floor; + int some_delay_3_ps; + int some_delay_3_halfcycles; + int some_delay_3_ps_rounded; + int some_delay_1_cycle_ceil; + int some_delay_1_cycle_floor; + + some_delay_3_halfcycles = 0; + some_delay_3_ps_rounded = 0; + extended_silicon_revision = info->silicon_revision; + if (!info->silicon_revision) + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + if ((info-> + spd[channel][slot][MODULE_TYPE] & 0xF) == + 3) + extended_silicon_revision = 4; + if (info->board_lane_delay[7] < 5) + info->board_lane_delay[7] = 5; + info->revision_flag_1 = 2; + if (info->silicon_revision == 2 || info->silicon_revision == 3) + info->revision_flag_1 = 0; + if (info->revision < 16) + info->revision_flag_1 = 0; + + if (info->revision < 8) + info->revision_flag_1 = 0; + if (info->revision >= 8 && (info->silicon_revision == 0 + || info->silicon_revision == 1)) + some_delay_2_ps = 735; + else + some_delay_2_ps = 750; + + if (info->revision >= 0x10 && (info->silicon_revision == 0 + || info->silicon_revision == 1)) + some_delay_1_ps = 3929; + else + some_delay_1_ps = 3490; + + some_delay_1_cycle_floor = some_delay_1_ps / cycle_ps(info); + some_delay_1_cycle_ceil = some_delay_1_ps / cycle_ps(info); + if (some_delay_1_ps % cycle_ps(info)) + some_delay_1_cycle_ceil++; + else + some_delay_1_cycle_floor--; + info->some_delay_1_cycle_floor = some_delay_1_cycle_floor; + if (info->revision_flag_1) + some_delay_2_ps = halfcycle_ps(info) >> 6; + some_delay_2_ps += + max(some_delay_1_ps - 30, + 2 * halfcycle_ps(info) * (some_delay_1_cycle_ceil - 1) + 1000) + + 375; + some_delay_3_ps = + halfcycle_ps(info) - some_delay_2_ps % halfcycle_ps(info); + if (info->revision_flag_1) { + if (some_delay_3_ps < 150) + some_delay_3_halfcycles = 0; + else + some_delay_3_halfcycles = + (some_delay_3_ps << 6) / halfcycle_ps(info); + some_delay_3_ps_rounded = + halfcycle_ps(info) * some_delay_3_halfcycles >> 6; + } + some_delay_2_halfcycles_ceil = + (some_delay_2_ps + halfcycle_ps(info) - 1) / halfcycle_ps(info) - + 2 * (some_delay_1_cycle_ceil - 1); + if (info->revision_flag_1 && some_delay_3_ps < 150) + some_delay_2_halfcycles_ceil++; + some_delay_2_halfcycles_floor = some_delay_2_halfcycles_ceil; + if (info->revision < 0x10) + some_delay_2_halfcycles_floor = + some_delay_2_halfcycles_ceil - 1; + if (!info->revision_flag_1) + some_delay_2_halfcycles_floor++; + info->some_delay_2_halfcycles_ceil = some_delay_2_halfcycles_ceil; + info->some_delay_3_ps_rounded = some_delay_3_ps_rounded; + if ((info->populated_ranks[0][0][0] && info->populated_ranks[0][1][0]) + || (info->populated_ranks[1][0][0] + && info->populated_ranks[1][1][0])) + info->max_slots_used_in_channel = 2; + else + info->max_slots_used_in_channel = 1; + for (channel = 0; channel < 2; channel++) + write_mchbar32(0x244 + (channel << 10), + ((info->revision < 8) ? 1 : 0x200) + | ((2 - info->max_slots_used_in_channel) << 17) | + (channel << 21) | (info-> + some_delay_1_cycle_floor << + 18) | 0x9510); + if (info->max_slots_used_in_channel == 1) { + info->mode4030[0] = (count_ranks_in_channel(info, 0) == 2); + info->mode4030[1] = (count_ranks_in_channel(info, 1) == 2); + } else { + info->mode4030[0] = ((count_ranks_in_channel(info, 0) == 1) || (count_ranks_in_channel(info, 0) == 2)) ? 2 : 3; /* 2 if 1 or 2 ranks */ + info->mode4030[1] = ((count_ranks_in_channel(info, 1) == 1) + || (count_ranks_in_channel(info, 1) == + 2)) ? 2 : 3; + } + for (channel = 0; channel < NUM_CHANNELS; channel++) { + int max_of_unk; + int min_of_unk_2; + + int i, count; + int sum; + + if (!info->populated_ranks_mask[channel]) + continue; + + max_of_unk = 0; + min_of_unk_2 = 32767; + + sum = 0; + count = 0; + for (i = 0; i < 3; i++) { + int unk1; + if (info->revision < 8) + unk1 = + u8_FFFD1891[0][channel][info-> + clock_speed_index] + [i]; + else if (! + (info->revision >= 0x10 + || info->revision_flag_1)) + unk1 = + u8_FFFD1891[1][channel][info-> + clock_speed_index] + [i]; + else + unk1 = 0; + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) { + int a = 0; + int b = 0; + + if (!info-> + populated_ranks[channel][slot] + [rank]) + continue; + if (extended_silicon_revision == 4 + && (info-> + populated_ranks_mask[channel] & + 5) != 5) { + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & + 0x1F) == 3) { + a = u16_ffd1178[0] + [info-> + clock_speed_index]; + b = u16_fe0eb8[0][info-> + clock_speed_index]; + } else + if ((info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] + & 0x1F) == 5) { + a = u16_ffd1178[1] + [info-> + clock_speed_index]; + b = u16_fe0eb8[1][info-> + clock_speed_index]; + } + } + min_of_unk_2 = min(min_of_unk_2, a); + min_of_unk_2 = min(min_of_unk_2, b); + if (rank == 0) { + sum += a; + count++; + } + { + int t; + t = b + + u8_FFFD0EF8[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][info-> + clock_speed_index]; + if (unk1 >= t) + max_of_unk = + max(max_of_unk, + unk1 - t); + } + } + { + int t = + u8_FFFD17E0[channel] + [extended_silicon_revision][info-> + mode4030 + [channel]] + [info->clock_speed_index] + min_of_unk_2; + if (unk1 >= t) + max_of_unk = max(max_of_unk, unk1 - t); + } + } + + info->avg4044[channel] = sum / count; + info->max4048[channel] = max_of_unk; + } +} + +static void jedec_read(struct raminfo *info, + int channel, int slot, int rank, + int total_rank, u8 addr3, unsigned int value) +{ + /* Handle mirrored mapping. */ + if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1)) + addr3 = + (addr3 & 0xCF) | ((addr3 & 0x10) << 1) | ((addr3 >> 1) & + 0x10); + write_mchbar8(0x271, addr3 | (read_mchbar8(0x271) & 0xC1)); + write_mchbar8(0x671, addr3 | (read_mchbar8(0x671) & 0xC1)); + + /* Handle mirrored mapping. */ + if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1)) + value = + (value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8) + << 1); + + read32((value << 3) | (total_rank << 28)); + + write_mchbar8(0x271, (read_mchbar8(0x271) & 0xC3) | 2); + write_mchbar8(0x671, (read_mchbar8(0x671) & 0xC3) | 2); + + read32(total_rank << 28); +} + +enum { + MR1_RZQ12 = 512, + MR1_RZQ2 = 64, + MR1_RZQ4 = 4, + MR1_ODS34OHM = 2 +}; + +enum { + MR0_BT_INTERLEAVED = 8, + MR0_DLL_RESET_ON = 256 +}; + +enum { + MR2_RTT_WR_DISABLED = 0, + MR2_RZQ2 = 1 << 10 +}; + +static void jedec_init(struct raminfo *info) +{ + int write_recovery; + int channel, slot, rank; + int total_rank; + int dll_on; + int self_refresh_temperature; + int auto_self_refresh; + + auto_self_refresh = 1; + self_refresh_temperature = 1; + if (info->board_lane_delay[3] <= 10) { + if (info->board_lane_delay[3] <= 8) + write_recovery = info->board_lane_delay[3] - 4; + else + write_recovery = 5; + } else { + write_recovery = 6; + } + FOR_POPULATED_RANKS { + auto_self_refresh &= + (info->spd[channel][slot][THERMAL_AND_REFRESH] >> 2) & 1; + self_refresh_temperature &= + info->spd[channel][slot][THERMAL_AND_REFRESH] & 1; + } + if (auto_self_refresh == 1) + self_refresh_temperature = 0; + + dll_on = ((info->silicon_revision != 2 && info->silicon_revision != 3) + || (info->populated_ranks[0][0][0] + && info->populated_ranks[0][1][0]) + || (info->populated_ranks[1][0][0] + && info->populated_ranks[1][1][0])); + + total_rank = 0; + + for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) { + int rtt, rtt_wr = MR2_RTT_WR_DISABLED; + int rzq_reg58e; + + if (info->silicon_revision == 2 || info->silicon_revision == 3) { + rzq_reg58e = 64; + rtt = MR1_RZQ2; + if (info->clock_speed_index != 0) { + rzq_reg58e = 4; + if (info->populated_ranks_mask[channel] == 3) + rtt = MR1_RZQ4; + } + } else { + if ((info->populated_ranks_mask[channel] & 5) == 5) { + rtt = MR1_RZQ12; + rzq_reg58e = 64; + rtt_wr = MR2_RZQ2; + } else { + rzq_reg58e = 4; + rtt = MR1_RZQ4; + } + } + + write_mchbar16(0x588 + (channel << 10), 0x0); + write_mchbar16(0x58a + (channel << 10), 0x4); + write_mchbar16(0x58c + (channel << 10), rtt | MR1_ODS34OHM); + write_mchbar16(0x58e + (channel << 10), rzq_reg58e | 0x82); + write_mchbar16(0x590 + (channel << 10), 0x1282); + + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + if (info->populated_ranks[channel][slot][rank]) { + jedec_read(info, channel, slot, rank, + total_rank, 0x28, + rtt_wr | (info-> + clock_speed_index + << 3) + | (auto_self_refresh << 6) | + (self_refresh_temperature << + 7)); + jedec_read(info, channel, slot, rank, + total_rank, 0x38, 0); + jedec_read(info, channel, slot, rank, + total_rank, 0x18, + rtt | MR1_ODS34OHM); + jedec_read(info, channel, slot, rank, + total_rank, 6, + (dll_on << 12) | + (write_recovery << 9) + | ((info->cas_latency - 4) << + 4) | MR0_BT_INTERLEAVED | + MR0_DLL_RESET_ON); + total_rank++; + } + } +} + +static void program_modules_memory_map(struct raminfo *info, int pre_jedec) +{ + unsigned channel, slot, rank; + unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */ + unsigned int channel_0_non_interleaved; + + FOR_ALL_RANKS { + if (info->populated_ranks[channel][slot][rank]) { + total_mb[channel] += + pre_jedec ? 256 : (256 << info-> + density[channel][slot] >> info-> + is_x16_module[channel][slot]); + write_mchbar8(0x208 + rank + 2 * slot + (channel << 10), + (pre_jedec ? (1 | ((1 + 1) << 1)) + : (info-> + is_x16_module[channel][slot] | + ((info->density[channel][slot] + + 1) << 1))) | 0x80); + } + write_mchbar16(0x200 + (channel << 10) + 4 * slot + 2 * rank, + total_mb[channel] >> 6); + } + + info->total_memory_mb = total_mb[0] + total_mb[1]; + + info->interleaved_part_mb = + pre_jedec ? 0 : 2 * min(total_mb[0], total_mb[1]); + info->non_interleaved_part_mb = + total_mb[0] + total_mb[1] - info->interleaved_part_mb; + channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2; + write_mchbar32(0x100, + channel_0_non_interleaved | (info-> + non_interleaved_part_mb << + 16)); + if (!pre_jedec) + write_mchbar16(0x104, info->interleaved_part_mb); +} + +static void program_board_delay(struct raminfo *info) +{ + int cas_latency_shift; + int some_delay_ns; + int some_delay_3_half_cycles; + + unsigned channel, i; + int high_multiplier; + int lane_3_delay; + int cas_latency_derived; + + high_multiplier = 0; + some_delay_ns = 200; + some_delay_3_half_cycles = 4; + cas_latency_shift = info->silicon_revision == 0 + || info->silicon_revision == 1 ? 1 : 0; + if (info->revision < 8) { + some_delay_ns = 600; + cas_latency_shift = 0; + } + { + int speed_bit; + speed_bit = + ((info->clock_speed_index > 1 + || (info->silicon_revision != 2 + && info->silicon_revision != 3))) ^ (info->revision >= + 0x10); + write_500(info, 0, speed_bit | ((!info->use_ecc) << 1), 0x60e, + 3, 1); + write_500(info, 1, speed_bit | ((!info->use_ecc) << 1), 0x60e, + 3, 1); + if (info->revision >= 0x10 && info->clock_speed_index <= 1 + && (info->silicon_revision == 2 + || info->silicon_revision == 3)) + rmw_1d0(0x116, 5, 2, 4, 1); + } + write_mchbar32(0x120, + (1 << (info->max_slots_used_in_channel + 28)) | + 0x188e7f9f); + + write_mchbar8(0x124, + info->board_lane_delay[4] + + ((frequency_01(info) + 999) / 1000)); + write_mchbar16(0x125, 0x1360); + write_mchbar8(0x127, 0x40); + if (info->fsb_frequency < frequency_11(info) / 2) { + unsigned some_delay_2_half_cycles; + high_multiplier = 1; + some_delay_2_half_cycles = ps_to_halfcycles(info, + ((3 * + fsbcycle_ps(info)) + >> 1) + + (halfcycle_ps(info) + * + reg178_min[info-> + clock_speed_index] + >> 6) + + + 4 * + halfcycle_ps(info) + + 2230); + some_delay_3_half_cycles = + min((some_delay_2_half_cycles + + (frequency_11(info) * 2) * (28 - + some_delay_2_half_cycles) / + (frequency_11(info) * 2 - + 4 * (info->fsb_frequency))) >> 3, 7); + } + if (read_mchbar8(0x2ca9) & 1) + some_delay_3_half_cycles = 3; + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_mchbar32(0x220 + (channel << 10), + read_mchbar32(0x220 + + (channel << 10)) | 0x18001117); + write_mchbar32(0x224 + (channel << 10), + (info->max_slots_used_in_channel - 1) + | + ((info->cas_latency - 5 - + info->clock_speed_index) << 21) + | + ((info->max_slots_used_in_channel + + info->cas_latency - cas_latency_shift - + 4) << 16) + | ((info->cas_latency - cas_latency_shift - 4) << + 26) + | + ((info->cas_latency - info->clock_speed_index + + info->max_slots_used_in_channel - 6) << 8)); + write_mchbar32(0x228 + (channel << 10), + info->max_slots_used_in_channel); + write_mchbar8(0x239 + (channel << 10), 32); + write_mchbar32(0x248 + (channel << 10), + (high_multiplier << 24) | + (some_delay_3_half_cycles << 25) | 0x840000); + write_mchbar32(0x278 + (channel << 10), 0xc362042); + write_mchbar32(0x27c + (channel << 10), 0x8b000062); + write_mchbar32(0x24c + (channel << 10), + ((! !info-> + clock_speed_index) << 17) | (((2 + + info-> + clock_speed_index + - + (! !info-> + clock_speed_index))) + << 12) | 0x10200); + + write_mchbar8(0x267 + (channel << 10), 0x4); + write_mchbar16(0x272 + (channel << 10), 0x155); + write_mchbar32(0x2bc + (channel << 10), + (read_mchbar32(0x2bc + (channel << 10)) & + 0xFF000000) + | 0x707070); + + write_500(info, channel, + ((!info->populated_ranks[channel][1][1]) + | (!info->populated_ranks[channel][1][0] << 1) + | (!info->populated_ranks[channel][0][1] << 2) + | (!info->populated_ranks[channel][0][0] << 3)), + 0x4c9, 4, 1); + } + + write_mchbar8(0x2c4, ((1 + (info->clock_speed_index != 0)) << 6) | 0xC); + { + u8 freq_divisor = 2; + if (info->fsb_frequency == frequency_11(info)) + freq_divisor = 3; + else if (2 * info->fsb_frequency < 3 * (frequency_11(info) / 2)) + freq_divisor = 1; + else + freq_divisor = 2; + write_mchbar32(0x2c0, (freq_divisor << 11) | 0x6009c400); + } + + if (info->board_lane_delay[3] <= 10) { + if (info->board_lane_delay[3] <= 8) + lane_3_delay = info->board_lane_delay[3]; + else + lane_3_delay = 10; + } else { + lane_3_delay = 12; + } + cas_latency_derived = info->cas_latency - info->clock_speed_index + 2; + if (info->clock_speed_index > 1) + cas_latency_derived++; + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_mchbar32(0x240 + (channel << 10), + ((info->clock_speed_index == + 0) * 0x11000) | 0x1002100 | ((2 + + info-> + clock_speed_index) + << 4) | (info-> + cas_latency + - 3)); + write_500(info, channel, (info->clock_speed_index << 1) | 1, + 0x609, 6, 1); + write_500(info, channel, + info->clock_speed_index + 2 * info->cas_latency - 7, + 0x601, 6, 1); + + write_mchbar32(0x250 + (channel << 10), + ((lane_3_delay + info->clock_speed_index + + 9) << 6) + | (info->board_lane_delay[7] << 2) | (info-> + board_lane_delay + [4] << 16) + | (info->board_lane_delay[1] << 25) | (info-> + board_lane_delay + [1] << 29) + | 1); + write_mchbar32(0x254 + (channel << 10), + (info-> + board_lane_delay[1] >> 3) | ((info-> + board_lane_delay + [8] + + 4 * + info-> + use_ecc) << 6) | + 0x80 | (info->board_lane_delay[6] << 1) | (info-> + board_lane_delay + [2] << + 28) | + (cas_latency_derived << 16) | 0x4700000); + write_mchbar32(0x258 + (channel << 10), + ((info->board_lane_delay[5] + + info->clock_speed_index + + 9) << 12) | ((info->clock_speed_index - + info->cas_latency + 12) << 8) + | (info->board_lane_delay[2] << 17) | (info-> + board_lane_delay + [4] << 24) + | 0x47); + write_mchbar32(0x25c + (channel << 10), + (info->board_lane_delay[1] << 1) | (info-> + board_lane_delay + [0] << 8) | + 0x1da50000); + write_mchbar8(0x264 + (channel << 10), 0xff); + write_mchbar8(0x5f8 + (channel << 10), + (cas_latency_shift << 3) | info->use_ecc); + } + + program_modules_memory_map(info, 1); + + write_mchbar16(0x610, + (min(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) + | (read_mchbar16(0x610) & 0x1C3) | 0x3C); + write_mchbar16(0x612, read_mchbar16(0x612) | 0x100); + write_mchbar16(0x214, read_mchbar16(0x214) | 0x3E00); + for (i = 0; i < 8; i++) { + pci_mm_write32(QUICKPATH_BUS, 0, 1, 0x80 + 4 * i, + (info->total_memory_mb - 64) | !i | 2); + pci_mm_write32(QUICKPATH_BUS, 0, 1, 0xc0 + 4 * i, 0); + } +} + +#define BETTER_MEMORY_MAP 0 + +static void program_total_memory_map(struct raminfo *info) +{ + unsigned int TOM, TOLUD, TOUUD; + unsigned int quickpath_reserved; + unsigned int REMAPbase; + unsigned int uma_base_igd; + unsigned int uma_base_gtt; + int memory_remap; + unsigned int memory_map[8]; + int i; + unsigned int current_limit; + unsigned int tseg_base; + int uma_size_igd = 0, uma_size_gtt = 0; + + memset(memory_map, 0, sizeof(memory_map)); + +#if REAL + if (info->uma_enabled) { + u16 t = pci_mm_read16(NORTHBRIDGE, D0F0_GGC); + gav(t); + const int uma_sizes_gtt[16] = + { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; + /* Igd memory */ + const int uma_sizes_igd[16] = { + 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, + 256, 512 + }; + + uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF]; + uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; + } +#endif + + TOM = info->total_memory_mb; + if (TOM == 4096) + TOM = 4032; + TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); + TOLUD = ALIGN_DOWN(min(3072 + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) + , TOUUD), 64); + memory_remap = 0; + if (TOUUD - TOLUD > 64) { + memory_remap = 1; + REMAPbase = max(4096, TOUUD); + TOUUD = TOUUD - TOLUD + 4096; + } + if (TOUUD > 4096) + memory_map[2] = TOUUD | 1; + quickpath_reserved = 0; + + { + u32 t; + + gav(t = pci_mm_read32(QUICKPATH_BUS, 0, 1, 0x68)); + if (t & 0x800) + quickpath_reserved = + (1 << find_lowest_bit_set32(t >> 20)); + } + if (memory_remap) + TOUUD -= quickpath_reserved; + +#if !REAL + if (info->uma_enabled) { + u16 t = pci_mm_read16(NORTHBRIDGE, D0F0_GGC); + gav(t); + const int uma_sizes_gtt[16] = + { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; + /* Igd memory */ + const int uma_sizes_igd[16] = { + 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, + 256, 512 + }; + + uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF]; + uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; + } +#endif + + uma_base_igd = TOLUD - uma_size_igd; + uma_base_gtt = uma_base_igd - uma_size_gtt; + tseg_base = ALIGN_DOWN(uma_base_gtt, 64) - (CONFIG_SMM_TSEG_SIZE >> 20); + if (!memory_remap) + tseg_base -= quickpath_reserved; + tseg_base = ALIGN_DOWN(tseg_base, 8); + + pci_mm_write16(NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4); + pci_mm_write16(NORTHBRIDGE, D0F0_TOM, TOM >> 6); + if (memory_remap) { + pci_mm_write16(NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6); + pci_mm_write16(NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6); + } + pci_mm_write16(NORTHBRIDGE, D0F0_TOUUD, TOUUD); + + if (info->uma_enabled) { + pci_mm_write32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20); + pci_mm_write32(NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20); + } + pci_mm_write32(NORTHBRIDGE, TSEG, tseg_base << 20); + + current_limit = 0; + memory_map[0] = ALIGN_DOWN(uma_base_gtt, 64) | 1; + memory_map[1] = 4096; + for (i = 0; i < ARRAY_SIZE(memory_map); i++) { + current_limit = max(current_limit, memory_map[i] & ~1); + pci_mm_write32(QUICKPATH_BUS, 0, 1, 4 * i + 0x80, + (memory_map[i] & 1) | ALIGN_DOWN(current_limit - + 1, 64) | 2); + pci_mm_write32(QUICKPATH_BUS, 0, 1, 4 * i + 0xc0, 0); + } +} + +static void collect_system_info(struct raminfo *info) +{ + u32 capid0[3]; + int i; + unsigned channel; + + /* Wait for some bit, maybe TXT clear. */ + while (!(read8(0xfed40000) & (1 << 7))) ; + + if (!info->heci_bar) + gav(info->heci_bar = + pci_mm_read32(HECIDEV, HECIBAR) & 0xFFFFFFF8); + if (!info->memory_reserved_for_heci_mb) { + /* Wait for ME to be ready */ + intel_early_me_init(); + info->memory_reserved_for_heci_mb = intel_early_me_uma_size(); + } + + for (i = 0; i < 3; i++) + gav(capid0[i] = + pci_mm_read32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2))); + gav(info->revision = pci_mm_read8(NORTHBRIDGE, PCI_REVISION_ID)); + info->max_supported_clock_speed_index = (~capid0[1] & 7); + + if ((capid0[1] >> 11) & 1) + info->uma_enabled = 0; + else + gav(info->uma_enabled = + pci_mm_read8(NORTHBRIDGE, D0F0_DEVEN) & 8); + /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff */ + info->silicon_revision = 0; + + if (capid0[2] & 2) { + info->silicon_revision = 0; + info->max_supported_clock_speed_index = 2; + for (channel = 0; channel < NUM_CHANNELS; channel++) + if (info->populated_ranks[channel][0][0] + && (info->spd[channel][0][MODULE_TYPE] & 0xf) == + 3) { + info->silicon_revision = 2; + info->max_supported_clock_speed_index = 1; + } + } else { + switch (((capid0[2] >> 18) & 1) + 2 * ((capid0[1] >> 3) & 1)) { + case 1: + case 2: + info->silicon_revision = 3; + break; + case 3: + info->silicon_revision = 0; + break; + case 0: + info->silicon_revision = 2; + break; + } + switch (pci_mm_read16(NORTHBRIDGE, PCI_DEVICE_ID)) { + case 0x40: + info->silicon_revision = 0; + break; + case 0x48: + info->silicon_revision = 1; + break; + } + } +} + +static void write_training_data(struct raminfo *info) +{ + int tm, channel, slot, rank, lane; + if (info->revision < 8) + return; + + for (tm = 0; tm < 4; tm++) + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + for (lane = 0; lane < 9; lane++) + write_500(info, channel, + info-> + cached_training-> + lane_timings[tm] + [channel][slot][rank] + [lane], + get_timing_register_addr + (lane, tm, slot, + rank), 9, 0); + write_1d0(info->cached_training->reg_178, 0x178, 7, 1); + write_1d0(info->cached_training->reg_10b, 0x10b, 6, 1); +} + +static void dump_timings(struct raminfo *info) +{ +#if REAL + int channel, slot, rank, lane, i; + printk(BIOS_DEBUG, "Timings:\n"); + FOR_POPULATED_RANKS { + printk(BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel, + slot, rank); + for (lane = 0; lane < 9; lane++) { + printk(BIOS_DEBUG, "lane %d: ", lane); + for (i = 0; i < 4; i++) { + printk(BIOS_DEBUG, "%x (%x) ", + read_500(info, channel, + get_timing_register_addr + (lane, i, slot, rank), + 9), + info->training. + lane_timings[i][channel][slot][rank] + [lane]); + } + printk(BIOS_DEBUG, "\n"); + } + } + printk(BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), + info->training.reg_178); + printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), + info->training.reg_10b); +#endif +} + +static void save_timings(struct raminfo *info) +{ +#if CONFIG_EARLY_CBMEM_INIT + struct ram_training train; + struct mrc_data_container *mrcdata; + int output_len = ALIGN(sizeof(train), 16); + int channel, slot, rank, lane, i; + + train = info->training; + FOR_POPULATED_RANKS for (lane = 0; lane < 9; lane++) + for (i = 0; i < 4; i++) + train.lane_timings[i][channel][slot][rank][lane] = + read_500(info, channel, + get_timing_register_addr(lane, i, slot, + rank), 9); + train.reg_178 = read_1d0(0x178, 7); + train.reg_10b = read_1d0(0x10b, 6); + + /* Save the MRC S3 restore data to cbmem */ + cbmem_initialize(); + mrcdata = cbmem_add + (CBMEM_ID_MRCDATA, output_len + sizeof(struct mrc_data_container)); + + printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", + &train, mrcdata, output_len); + + mrcdata->mrc_signature = MRC_DATA_SIGNATURE; + mrcdata->mrc_data_size = output_len; + mrcdata->reserved = 0; + memcpy(mrcdata->mrc_data, &train, sizeof(train)); + + /* Zero the unused space in aligned buffer. */ + if (output_len > sizeof(train)) + memset(mrcdata->mrc_data + sizeof(train), 0, + output_len - sizeof(train)); + + mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, + mrcdata->mrc_data_size); +#endif +} + +#if REAL +static const struct ram_training *get_cached_training(void) +{ + struct mrc_data_container *cont; + cont = find_current_mrc_cache(); + if (!cont) + return 0; + return (void *)cont->mrc_data; +} +#endif + +/* FIXME: add timeout. */ +static void wait_heci_ready(void) +{ + while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ; // = 0x8000000c + write32((DEFAULT_HECIBAR | 0x4), + (read32(DEFAULT_HECIBAR | 0x4) & ~0x10) | 0xc); +} + +/* FIXME: add timeout. */ +static void wait_heci_cb_avail(int len) +{ + union { + struct mei_csr csr; + u32 raw; + } csr; + + while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ; + + do + csr.raw = read32(DEFAULT_HECIBAR | 0x4); + while (len > + csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - + csr.csr.buffer_read_ptr)); +} + +static void send_heci_packet(struct mei_header *head, u32 * payload) +{ + int len = (head->length + 3) / 4; + int i; + + wait_heci_cb_avail(len + 1); + + /* FIXME: handle leftovers correctly. */ + write32(DEFAULT_HECIBAR | 0, *(u32 *) head); + for (i = 0; i < len - 1; i++) + write32(DEFAULT_HECIBAR | 0, payload[i]); + + write32(DEFAULT_HECIBAR | 0, payload[i] & ((1 << (8 * len)) - 1)); + write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 0x4); +} + +static void +send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress) +{ + struct mei_header head; + int maxlen; + + wait_heci_ready(); + maxlen = (read32(DEFAULT_HECIBAR | 0x4) >> 24) * 4 - 4; + + while (len) { + int cur = len; + if (cur > maxlen) { + cur = maxlen; + head.is_complete = 0; + } else + head.is_complete = 1; + head.length = cur; + head.reserved = 0; + head.client_address = clientaddress; + head.host_address = hostaddress; + send_heci_packet(&head, (u32 *) msg); + len -= cur; + msg += cur; + } +} + +/* FIXME: Add timeout. */ +static int +recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet, + u32 * packet_size) +{ + union { + struct mei_csr csr; + u32 raw; + } csr; + int i = 0; + + write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 2); + do { + csr.raw = read32(DEFAULT_HECIBAR | 0xc); +#if !REAL + if (i++ > 346) + return -1; +#endif + } + while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr); + *(u32 *) head = read32(DEFAULT_HECIBAR | 0x8); + if (!head->length) { + write32(DEFAULT_HECIBAR | 0x4, + read32(DEFAULT_HECIBAR | 0x4) | 2); + *packet_size = 0; + return 0; + } + if (head->length + 4 > 4 * csr.csr.buffer_depth + || head->length > *packet_size) { + *packet_size = 0; + return -1; + } + + do + csr.raw = read32(DEFAULT_HECIBAR | 0xc); + while ((head->length + 3) >> 2 > + csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr); + + for (i = 0; i < (head->length + 3) >> 2; i++) + packet[i++] = read32(DEFAULT_HECIBAR | 0x8); + *packet_size = head->length; + if (!csr.csr.ready) + *packet_size = 0; + write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 4); + return 0; +} + +/* FIXME: Add timeout. */ +static int +recv_heci_message(struct raminfo *info, u32 * message, u32 * message_size) +{ + struct mei_header head; + int current_position; + + current_position = 0; + while (1) { + u32 current_size; + current_size = *message_size - current_position; + if (recv_heci_packet + (info, &head, message + (current_position >> 2), + &current_size) == -1) + break; + if (!current_size) + break; + current_position += current_size; + if (head.is_complete) { + *message_size = current_position; + return 0; + } + + if (current_position >= *message_size) + break; + } + *message_size = 0; + return -1; +} + +static void send_heci_uma_message(struct raminfo *info) +{ + struct uma_reply { + u8 group_id; + u8 command; + u8 reserved; + u8 result; + u8 field2; + u8 unk3[0x48 - 4 - 1]; + } __attribute__ ((packed)) reply; + struct uma_message { + u8 group_id; + u8 cmd; + u8 reserved; + u8 result; + u32 c2; + u64 heci_uma_addr; + u32 memory_reserved_for_heci_mb; + u16 c3; + } __attribute__ ((packed)) msg = { + 0, MKHI_SET_UMA, 0, 0, + 0x82, + info->heci_uma_addr, info->memory_reserved_for_heci_mb, 0}; + u32 reply_size; + + send_heci_message((u8 *) & msg, sizeof(msg), 0, 7); + + reply_size = sizeof(reply); + if (recv_heci_message(info, (u32 *) & reply, &reply_size) == -1) + return; + + if (reply.command != (MKHI_SET_UMA | (1 << 7))) + die("HECI init failed\n"); +} + +static void setup_heci_uma(struct raminfo *info) +{ + u32 reg44; + + reg44 = pci_mm_read32(HECIDEV, 0x44); // = 0x80010020 + info->memory_reserved_for_heci_mb = 0; + info->heci_uma_addr = 0; + if (!((reg44 & 0x10000) && !(pci_mm_read32(HECIDEV, 0x40) & 0x20))) + return; + + info->heci_bar = pci_mm_read32(HECIDEV, 0x10) & 0xFFFFFFF0; + info->memory_reserved_for_heci_mb = reg44 & 0x3f; + info->heci_uma_addr = + ((u64) + ((((u64) pci_mm_read16(NORTHBRIDGE, D0F0_TOM)) << 6) - + info->memory_reserved_for_heci_mb)) << 20; + + pci_mm_read32(NORTHBRIDGE, DMIBAR); + if (info->memory_reserved_for_heci_mb) { + write32(DEFAULT_DMIBAR | 0x14, + read32(DEFAULT_DMIBAR | 0x14) & ~0x80); + write32(DEFAULT_RCBA | 0x14, + read32(DEFAULT_RCBA | 0x14) & ~0x80); + write32(DEFAULT_DMIBAR | 0x20, + read32(DEFAULT_DMIBAR | 0x20) & ~0x80); + write32(DEFAULT_RCBA | 0x20, + read32(DEFAULT_RCBA | 0x20) & ~0x80); + write32(DEFAULT_DMIBAR | 0x2c, + read32(DEFAULT_DMIBAR | 0x2c) & ~0x80); + write32(DEFAULT_RCBA | 0x30, + read32(DEFAULT_RCBA | 0x30) & ~0x80); + write32(DEFAULT_DMIBAR | 0x38, + read32(DEFAULT_DMIBAR | 0x38) & ~0x80); + write32(DEFAULT_RCBA | 0x40, + read32(DEFAULT_RCBA | 0x40) & ~0x80); + + write32(DEFAULT_RCBA | 0x40, 0x87000080); // OK + write32(DEFAULT_DMIBAR | 0x38, 0x87000080); // OK + while (read16(DEFAULT_RCBA | 0x46) & 2 + && read16(DEFAULT_DMIBAR | 0x3e) & 2) ; + } + + write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb); + + send_heci_uma_message(info); + + pci_mm_write32(HECIDEV, 0x10, 0x0); + pci_mm_write8(HECIDEV, 0x4, 0x0); + +} + +static int have_match_ranks(struct raminfo *info, int channel, int ranks) +{ + int ranks_in_channel; + ranks_in_channel = info->populated_ranks[channel][0][0] + + info->populated_ranks[channel][0][1] + + info->populated_ranks[channel][1][0] + + info->populated_ranks[channel][1][1]; + + /* empty channel */ + if (ranks_in_channel == 0) + return 1; + + if (ranks_in_channel != ranks) + return 0; + /* single slot */ + if (info->populated_ranks[channel][0][0] != + info->populated_ranks[channel][1][0]) + return 1; + if (info->populated_ranks[channel][0][1] != + info->populated_ranks[channel][1][1]) + return 1; + if (info->is_x16_module[channel][0] != info->is_x16_module[channel][1]) + return 0; + if (info->density[channel][0] != info->density[channel][1]) + return 0; + return 1; +} + +#define WTF1 1 + +static void read_4090(struct raminfo *info) +{ + int i, channel, slot, rank, lane; + for (i = 0; i < 2; i++) + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + for (lane = 0; lane < 9; lane++) + info->training. + lane_timings[0][i][slot][rank][lane] + = 32; + + for (i = 1; i < 4; i++) + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + for (lane = 0; lane < 9; lane++) { + info->training. + lane_timings[i][channel] + [slot][rank][lane] = + read_500(info, channel, + get_timing_register_addr + (lane, i, slot, + rank), 9) + + (i == 1) * 11; // !!!! + } + +} + +static u32 get_etalon2(int flip, u32 addr) +{ + const u16 invmask[] = { + 0xaaaa, 0x6db6, 0x4924, 0xeeee, 0xcccc, 0x8888, 0x7bde, 0x739c, + 0x6318, 0x4210, 0xefbe, 0xcf3c, 0x8e38, 0x0c30, 0x0820 + }; + u32 ret; + u32 comp4 = addr / 480; + addr %= 480; + u32 comp1 = addr & 0xf; + u32 comp2 = (addr >> 4) & 1; + u32 comp3 = addr >> 5; + + if (comp4) + ret = 0x1010101 << (comp4 - 1); + else + ret = 0; + if (flip ^ (((invmask[comp3] >> comp1) ^ comp2) & 1)) + ret = ~ret; + + return ret; +} + +static void disable_cache(void) +{ + my_write_msr(MTRRphysBase_MSR(3), 0); + my_write_msr(MTRRphysMask_MSR(3), 0); +} + +static void enable_cache(unsigned int base, unsigned int size) +{ + my_write_msr(MTRRphysBase_MSR(3), base | MTRR_TYPE_WRPROT); + my_write_msr(MTRRphysMask_MSR(3), 0x0000000f00000000LL + | ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRRdefTypeEn) + & 0xffffffff)); +} + +static void flush_cache(u32 start, u32 size) +{ + u32 end; + u32 addr; + + end = start + (ALIGN_DOWN(size + 4096, 4096)); + for (addr = start; addr < end; addr += 64) + clflush(addr); +} + +static void clear_errors(void) +{ + pci_mm_write8(NORTHBRIDGE, 0xc0, 0x01); +} + +static void write_testing(struct raminfo *info, int totalrank, int flip) +{ + int nwrites = 0; + /* in 8-byte units. */ + u32 offset; + u32 base; + + base = totalrank << 28; + for (offset = 0; offset < 9 * 480; offset += 2) { + write32(base + offset * 8, get_etalon2(flip, offset)); + write32(base + offset * 8 + 4, get_etalon2(flip, offset)); + write32(base + offset * 8 + 8, get_etalon2(flip, offset + 1)); + write32(base + offset * 8 + 12, get_etalon2(flip, offset + 1)); + nwrites += 4; + if (nwrites >= 320) { + clear_errors(); + nwrites = 0; + } + } +} + +static u8 check_testing(struct raminfo *info, u8 total_rank, int flip) +{ + u8 failmask = 0; + int i; + int comp1, comp2, comp3; + u32 failxor[2] = { 0, 0 }; + + enable_cache((total_rank << 28), 1728 * 5 * 4); + + for (comp3 = 0; comp3 < 9 && failmask != 0xff; comp3++) { + for (comp1 = 0; comp1 < 4; comp1++) + for (comp2 = 0; comp2 < 60; comp2++) { + u32 re[4]; + u32 curroffset = + comp3 * 8 * 60 + 2 * comp1 + 8 * comp2; + read128((total_rank << 28) | (curroffset << 3), + (u64 *) re); + failxor[0] |= + get_etalon2(flip, curroffset) ^ re[0]; + failxor[1] |= + get_etalon2(flip, curroffset) ^ re[1]; + failxor[0] |= + get_etalon2(flip, curroffset | 1) ^ re[2]; + failxor[1] |= + get_etalon2(flip, curroffset | 1) ^ re[3]; + } + for (i = 0; i < 8; i++) + if ((0xff << (8 * (i % 4))) & failxor[i / 4]) + failmask |= 1 << i; + } + disable_cache(); + flush_cache((total_rank << 28), 1728 * 5 * 4); + return failmask; +} + +const u32 seed1[0x18] = { + 0x3a9d5ab5, 0x576cb65b, 0x555773b6, 0x2ab772ee, + 0x555556ee, 0x3a9d5ab5, 0x576cb65b, 0x555773b6, + 0x2ab772ee, 0x555556ee, 0x5155a555, 0x5155a555, + 0x5155a555, 0x5155a555, 0x3a9d5ab5, 0x576cb65b, + 0x555773b6, 0x2ab772ee, 0x555556ee, 0x55d6b4a5, + 0x366d6b3a, 0x2ae5ddbb, 0x3b9ddbb7, 0x55d6b4a5, +}; + +static u32 get_seed2(int a, int b) +{ + const u32 seed2[5] = { + 0x55555555, 0x33333333, 0x2e555a55, 0x55555555, + 0x5b6db6db, + }; + u32 r; + r = seed2[(a + (a >= 10)) / 5]; + return b ? ~r : r; +} + +static int make_shift(int comp2, int comp5, int x) +{ + const u8 seed3[32] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x38, 0x1c, 0x3c, 0x18, 0x38, 0x38, + 0x38, 0x38, 0x38, 0x38, 0x0f, 0x0f, 0x0f, 0x0f, + 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, + }; + + return (comp2 - ((seed3[comp5] >> (x & 7)) & 1)) & 0x1f; +} + +static u32 get_etalon(int flip, u32 addr) +{ + u32 mask_byte = 0; + int comp1 = (addr >> 1) & 1; + int comp2 = (addr >> 3) & 0x1f; + int comp3 = (addr >> 8) & 0xf; + int comp4 = (addr >> 12) & 0xf; + int comp5 = (addr >> 16) & 0x1f; + u32 mask_bit = ~(0x10001 << comp3); + u32 part1; + u32 part2; + int byte; + + part2 = + ((seed1[comp5] >> + make_shift(comp2, comp5, + (comp3 >> 3) | (comp1 << 2) | 2)) & 1) ^ flip; + part1 = + ((seed1[comp5] >> + make_shift(comp2, comp5, + (comp3 >> 3) | (comp1 << 2) | 0)) & 1) ^ flip; + + for (byte = 0; byte < 4; byte++) + if ((get_seed2(comp5, comp4) >> + make_shift(comp2, comp5, (byte | (comp1 << 2)))) & 1) + mask_byte |= 0xff << (8 * byte); + + return (mask_bit & mask_byte) | (part1 << comp3) | (part2 << + (comp3 + 16)); +} + +static void +write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block, + char flip) +{ + int i; + for (i = 0; i < 2048; i++) + write32((totalrank << 28) | (region << 25) | (block << 16) | + (i << 2), get_etalon(flip, (block << 16) | (i << 2))); +} + +static u8 +check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block, + char flip) +{ + u8 failmask = 0; + u32 failxor[2]; + int i; + int comp1, comp2, comp3; + + failxor[0] = 0; + failxor[1] = 0; + + enable_cache(totalrank << 28, 134217728); + for (comp3 = 0; comp3 < 2 && failmask != 0xff; comp3++) { + for (comp1 = 0; comp1 < 16; comp1++) + for (comp2 = 0; comp2 < 64; comp2++) { + u32 addr = + (totalrank << 28) | (region << 25) | (block + << 16) + | (comp3 << 12) | (comp2 << 6) | (comp1 << + 2); + failxor[comp1 & 1] |= + read32(addr) ^ get_etalon(flip, addr); + } + for (i = 0; i < 8; i++) + if ((0xff << (8 * (i % 4))) & failxor[i / 4]) + failmask |= 1 << i; + } + disable_cache(); + flush_cache((totalrank << 28) | (region << 25) | (block << 16), 16384); + return failmask; +} + +static int check_bounded(unsigned short *vals, u16 bound) +{ + int i; + + for (i = 0; i < 8; i++) + if (vals[i] < bound) + return 0; + return 1; +} + +enum state { + BEFORE_USABLE = 0, AT_USABLE = 1, AT_MARGIN = 2, COMPLETE = 3 +}; + +static int validate_state(enum state *in) +{ + int i; + for (i = 0; i < 8; i++) + if (in[i] != COMPLETE) + return 0; + return 1; +} + +static void +do_fsm(enum state *state, u16 * counter, + u8 fail_mask, int margin, int uplimit, + u8 * res_low, u8 * res_high, u8 val) +{ + int lane; + + for (lane = 0; lane < 8; lane++) { + int is_fail = (fail_mask >> lane) & 1; + switch (state[lane]) { + case BEFORE_USABLE: + if (!is_fail) { + counter[lane] = 1; + state[lane] = AT_USABLE; + break; + } + counter[lane] = 0; + state[lane] = BEFORE_USABLE; + break; + case AT_USABLE: + if (!is_fail) { + ++counter[lane]; + if (counter[lane] >= margin) { + state[lane] = AT_MARGIN; + res_low[lane] = val - margin + 1; + break; + } + state[lane] = 1; + break; + } + counter[lane] = 0; + state[lane] = BEFORE_USABLE; + break; + case AT_MARGIN: + if (is_fail) { + state[lane] = COMPLETE; + res_high[lane] = val - 1; + } else { + counter[lane]++; + state[lane] = AT_MARGIN; + if (val == uplimit) { + state[lane] = COMPLETE; + res_high[lane] = uplimit; + } + } + break; + case COMPLETE: + break; + } + } +} + +static void +train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank, + u8 total_rank, u8 reg_178, int first_run, int niter, + timing_bounds_t * timings) +{ + int lane; + enum state state[8]; + u16 count[8]; + u8 lower_usable[8]; + u8 upper_usable[8]; + unsigned short num_sucessfully_checked[8]; + u8 secondary_total_rank; + u8 reg1b3; + + if (info->populated_ranks_mask[1]) { + if (channel == 1) + secondary_total_rank = + info->populated_ranks[1][0][0] + + info->populated_ranks[1][0][1] + + info->populated_ranks[1][1][0] + + info->populated_ranks[1][1][1]; + else + secondary_total_rank = 0; + } else + secondary_total_rank = total_rank; + + { + int i; + for (i = 0; i < 8; i++) + state[i] = BEFORE_USABLE; + } + + if (!first_run) { + int is_all_ok = 1; + for (lane = 0; lane < 8; lane++) + if (timings[reg_178][channel][slot][rank][lane]. + smallest == + timings[reg_178][channel][slot][rank][lane]. + largest) { + timings[reg_178][channel][slot][rank][lane]. + smallest = 0; + timings[reg_178][channel][slot][rank][lane]. + largest = 0; + is_all_ok = 0; + } + if (is_all_ok) { + int i; + for (i = 0; i < 8; i++) + state[i] = COMPLETE; + } + } + + for (reg1b3 = 0; reg1b3 < 0x30 && !validate_state(state); reg1b3++) { + u8 failmask = 0; + write_1d0(reg1b3 ^ 32, 0x1b3, 6, 1); + write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1); + failmask = check_testing(info, total_rank, 0); + write_mchbar32(0xfb0, read_mchbar32(0xfb0) | 0x00030000); + do_fsm(state, count, failmask, 5, 47, lower_usable, + upper_usable, reg1b3); + } + + if (reg1b3) { + write_1d0(0, 0x1b3, 6, 1); + write_1d0(0, 0x1a3, 6, 1); + for (lane = 0; lane < 8; lane++) { + if (state[lane] == COMPLETE) { + timings[reg_178][channel][slot][rank][lane]. + smallest = + lower_usable[lane] + + (info->training. + lane_timings[0][channel][slot][rank][lane] + & 0x3F) - 32; + timings[reg_178][channel][slot][rank][lane]. + largest = + upper_usable[lane] + + (info->training. + lane_timings[0][channel][slot][rank][lane] + & 0x3F) - 32; + } + } + } + + if (!first_run) { + for (lane = 0; lane < 8; lane++) + if (state[lane] == COMPLETE) { + write_500(info, channel, + timings[reg_178][channel][slot][rank] + [lane].smallest, + get_timing_register_addr(lane, 0, + slot, rank), + 9, 1); + write_500(info, channel, + timings[reg_178][channel][slot][rank] + [lane].smallest + + info->training. + lane_timings[1][channel][slot][rank] + [lane] + - + info->training. + lane_timings[0][channel][slot][rank] + [lane], get_timing_register_addr(lane, + 1, + slot, + rank), + 9, 1); + num_sucessfully_checked[lane] = 0; + } else + num_sucessfully_checked[lane] = -1; + + do { + u8 failmask = 0; + int i; + for (i = 0; i < niter; i++) { + if (failmask == 0xFF) + break; + failmask |= + check_testing_type2(info, total_rank, 2, i, + 0); + failmask |= + check_testing_type2(info, total_rank, 3, i, + 1); + } + write_mchbar32(0xfb0, + read_mchbar32(0xfb0) | 0x00030000); + for (lane = 0; lane < 8; lane++) + if (num_sucessfully_checked[lane] != 0xffff) { + if ((1 << lane) & failmask) { + if (timings[reg_178][channel] + [slot][rank][lane]. + largest <= + timings[reg_178][channel] + [slot][rank][lane].smallest) + num_sucessfully_checked + [lane] = -1; + else { + num_sucessfully_checked + [lane] = 0; + timings[reg_178] + [channel][slot] + [rank][lane]. + smallest++; + write_500(info, channel, + timings + [reg_178] + [channel] + [slot][rank] + [lane]. + smallest, + get_timing_register_addr + (lane, 0, + slot, rank), + 9, 1); + write_500(info, channel, + timings + [reg_178] + [channel] + [slot][rank] + [lane]. + smallest + + info-> + training. + lane_timings + [1][channel] + [slot][rank] + [lane] + - + info-> + training. + lane_timings + [0][channel] + [slot][rank] + [lane], + get_timing_register_addr + (lane, 1, + slot, rank), + 9, 1); + } + } else + num_sucessfully_checked[lane]++; + } + } + while (!check_bounded(num_sucessfully_checked, 2)); + + for (lane = 0; lane < 8; lane++) + if (state[lane] == COMPLETE) { + write_500(info, channel, + timings[reg_178][channel][slot][rank] + [lane].largest, + get_timing_register_addr(lane, 0, + slot, rank), + 9, 1); + write_500(info, channel, + timings[reg_178][channel][slot][rank] + [lane].largest + + info->training. + lane_timings[1][channel][slot][rank] + [lane] + - + info->training. + lane_timings[0][channel][slot][rank] + [lane], get_timing_register_addr(lane, + 1, + slot, + rank), + 9, 1); + num_sucessfully_checked[lane] = 0; + } else + num_sucessfully_checked[lane] = -1; + + do { + int failmask = 0; + int i; + for (i = 0; i < niter; i++) { + if (failmask == 0xFF) + break; + failmask |= + check_testing_type2(info, total_rank, 2, i, + 0); + failmask |= + check_testing_type2(info, total_rank, 3, i, + 1); + } + + write_mchbar32(0xfb0, + read_mchbar32(0xfb0) | 0x00030000); + for (lane = 0; lane < 8; lane++) { + if (num_sucessfully_checked[lane] != 0xffff) { + if ((1 << lane) & failmask) { + if (timings[reg_178][channel] + [slot][rank][lane]. + largest <= + timings[reg_178][channel] + [slot][rank][lane]. + smallest) { + num_sucessfully_checked + [lane] = -1; + } else { + num_sucessfully_checked + [lane] = 0; + timings[reg_178] + [channel][slot] + [rank][lane]. + largest--; + write_500(info, channel, + timings + [reg_178] + [channel] + [slot][rank] + [lane]. + largest, + get_timing_register_addr + (lane, 0, + slot, rank), + 9, 1); + write_500(info, channel, + timings + [reg_178] + [channel] + [slot][rank] + [lane]. + largest + + info-> + training. + lane_timings + [1][channel] + [slot][rank] + [lane] + - + info-> + training. + lane_timings + [0][channel] + [slot][rank] + [lane], + get_timing_register_addr + (lane, 1, + slot, rank), + 9, 1); + } + } else + num_sucessfully_checked[lane]++; + } + } + } + while (!check_bounded(num_sucessfully_checked, 3)); + + for (lane = 0; lane < 8; lane++) { + write_500(info, channel, + info->training. + lane_timings[0][channel][slot][rank][lane], + get_timing_register_addr(lane, 0, slot, rank), + 9, 1); + write_500(info, channel, + info->training. + lane_timings[1][channel][slot][rank][lane], + get_timing_register_addr(lane, 1, slot, rank), + 9, 1); + if (timings[reg_178][channel][slot][rank][lane]. + largest <= + timings[reg_178][channel][slot][rank][lane]. + smallest) { + timings[reg_178][channel][slot][rank][lane]. + largest = 0; + timings[reg_178][channel][slot][rank][lane]. + smallest = 0; + } + } + } +} + +static void set_10b(struct raminfo *info, u8 val) +{ + int channel; + int slot, rank; + int lane; + + if (read_1d0(0x10b, 6) == val) + return; + + write_1d0(val, 0x10b, 6, 1); + + FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 9; lane++) { + u16 reg_500; + reg_500 = read_500(info, channel, + get_timing_register_addr(lane, 0, slot, + rank), 9); + if (val == 1) { + if (lut16[info->clock_speed_index] <= reg_500) + reg_500 -= lut16[info->clock_speed_index]; + else + reg_500 = 0; + } else { + reg_500 += lut16[info->clock_speed_index]; + } + write_500(info, channel, reg_500, + get_timing_register_addr(lane, 0, slot, rank), 9, 1); + } +} + +static void set_ecc(int onoff) +{ + int channel; + for (channel = 0; channel < NUM_CHANNELS; channel++) { + u8 t; + t = read_mchbar8((channel << 10) + 0x5f8); + if (onoff) + t |= 1; + else + t &= ~1; + write_mchbar8((channel << 10) + 0x5f8, t); + } +} + +static void set_178(u8 val) +{ + if (val >= 31) + val = val - 31; + else + val = 63 - val; + + write_1d0(2 * val, 0x178, 7, 1); +} + +static void +write_500_timings_type(struct raminfo *info, int channel, int slot, int rank, + int type) +{ + int lane; + + for (lane = 0; lane < 8; lane++) + write_500(info, channel, + info->training. + lane_timings[type][channel][slot][rank][lane], + get_timing_register_addr(lane, type, slot, rank), 9, + 0); +} + +static void +try_timing_offsets(struct raminfo *info, int channel, + int slot, int rank, int totalrank) +{ + u16 count[8]; + enum state state[8]; + u8 lower_usable[8], upper_usable[8]; + int lane; + int i; + int flip = 1; + int timing_offset; + + for (i = 0; i < 8; i++) + state[i] = BEFORE_USABLE; + + memset(count, 0, sizeof(count)); + + for (lane = 0; lane < 8; lane++) + write_500(info, channel, + info->training. + lane_timings[2][channel][slot][rank][lane] + 32, + get_timing_register_addr(lane, 3, slot, rank), 9, 1); + + for (timing_offset = 0; !validate_state(state) && timing_offset < 64; + timing_offset++) { + u8 failmask; + write_1d0(timing_offset ^ 32, 0x1bb, 6, 1); + failmask = 0; + for (i = 0; i < 2 && failmask != 0xff; i++) { + flip = !flip; + write_testing(info, totalrank, flip); + failmask |= check_testing(info, totalrank, flip); + } + do_fsm(state, count, failmask, 10, 63, lower_usable, + upper_usable, timing_offset); + } + write_1d0(0, 0x1bb, 6, 1); + dump_timings(info); + if (!validate_state(state)) + die("Couldn't discover DRAM timings (1)\n"); + + for (lane = 0; lane < 8; lane++) { + u8 bias = 0; + + if (info->silicon_revision) { + int usable_length; + + usable_length = upper_usable[lane] - lower_usable[lane]; + if (usable_length >= 20) { + bias = usable_length / 2 - 10; + if (bias >= 2) + bias = 2; + } + } + write_500(info, channel, + info->training. + lane_timings[2][channel][slot][rank][lane] + + (upper_usable[lane] + lower_usable[lane]) / 2 - bias, + get_timing_register_addr(lane, 3, slot, rank), 9, 1); + info->training.timing2_bounds[channel][slot][rank][lane][0] = + info->training.lane_timings[2][channel][slot][rank][lane] + + lower_usable[lane]; + info->training.timing2_bounds[channel][slot][rank][lane][1] = + info->training.lane_timings[2][channel][slot][rank][lane] + + upper_usable[lane]; + info->training.timing2_offset[channel][slot][rank][lane] = + info->training.lane_timings[2][channel][slot][rank][lane]; + } +} + +static u8 +choose_training(struct raminfo *info, int channel, int slot, int rank, + int lane, timing_bounds_t * timings, u8 center_178) +{ + u16 central_weight; + u16 side_weight; + unsigned int sum = 0, count = 0; + u8 span; + u8 lower_margin, upper_margin; + u8 reg_178; + u8 result; + + span = 12; + central_weight = 20; + side_weight = 20; + if (info->silicon_revision == 1 && channel == 1) { + central_weight = 5; + side_weight = 20; + if ((info-> + populated_ranks_mask[1] ^ (info-> + populated_ranks_mask[1] >> 2)) & + 1) + span = 18; + } + if ((info->populated_ranks_mask[0] & 5) == 5) { + central_weight = 20; + side_weight = 20; + } + if (info->clock_speed_index >= 2 + && (info->populated_ranks_mask[0] & 5) == 5 && slot == 1) { + if (info->silicon_revision == 1) { + switch (channel) { + case 0: + if (lane == 1) { + central_weight = 10; + side_weight = 20; + } + break; + case 1: + if (lane == 6) { + side_weight = 5; + central_weight = 20; + } + break; + } + } + if (info->silicon_revision == 0 && channel == 0 && lane == 0) { + side_weight = 5; + central_weight = 20; + } + } + for (reg_178 = center_178 - span; reg_178 <= center_178 + span; + reg_178 += span) { + u8 smallest; + u8 largest; + largest = timings[reg_178][channel][slot][rank][lane].largest; + smallest = timings[reg_178][channel][slot][rank][lane].smallest; + if (largest - smallest + 1 >= 5) { + unsigned int weight; + if (reg_178 == center_178) + weight = central_weight; + else + weight = side_weight; + sum += weight * (largest + smallest); + count += weight; + } + } + dump_timings(info); + if (count == 0) + die("Couldn't discover DRAM timings (2)\n"); + result = sum / (2 * count); + lower_margin = + result - timings[center_178][channel][slot][rank][lane].smallest; + upper_margin = + timings[center_178][channel][slot][rank][lane].largest - result; + if (upper_margin < 10 && lower_margin > 10) + result -= min(lower_margin - 10, 10 - upper_margin); + if (upper_margin > 10 && lower_margin < 10) + result += min(upper_margin - 10, 10 - lower_margin); + return result; +} + +#define STANDARD_MIN_MARGIN 5 + +static u8 choose_reg178(struct raminfo *info, timing_bounds_t * timings) +{ + u16 margin[64]; + int lane, rank, slot, channel; + u8 reg178; + int count = 0, sum = 0; + + for (reg178 = reg178_min[info->clock_speed_index]; + reg178 < reg178_max[info->clock_speed_index]; + reg178 += reg178_step[info->clock_speed_index]) { + margin[reg178] = -1; + FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { + int curmargin = + timings[reg178][channel][slot][rank][lane].largest - + timings[reg178][channel][slot][rank][lane]. + smallest + 1; + if (curmargin < margin[reg178]) + margin[reg178] = curmargin; + } + if (margin[reg178] >= STANDARD_MIN_MARGIN) { + u16 weight; + weight = margin[reg178] - STANDARD_MIN_MARGIN; + sum += weight * reg178; + count += weight; + } + } + dump_timings(info); + if (count == 0) + die("Couldn't discover DRAM timings (3)\n"); + + u8 threshold; + + for (threshold = 30; threshold >= 5; threshold--) { + int usable_length = 0; + int smallest_fount = 0; + for (reg178 = reg178_min[info->clock_speed_index]; + reg178 < reg178_max[info->clock_speed_index]; + reg178 += reg178_step[info->clock_speed_index]) + if (margin[reg178] >= threshold) { + usable_length += + reg178_step[info->clock_speed_index]; + info->training.reg178_largest = + reg178 - + 2 * reg178_step[info->clock_speed_index]; + + if (!smallest_fount) { + smallest_fount = 1; + info->training.reg178_smallest = + reg178 + + reg178_step[info-> + clock_speed_index]; + } + } + if (usable_length >= 0x21) + break; + } + + return sum / count; +} + +static int check_cached_sanity(struct raminfo *info) +{ + int lane; + int slot, rank; + int channel; + + if (!info->cached_training) + return 0; + + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + for (lane = 0; lane < 8 + info->use_ecc; lane++) { + u16 cached_value, estimation_value; + cached_value = + info->cached_training-> + lane_timings[1][channel][slot][rank] + [lane]; + if (cached_value >= 0x18 + && cached_value <= 0x1E7) { + estimation_value = + info->training. + lane_timings[1][channel] + [slot][rank][lane]; + if (estimation_value < + cached_value - 24) + return 0; + if (estimation_value > + cached_value + 24) + return 0; + } + } + return 1; +} + +static int try_cached_training(struct raminfo *info) +{ + u8 saved_243[2]; + u8 tm; + + int channel, slot, rank, lane; + int flip = 1; + int i, j; + + if (!check_cached_sanity(info)) + return 0; + + info->training.reg178_center = info->cached_training->reg178_center; + info->training.reg178_smallest = info->cached_training->reg178_smallest; + info->training.reg178_largest = info->cached_training->reg178_largest; + memcpy(&info->training.timing_bounds, + &info->cached_training->timing_bounds, + sizeof(info->training.timing_bounds)); + memcpy(&info->training.timing_offset, + &info->cached_training->timing_offset, + sizeof(info->training.timing_offset)); + + write_1d0(2, 0x142, 3, 1); + saved_243[0] = read_mchbar8(0x243); + saved_243[1] = read_mchbar8(0x643); + write_mchbar8(0x243, saved_243[0] | 2); + write_mchbar8(0x643, saved_243[1] | 2); + set_ecc(0); + pci_mm_write16(0, 0, 0, 0xc8, 3); + if (read_1d0(0x10b, 6) & 1) + set_10b(info, 0); + for (tm = 0; tm < 2; tm++) { + int totalrank; + + set_178(tm ? info->cached_training->reg178_largest : info-> + cached_training->reg178_smallest); + + totalrank = 0; + /* Check timing ranges. With i == 0 we check smallest one and with + i == 1 the largest bound. With j == 0 we check that on the bound + it still works whereas with j == 1 we check that just outside of + bound we fail. + */ + FOR_POPULATED_RANKS_BACKWARDS { + for (i = 0; i < 2; i++) { + for (lane = 0; lane < 8; lane++) { + write_500(info, channel, + info->cached_training-> + timing2_bounds[channel][slot] + [rank][lane][i], + get_timing_register_addr(lane, + 3, + slot, + rank), + 9, 1); + + if (!i) + write_500(info, channel, + info-> + cached_training-> + timing2_offset + [channel][slot][rank] + [lane], + get_timing_register_addr + (lane, 2, slot, rank), + 9, 1); + write_500(info, channel, + i ? info->cached_training-> + timing_bounds[tm][channel] + [slot][rank][lane]. + largest : info-> + cached_training-> + timing_bounds[tm][channel] + [slot][rank][lane].smallest, + get_timing_register_addr(lane, + 0, + slot, + rank), + 9, 1); + write_500(info, channel, + info->cached_training-> + timing_offset[channel][slot] + [rank][lane] + + (i ? info->cached_training-> + timing_bounds[tm][channel] + [slot][rank][lane]. + largest : info-> + cached_training-> + timing_bounds[tm][channel] + [slot][rank][lane]. + smallest) - 64, + get_timing_register_addr(lane, + 1, + slot, + rank), + 9, 1); + } + for (j = 0; j < 2; j++) { + u8 failmask; + u8 expected_failmask; + char reg1b3; + + reg1b3 = (j == 1) + 4; + reg1b3 = + j == i ? reg1b3 : (-reg1b3) & 0x3f; + write_1d0(reg1b3, 0x1bb, 6, 1); + write_1d0(reg1b3, 0x1b3, 6, 1); + write_1d0(reg1b3, 0x1a3, 6, 1); + + flip = !flip; + write_testing(info, totalrank, flip); + failmask = + check_testing(info, totalrank, + flip); + expected_failmask = + j == 0 ? 0x00 : 0xff; + if (failmask != expected_failmask) + goto fail; + } + } + totalrank++; + } + } + + set_178(info->cached_training->reg178_center); + if (info->use_ecc) + set_ecc(1); + write_training_data(info); + write_1d0(0, 322, 3, 1); + info->training = *info->cached_training; + + write_1d0(0, 0x1bb, 6, 1); + write_1d0(0, 0x1b3, 6, 1); + write_1d0(0, 0x1a3, 6, 1); + write_mchbar8(0x243, saved_243[0]); + write_mchbar8(0x643, saved_243[1]); + + return 1; + +fail: + FOR_POPULATED_RANKS { + write_500_timings_type(info, channel, slot, rank, 1); + write_500_timings_type(info, channel, slot, rank, 2); + write_500_timings_type(info, channel, slot, rank, 3); + } + + write_1d0(0, 0x1bb, 6, 1); + write_1d0(0, 0x1b3, 6, 1); + write_1d0(0, 0x1a3, 6, 1); + write_mchbar8(0x243, saved_243[0]); + write_mchbar8(0x643, saved_243[1]); + + return 0; +} + +static void do_ram_training(struct raminfo *info) +{ + u8 saved_243[2]; + int totalrank = 0; + u8 reg_178; + int niter; + + timing_bounds_t timings[64]; + int lane, rank, slot, channel; + u8 reg178_center; + + write_1d0(2, 0x142, 3, 1); + saved_243[0] = read_mchbar8(0x243); + saved_243[1] = read_mchbar8(0x643); + write_mchbar8(0x243, saved_243[0] | 2); + write_mchbar8(0x643, saved_243[1] | 2); + switch (info->clock_speed_index) { + case 0: + niter = 5; + break; + case 1: + niter = 10; + break; + default: + niter = 19; + break; + } + set_ecc(0); + + FOR_POPULATED_RANKS_BACKWARDS { + int i; + + write_500_timings_type(info, channel, slot, rank, 0); + + write_testing(info, totalrank, 0); + for (i = 0; i < niter; i++) { + write_testing_type2(info, totalrank, 2, i, 0); + write_testing_type2(info, totalrank, 3, i, 1); + } + pci_mm_write8(0, 0, 0, 0xc0, 0x01); + totalrank++; + } + + if (reg178_min[info->clock_speed_index] < + reg178_max[info->clock_speed_index]) + memset(timings[reg178_min[info->clock_speed_index]], 0, + sizeof(timings[0]) * + (reg178_max[info->clock_speed_index] - + reg178_min[info->clock_speed_index])); + for (reg_178 = reg178_min[info->clock_speed_index]; + reg_178 < reg178_max[info->clock_speed_index]; + reg_178 += reg178_step[info->clock_speed_index]) { + totalrank = 0; + set_178(reg_178); + for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) { + memset(&timings[reg_178][channel][slot] + [rank][0].smallest, 0, 16); + if (info-> + populated_ranks[channel][slot] + [rank]) { + train_ram_at_178(info, channel, + slot, rank, + totalrank, + reg_178, 1, + niter, + timings); + totalrank++; + } + } + } + + reg178_center = choose_reg178(info, timings); + + FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { + info->training.timing_bounds[0][channel][slot][rank][lane]. + smallest = + timings[info->training. + reg178_smallest][channel][slot][rank][lane]. + smallest; + info->training.timing_bounds[0][channel][slot][rank][lane]. + largest = + timings[info->training. + reg178_smallest][channel][slot][rank][lane].largest; + info->training.timing_bounds[1][channel][slot][rank][lane]. + smallest = + timings[info->training. + reg178_largest][channel][slot][rank][lane].smallest; + info->training.timing_bounds[1][channel][slot][rank][lane]. + largest = + timings[info->training. + reg178_largest][channel][slot][rank][lane].largest; + info->training.timing_offset[channel][slot][rank][lane] = + info->training.lane_timings[1][channel][slot][rank][lane] + - + info->training.lane_timings[0][channel][slot][rank][lane] + + 64; + } + + if (info->silicon_revision == 1 + && (info-> + populated_ranks_mask[1] ^ (info-> + populated_ranks_mask[1] >> 2)) & 1) { + int ranks_after_channel1; + + totalrank = 0; + for (reg_178 = reg178_center - 18; + reg_178 <= reg178_center + 18; reg_178 += 18) { + totalrank = 0; + set_178(reg_178); + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) { + if (info-> + populated_ranks[1][slot][rank]) { + train_ram_at_178(info, 1, slot, + rank, + totalrank, + reg_178, 0, + niter, + timings); + totalrank++; + } + } + } + ranks_after_channel1 = totalrank; + + for (reg_178 = reg178_center - 12; + reg_178 <= reg178_center + 12; reg_178 += 12) { + totalrank = ranks_after_channel1; + set_178(reg_178); + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + if (info-> + populated_ranks[0][slot][rank]) { + train_ram_at_178(info, 0, slot, + rank, + totalrank, + reg_178, 0, + niter, + timings); + totalrank++; + } + + } + } else { + for (reg_178 = reg178_center - 12; + reg_178 <= reg178_center + 12; reg_178 += 12) { + totalrank = 0; + set_178(reg_178); + FOR_POPULATED_RANKS_BACKWARDS { + train_ram_at_178(info, channel, slot, rank, + totalrank, reg_178, 0, niter, + timings); + totalrank++; + } + } + } + + set_178(reg178_center); + FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) { + u16 tm0; + + tm0 = + choose_training(info, channel, slot, rank, lane, timings, + reg178_center); + write_500(info, channel, tm0, + get_timing_register_addr(lane, 0, slot, rank), 9, 1); + write_500(info, channel, + tm0 + + info->training. + lane_timings[1][channel][slot][rank][lane] - + info->training. + lane_timings[0][channel][slot][rank][lane], + get_timing_register_addr(lane, 1, slot, rank), 9, 1); + } + + totalrank = 0; + FOR_POPULATED_RANKS_BACKWARDS { + try_timing_offsets(info, channel, slot, rank, totalrank); + totalrank++; + } + write_mchbar8(0x243, saved_243[0]); + write_mchbar8(0x643, saved_243[1]); + write_1d0(0, 0x142, 3, 1); + info->training.reg178_center = reg178_center; +} + +static void ram_training(struct raminfo *info) +{ + u16 saved_fc4; + + saved_fc4 = read_mchbar16(0xfc4); + write_mchbar16(0xfc4, 0xffff); + + if (info->revision >= 8) + read_4090(info); + + if (!try_cached_training(info)) + do_ram_training(info); + if ((info->silicon_revision == 2 || info->silicon_revision == 3) + && info->clock_speed_index < 2) + set_10b(info, 1); + write_mchbar16(0xfc4, saved_fc4); +} + +static unsigned gcd(unsigned a, unsigned b) +{ + unsigned t; + if (a > b) { + t = a; + a = b; + b = t; + } + /* invariant a < b. */ + while (a) { + t = b % a; + b = a; + a = t; + } + return b; +} + +static inline int div_roundup(int a, int b) +{ + return (a + b - 1) / b; +} + +static unsigned lcm(unsigned a, unsigned b) +{ + return (a * b) / gcd(a, b); +} + +struct stru1 { + u8 freqs_reversed; + u8 freq_diff_reduced; + u8 freq_min_reduced; + u8 divisor_f4_to_fmax; + u8 divisor_f3_to_fmax; + u8 freq4_to_max_remainder; + u8 freq3_to_2_remainder; + u8 freq3_to_2_remaindera; + u8 freq4_to_2_remainder; + int divisor_f3_to_f1, divisor_f4_to_f2; + int common_time_unit_ps; + int freq_max_reduced; +}; + +static void +compute_frequence_ratios(struct raminfo *info, u16 freq1, u16 freq2, + int num_cycles_2, int num_cycles_1, int round_it, + int add_freqs, struct stru1 *result) +{ + int g; + int common_time_unit_ps; + int freq1_reduced, freq2_reduced; + int freq_min_reduced; + int freq_max_reduced; + int freq3, freq4; + + g = gcd(freq1, freq2); + freq1_reduced = freq1 / g; + freq2_reduced = freq2 / g; + freq_min_reduced = min(freq1_reduced, freq2_reduced); + freq_max_reduced = max(freq1_reduced, freq2_reduced); + + common_time_unit_ps = div_roundup(900000, lcm(freq1, freq2)); + freq3 = div_roundup(num_cycles_2, common_time_unit_ps) - 1; + freq4 = div_roundup(num_cycles_1, common_time_unit_ps) - 1; + if (add_freqs) { + freq3 += freq2_reduced; + freq4 += freq1_reduced; + } + + if (round_it) { + result->freq3_to_2_remainder = 0; + result->freq3_to_2_remaindera = 0; + result->freq4_to_max_remainder = 0; + result->divisor_f4_to_f2 = 0; + result->divisor_f3_to_f1 = 0; + } else { + if (freq2_reduced < freq1_reduced) { + result->freq3_to_2_remainder = + result->freq3_to_2_remaindera = + freq3 % freq1_reduced - freq1_reduced + 1; + result->freq4_to_max_remainder = + -(freq4 % freq1_reduced); + result->divisor_f3_to_f1 = freq3 / freq1_reduced; + result->divisor_f4_to_f2 = + (freq4 - + (freq1_reduced - freq2_reduced)) / freq2_reduced; + result->freq4_to_2_remainder = + -(char)((freq1_reduced - freq2_reduced) + + ((u8) freq4 - + (freq1_reduced - + freq2_reduced)) % (u8) freq2_reduced); + } else { + if (freq2_reduced > freq1_reduced) { + result->freq4_to_max_remainder = + (freq4 % freq2_reduced) - freq2_reduced + 1; + result->freq4_to_2_remainder = + freq4 % freq_max_reduced - + freq_max_reduced + 1; + } else { + result->freq4_to_max_remainder = + -(freq4 % freq2_reduced); + result->freq4_to_2_remainder = + -(char)(freq4 % freq_max_reduced); + } + result->divisor_f4_to_f2 = freq4 / freq2_reduced; + result->divisor_f3_to_f1 = + (freq3 - + (freq2_reduced - freq1_reduced)) / freq1_reduced; + result->freq3_to_2_remainder = -(freq3 % freq2_reduced); + result->freq3_to_2_remaindera = + -(char)((freq_max_reduced - freq_min_reduced) + + (freq3 - + (freq_max_reduced - + freq_min_reduced)) % freq1_reduced); + } + } + result->divisor_f3_to_fmax = freq3 / freq_max_reduced; + result->divisor_f4_to_fmax = freq4 / freq_max_reduced; + if (round_it) { + if (freq2_reduced > freq1_reduced) { + if (freq3 % freq_max_reduced) + result->divisor_f3_to_fmax++; + } + if (freq2_reduced < freq1_reduced) { + if (freq4 % freq_max_reduced) + result->divisor_f4_to_fmax++; + } + } + result->freqs_reversed = (freq2_reduced < freq1_reduced); + result->freq_diff_reduced = freq_max_reduced - freq_min_reduced; + result->freq_min_reduced = freq_min_reduced; + result->common_time_unit_ps = common_time_unit_ps; + result->freq_max_reduced = freq_max_reduced; +} + +static void +set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, + int num_cycles_2, int num_cycles_1, int num_cycles_3, + int num_cycles_4, int reverse) +{ + struct stru1 vv; + char multiplier; + + compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1, + 0, 1, &vv); + + multiplier = + div_roundup(max + (div_roundup(num_cycles_2, vv.common_time_unit_ps) + + div_roundup(num_cycles_3, vv.common_time_unit_ps), + div_roundup(num_cycles_1, + vv.common_time_unit_ps) + + div_roundup(num_cycles_4, vv.common_time_unit_ps)) + + vv.freq_min_reduced - 1, vv.freq_max_reduced) - 1; + + u32 y = + (u8) ((vv.freq_max_reduced - vv.freq_min_reduced) + + vv.freq_max_reduced * multiplier) + | (vv. + freqs_reversed << 8) | ((u8) (vv.freq_min_reduced * + multiplier) << 16) | ((u8) (vv. + freq_min_reduced + * + multiplier) + << 24); + u32 x = + vv.freq3_to_2_remaindera | (vv.freq4_to_2_remainder << 8) | (vv. + divisor_f3_to_f1 + << 16) + | (vv.divisor_f4_to_f2 << 20) | (vv.freq_min_reduced << 24); + if (reverse) { + write_mchbar32(reg, y); + write_mchbar32(reg + 4, x); + } else { + write_mchbar32(reg + 4, y); + write_mchbar32(reg, x); + } +} + +static void +set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, + int num_cycles_1, int num_cycles_2, int num_cycles_3, + int num_cycles_4) +{ + struct stru1 ratios1; + struct stru1 ratios2; + + compute_frequence_ratios(info, freq1, freq2, num_cycles_1, num_cycles_2, + 0, 1, &ratios2); + compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, + 0, 1, &ratios1); + write_mchbar32(reg, + ratios1.freq4_to_max_remainder | (ratios2. + freq4_to_max_remainder + << 8) + | (ratios1.divisor_f4_to_fmax << 16) | (ratios2. + divisor_f4_to_fmax + << 20)); +} + +static void +set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2, + int num_cycles_2, int num_cycles_1, int round_it, int add_freqs) +{ + struct stru1 ratios; + + compute_frequence_ratios(info, freq1, freq2, num_cycles_2, num_cycles_1, + round_it, add_freqs, &ratios); + switch (mode) { + case 0: + write_mchbar32(reg + 4, + ratios.freq_diff_reduced | (ratios. + freqs_reversed << + 8)); + write_mchbar32(reg, + ratios.freq3_to_2_remainder | (ratios. + freq4_to_max_remainder + << 8) + | (ratios.divisor_f3_to_fmax << 16) | (ratios. + divisor_f4_to_fmax + << 20) | + (ratios.freq_min_reduced << 24)); + break; + + case 1: + write_mchbar32(reg, + ratios.freq3_to_2_remainder | (ratios. + divisor_f3_to_fmax + << 16)); + break; + + case 2: + write_mchbar32(reg, + ratios.freq3_to_2_remainder | (ratios. + freq4_to_max_remainder + << 8) | (ratios. + divisor_f3_to_fmax + << 16) | + (ratios.divisor_f4_to_fmax << 20)); + break; + + case 4: + write_mchbar32(reg, (ratios.divisor_f3_to_fmax << 4) + | (ratios.divisor_f4_to_fmax << 8) | (ratios. + freqs_reversed + << 12) | + (ratios.freq_min_reduced << 16) | (ratios. + freq_diff_reduced + << 24)); + break; + } +} + +static void set_2dxx_series(struct raminfo *info) +{ + set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005, + 0, 1); + set_2dx8_reg(info, 0x2d08, 0, 0x78, 0x78, 3273, 5033, 1, 1); + set_2dx8_reg(info, 0x2d10, 0, 0x78, info->fsb_frequency, 1475, 1131, 0, + 1); + set_2dx8_reg(info, 0x2d18, 0, 2 * info->fsb_frequency, + frequency_11(info), 1231, 1524, 0, 1); + set_2dx8_reg(info, 0x2d20, 0, 2 * info->fsb_frequency, + frequency_11(info) / 2, 1278, 2008, 0, 1); + set_2dx8_reg(info, 0x2d28, 0, info->fsb_frequency, frequency_11(info), + 1167, 1539, 0, 1); + set_2dx8_reg(info, 0x2d30, 0, info->fsb_frequency, + frequency_11(info) / 2, 1403, 1318, 0, 1); + set_2dx8_reg(info, 0x2d38, 0, info->fsb_frequency, 0x78, 3460, 5363, 1, + 1); + set_2dx8_reg(info, 0x2d40, 0, info->fsb_frequency, 0x3c, 2792, 5178, 1, + 1); + set_2dx8_reg(info, 0x2d48, 0, 2 * info->fsb_frequency, 0x78, 2738, 4610, + 1, 1); + set_2dx8_reg(info, 0x2d50, 0, info->fsb_frequency, 0x78, 2819, 5932, 1, + 1); + set_2dx8_reg(info, 0x6d4, 1, info->fsb_frequency, + frequency_11(info) / 2, 4000, 0, 0, 0); + set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency, + frequency_11(info) / 2, 4000, 4000, 0, 0); + + set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[0], 0, info->delay54_ps[0]); + set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency, + frequency_11(info), 2500, 0, 0, 0); + set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, + frequency_11(info) / 2, 3500, 0, 0, 0); + set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[1], 0, info->delay54_ps[1]); + set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0); + set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455, + 470, 0); + set_2d5x_reg(info, 0x2d68, 0x195, 0x3c, 2707, 5632, 3277, 2207, 0); + set_2d5x_reg(info, 0x2d70, 0x195, frequency_11(info) / 2, 1276, 758, + 454, 459, 0); + set_2d5x_reg(info, 0x2d78, 0x195, 0x78, 1021, 799, 510, 513, 0); + set_2d5x_reg(info, 0x2d80, info->fsb_frequency, 0xe1, 0, 2862, 2579, + 2588, 0); + set_2d5x_reg(info, 0x2d88, info->fsb_frequency, 0xe1, 0, 2690, 2405, + 2405, 0); + set_2d5x_reg(info, 0x2da0, 0x78, 0xe1, 0, 2560, 2264, 2251, 0); + set_2d5x_reg(info, 0x2da8, 0x195, frequency_11(info), 1060, 775, 484, + 480, 0); + set_2d5x_reg(info, 0x2db0, 0x195, 0x78, 4183, 6023, 2217, 2048, 0); + write_mchbar32(0x2dbc, ((frequency_11(info) / 2) - 1) | 0xe00000); + write_mchbar32(0x2db8, ((info->fsb_frequency - 1) << 16) | 0x77); +} + +static u16 get_max_timing(struct raminfo *info, int channel) +{ + int slot, rank, lane; + u16 ret = 0; + + if ((read_mchbar8(0x2ca8) >> 2) < 1) + return 384; + + if (info->revision < 8) + return 256; + + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + if (info->populated_ranks[channel][slot][rank]) + for (lane = 0; lane < 8 + info->use_ecc; lane++) + ret = max(ret, read_500(info, channel, + get_timing_register_addr + (lane, 0, slot, + rank), 9)); + return ret; +} + +static void set_274265(struct raminfo *info) +{ + int delay_a_ps, delay_b_ps, delay_c_ps, delay_d_ps; + int delay_e_ps, delay_e_cycles, delay_f_cycles; + int delay_e_over_cycle_ps; + int cycletime_ps; + int channel; + + delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info); + info->reg2ca9_bit0 = 0; + for (channel = 0; channel < NUM_CHANNELS; channel++) { + cycletime_ps = + 900000 / lcm(2 * info->fsb_frequency, frequency_11(info)); + delay_d_ps = + (halfcycle_ps(info) * get_max_timing(info, channel) >> 6) + - info->some_delay_3_ps_rounded + 200; + if (! + ((info->silicon_revision == 0 + || info->silicon_revision == 1) + && (info->revision >= 8))) + delay_d_ps += halfcycle_ps(info) * 2; + delay_d_ps += + halfcycle_ps(info) * (!info->revision_flag_1 + + info->some_delay_2_halfcycles_ceil + + 2 * info->some_delay_1_cycle_floor + + info->clock_speed_index + + 2 * info->cas_latency - 7 + 11); + delay_d_ps += info->revision >= 8 ? 2758 : 4428; + + write_mchbar32(0x140, + (read_mchbar32(0x140) & 0xfaffffff) | 0x2000000); + write_mchbar32(0x138, + (read_mchbar32(0x138) & 0xfaffffff) | 0x2000000); + if ((read_mchbar8(0x144) & 0x1f) > 0x13) + delay_d_ps += 650; + delay_c_ps = delay_d_ps + 1800; + if (delay_c_ps <= delay_a_ps) + delay_e_ps = 0; + else + delay_e_ps = + cycletime_ps * div_roundup(delay_c_ps - delay_a_ps, + cycletime_ps); + + delay_e_over_cycle_ps = delay_e_ps % (2 * halfcycle_ps(info)); + delay_e_cycles = delay_e_ps / (2 * halfcycle_ps(info)); + delay_f_cycles = + div_roundup(2500 - delay_e_over_cycle_ps, + 2 * halfcycle_ps(info)); + if (delay_f_cycles > delay_e_cycles) { + info->delay46_ps[channel] = delay_e_ps; + delay_e_cycles = 0; + } else { + info->delay46_ps[channel] = + delay_e_over_cycle_ps + + 2 * halfcycle_ps(info) * delay_f_cycles; + delay_e_cycles -= delay_f_cycles; + } + + if (info->delay46_ps[channel] < 2500) { + info->delay46_ps[channel] = 2500; + info->reg2ca9_bit0 = 1; + } + delay_b_ps = halfcycle_ps(info) + delay_c_ps; + if (delay_b_ps <= delay_a_ps) + delay_b_ps = 0; + else + delay_b_ps -= delay_a_ps; + info->delay54_ps[channel] = + cycletime_ps * div_roundup(delay_b_ps, + cycletime_ps) - + 2 * halfcycle_ps(info) * delay_e_cycles; + if (info->delay54_ps[channel] < 2500) + info->delay54_ps[channel] = 2500; + info->reg274265[channel][0] = delay_e_cycles; + if (delay_d_ps + 7 * halfcycle_ps(info) <= + 24 * halfcycle_ps(info)) + info->reg274265[channel][1] = 0; + else + info->reg274265[channel][1] = + div_roundup(delay_d_ps + 7 * halfcycle_ps(info), + 4 * halfcycle_ps(info)) - 6; + write_mchbar32((channel << 10) + 0x274, + info->reg274265[channel][1] | (info-> + reg274265[channel] + [0] << 16)); + info->reg274265[channel][2] = + div_roundup(delay_c_ps + 3 * fsbcycle_ps(info), + 4 * halfcycle_ps(info)) + 1; + write_mchbar16((channel << 10) + 0x265, + info->reg274265[channel][2] << 8); + } + if (info->reg2ca9_bit0) + write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); + else + write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); +} + +static void restore_274265(struct raminfo *info) +{ + int channel; + + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_mchbar32((channel << 10) + 0x274, + (info->reg274265[channel][0] << 16) | info-> + reg274265[channel][1]); + write_mchbar16((channel << 10) + 0x265, + info->reg274265[channel][2] << 8); + } + if (info->reg2ca9_bit0) + write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); + else + write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); +} + +#if REAL +static void dmi_setup(void) +{ + gav(read8(DEFAULT_DMIBAR | 0x254)); + write8(DEFAULT_DMIBAR | 0x254, 0x1); + write16(DEFAULT_DMIBAR | 0x1b8, 0x18f2); + read_mchbar16(0x48); + write_mchbar16(0x48, 0x2); + + write32(DEFAULT_DMIBAR | 0xd68, read32(DEFAULT_DMIBAR | 0xd68) | 0x08000000); + + outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000, + DEFAULT_GPIOBASE | 0x38); + gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e +} +#endif + +static void +set_fsb_frequency (void) +{ + u8 block[5]; + u16 fsbfreq = 62879; + smbus_block_read(0x69, 0, 5, block); + block[0] = fsbfreq; + block[1] = fsbfreq >> 8; + + smbus_block_write(0x69, 0, 5, block); +} + +#if REAL +void raminit(const int s3resume) +#else +void raminit(int s3resume) +#endif +{ + unsigned channel, slot, lane, rank; + int i; + struct raminfo info; +#if CONFIG_COLLECT_TIMESTAMPS + extern tsc_t before_spd, after_spd, before_training, after_training; +#endif + +#if !REAL + pre_raminit1(); +#endif + + if (s3resume) { + read_mchbar32(0x1e8); + write_mchbar32(0x1e8, 0x6); + read_mchbar32(0x1e8); + write_mchbar32(0x1e8, 0x4); + } + +#if !REAL + pre_raminit_2(); +#endif + u8 x2ca8; + + gav(x2ca8 = read_mchbar8(0x2ca8)); + if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + write_mchbar8(0x2ca8, 0); + outb(0xe, 0xcf9); +#if REAL + while (1) { + asm volatile ("hlt"); + } +#else + printf("CP5\n"); + exit(0); +#endif + } +#if !REAL + if (!s3resume) { + pre_raminit_3(x2ca8); + } +#endif + +#if !REAL + pre_raminit_4a(); +#endif + + dmi_setup(); + + write_mchbar16(0x1170, 0xa880); + write_mchbar8(0x11c1, 0x1); + write_mchbar16(0x1170, 0xb880); + read_mchbar8(0x1210); + write_mchbar8(0x1210, 0x84); + pci_mm_read8(NORTHBRIDGE, D0F0_GGC); // = 0x52 + pci_mm_write8(NORTHBRIDGE, D0F0_GGC, 0x2); + pci_mm_read8(NORTHBRIDGE, D0F0_GGC); // = 0x2 + pci_mm_write8(NORTHBRIDGE, D0F0_GGC, 0x52); + pci_mm_read16(NORTHBRIDGE, D0F0_GGC); // = 0xb52 + + pci_mm_write16(NORTHBRIDGE, D0F0_GGC, 0xb52); + + u16 deven; + deven = pci_mm_read16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3 + + if (deven & 8) { + write_mchbar8(0x2c30, 0x20); + pci_mm_read8(0, 0x0, 0x0, 0x8); // = 0x18 + write_mchbar16(0x2c30, read_mchbar16(0x2c30) | 0x200); + write_mchbar16(0x2c32, 0x434); + read_mchbar32(0x2c44); + write_mchbar32(0x2c44, 0x1053687); + pci_mm_read8(0, 0x2, 0x0, 0x62); // = 0x2 + pci_mm_write8(0, 0x2, 0x0, 0x62, 0x2); + read8(DEFAULT_RCBA | 0x2318); + write8(DEFAULT_RCBA | 0x2318, 0x47); + read8(DEFAULT_RCBA | 0x2320); + write8(DEFAULT_RCBA | 0x2320, 0xfc); + } + + read_mchbar32(0x30); + write_mchbar32(0x30, 0x40); + + pci_mm_read8(SOUTHBRIDGE, 0x8); // = 0x6 + pci_mm_read16(NORTHBRIDGE, D0F0_GGC); // = 0xb52 + pci_mm_write16(NORTHBRIDGE, D0F0_GGC, 0xb50); + gav(read32(DEFAULT_RCBA | 0x3428)); + write32(DEFAULT_RCBA | 0x3428, 0x1d); + +#if !REAL + pre_raminit_5(s3resume); +#else + set_fsb_frequency(); +#endif + + memset(&info, 0x5a, sizeof(info)); + + info.last_500_command[0] = 0; + info.last_500_command[1] = 0; + + info.fsb_frequency = 135 * 2; + info.board_lane_delay[0] = 0x14; + info.board_lane_delay[1] = 0x07; + info.board_lane_delay[2] = 0x07; + info.board_lane_delay[3] = 0x08; + info.board_lane_delay[4] = 0x56; + info.board_lane_delay[5] = 0x04; + info.board_lane_delay[6] = 0x04; + info.board_lane_delay[7] = 0x05; + info.board_lane_delay[8] = 0x10; + + info.training.reg_178 = 0; + info.training.reg_10b = 0; + + info.heci_bar = 0; + info.memory_reserved_for_heci_mb = 0; + +#if CONFIG_COLLECT_TIMESTAMPS + before_spd = rdtsc(); +#endif + + if (!s3resume || REAL) { + pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80 + + collect_system_info(&info); + +#if REAL + /* Enable SMBUS. */ + enable_smbus(); +#endif + + memset(&info.populated_ranks, 0, sizeof(info.populated_ranks)); + + info.use_ecc = 1; + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_CHANNELS; slot++) { + int v; + int try; + int addr; + const u8 useful_addresses[] = { + DEVICE_TYPE, + MODULE_TYPE, + DENSITY, + RANKS_AND_DQ, + MEMORY_BUS_WIDTH, + TIMEBASE_DIVIDEND, + TIMEBASE_DIVISOR, + CYCLETIME, + CAS_LATENCIES_LSB, + CAS_LATENCIES_MSB, + CAS_LATENCY_TIME, + 0x11, 0x12, 0x13, 0x14, 0x15, + 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, + 0x1c, 0x1d, + THERMAL_AND_REFRESH, + 0x20, + REFERENCE_RAW_CARD_USED, + RANK1_ADDRESS_MAPPING, + 0x75, 0x76, 0x77, 0x78, + 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, + 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84, + 0x85, 0x86, 0x87, 0x88, + 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, + 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, + 0x95 + }; + if (slot) + continue; + for (try = 0; try < 5; try++) { + v = smbus_read_byte(0x50 + channel, + DEVICE_TYPE); + if (v >= 0) + break; + } + if (v < 0) + continue; + for (addr = 0; + addr < + sizeof(useful_addresses) / + sizeof(useful_addresses[0]); addr++) + gav(info. + spd[channel][0][useful_addresses + [addr]] = + smbus_read_byte(0x50 + channel, + useful_addresses + [addr])); + if (info.spd[channel][0][DEVICE_TYPE] != 11) + die("Only DDR3 is supported"); + + v = info.spd[channel][0][RANKS_AND_DQ]; + info.populated_ranks[channel][0][0] = 1; + info.populated_ranks[channel][0][1] = + ((v >> 3) & 7); + if (((v >> 3) & 7) > 1) + die("At most 2 ranks are supported"); + if ((v & 7) == 0 || (v & 7) > 2) + die("Only x8 and x16 modules are supported"); + if ((info. + spd[channel][slot][MODULE_TYPE] & 0xF) != 2 + && (info. + spd[channel][slot][MODULE_TYPE] & 0xF) + != 3) + die("Registered memory is not supported"); + info.is_x16_module[channel][0] = (v & 7) - 1; + info.density[channel][slot] = + info.spd[channel][slot][DENSITY] & 0xF; + if (! + (info. + spd[channel][slot][MEMORY_BUS_WIDTH] & + 0x18)) + info.use_ecc = 0; + } + + gav(0x55); + + for (channel = 0; channel < NUM_CHANNELS; channel++) { + int v = 0; + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + v |= info. + populated_ranks[channel][slot][rank] + << (2 * slot + rank); + info.populated_ranks_mask[channel] = v; + } + + gav(0x55); + + gav(pci_mm_read32(NORTHBRIDGE, D0F0_CAPID0 + 4)); + } else { + memset(info.populated_ranks, 0, sizeof(info.populated_ranks)); +#if 0 + info.populated_ranks[0][0][0] = 1; + info.populated_ranks[0][0][1] = 1; + info.populated_ranks_mask[0] = 3; + info.populated_ranks_mask[1] = 0; + info.use_ecc = 0; + info.max_slots_used_in_channel = 1; + + info.spd[0][0][0x02] = 0x0b; + info.spd[0][0][0x03] = 0x03; + info.spd[0][0][0x04] = 0x03; + info.spd[0][0][0x07] = 0x09; + info.spd[0][0][0x08] = 0x03; + info.spd[0][0][0x0a] = 0x01; + info.spd[0][0][0x0b] = 0x08; + info.spd[0][0][0x0c] = 0x0c; + info.spd[0][0][0x0e] = 0x3e; + info.spd[0][0][0x0f] = 0x00; + info.spd[0][0][0x10] = 0x69; + info.spd[0][0][0x11] = 0x78; + info.spd[0][0][0x12] = 0x69; + info.spd[0][0][0x13] = 0x30; + info.spd[0][0][0x14] = 0x69; + info.spd[0][0][0x15] = 0x11; + info.spd[0][0][0x16] = 0x20; + info.spd[0][0][0x17] = 0x89; + info.spd[0][0][0x18] = 0x00; + info.spd[0][0][0x19] = 0x05; + info.spd[0][0][0x1a] = 0x3c; + info.spd[0][0][0x1b] = 0x3c; + info.spd[0][0][0x1c] = 0x00; + info.spd[0][0][0x1d] = 0xf0; + info.spd[0][0][0x1f] = 0x05; + info.spd[0][0][0x20] = 0x00; + info.spd[0][0][0x3e] = 0x05; + info.spd[0][0][0x3f] = 0x00; + info.spd[0][0][0x75] = 0x80; + info.spd[0][0][0x76] = 0xad; + info.spd[0][0][0x77] = 0x01; + info.spd[0][0][0x78] = 0x10; + info.spd[0][0][0x79] = 0x52; + info.spd[0][0][0x7a] = 0x26; + info.spd[0][0][0x7b] = 0x50; + info.spd[0][0][0x7c] = 0xf4; + info.spd[0][0][0x7d] = 0x7d; + info.spd[0][0][0x7e] = 0xb0; + info.spd[0][0][0x7f] = 0xcf; + info.spd[0][0][0x80] = 0x48; + info.spd[0][0][0x81] = 0x4d; + info.spd[0][0][0x82] = 0x54; + info.spd[0][0][0x83] = 0x33; + info.spd[0][0][0x84] = 0x35; + info.spd[0][0][0x85] = 0x31; + info.spd[0][0][0x86] = 0x53; + info.spd[0][0][0x87] = 0x36; + info.spd[0][0][0x88] = 0x42; + info.spd[0][0][0x89] = 0x46; + info.spd[0][0][0x8a] = 0x52; + info.spd[0][0][0x8b] = 0x38; + info.spd[0][0][0x8c] = 0x43; + info.spd[0][0][0x8d] = 0x2d; + info.spd[0][0][0x8e] = 0x48; + info.spd[0][0][0x8f] = 0x39; + info.spd[0][0][0x90] = 0x20; + info.spd[0][0][0x91] = 0x20; + info.spd[0][0][0x92] = 0x4e; + info.spd[0][0][0x93] = 0x30; + info.spd[0][0][0x94] = 0x80; + info.spd[0][0][0x95] = 0xad; +#else + info.populated_ranks[0][0][0] = 1; + info.populated_ranks[0][0][1] = 1; + info.populated_ranks[1][0][0] = 1; + info.populated_ranks[1][0][1] = 1; + info.populated_ranks_mask[0] = 3; + info.populated_ranks_mask[1] = 3; + info.use_ecc = 0; + info.max_slots_used_in_channel = 1; + + info.spd[0][0][0x02] = 0x0b; + info.spd[0][0][0x03] = 0x03; + info.spd[0][0][0x04] = 0x03; + info.spd[0][0][0x07] = 0x09; + info.spd[0][0][0x08] = 0x03; + info.spd[0][0][0x0a] = 0x01; + info.spd[0][0][0x0b] = 0x08; + info.spd[0][0][0x0c] = 0x0c; + info.spd[0][0][0x0e] = 0x3e; + info.spd[0][0][0x0f] = 0x00; + info.spd[0][0][0x10] = 0x69; + info.spd[0][0][0x11] = 0x78; + info.spd[0][0][0x12] = 0x69; + info.spd[0][0][0x13] = 0x30; + info.spd[0][0][0x14] = 0x69; + info.spd[0][0][0x15] = 0x11; + info.spd[0][0][0x16] = 0x20; + info.spd[0][0][0x17] = 0x89; + info.spd[0][0][0x18] = 0x00; + info.spd[0][0][0x19] = 0x05; + info.spd[0][0][0x1a] = 0x3c; + info.spd[0][0][0x1b] = 0x3c; + info.spd[0][0][0x1c] = 0x00; + info.spd[0][0][0x1d] = 0xf0; + info.spd[0][0][0x1f] = 0x05; + info.spd[0][0][0x20] = 0x00; + info.spd[0][0][0x3e] = 0x05; + info.spd[0][0][0x3f] = 0x00; + info.spd[0][0][0x75] = 0x80; + info.spd[0][0][0x76] = 0xad; + info.spd[0][0][0x77] = 0x01; + info.spd[0][0][0x78] = 0x10; + info.spd[0][0][0x79] = 0x52; + info.spd[0][0][0x7a] = 0x26; + info.spd[0][0][0x7b] = 0x50; + info.spd[0][0][0x7c] = 0xf4; + info.spd[0][0][0x7d] = 0x7d; + info.spd[0][0][0x7e] = 0xb0; + info.spd[0][0][0x7f] = 0xcf; + info.spd[0][0][0x80] = 0x48; + info.spd[0][0][0x81] = 0x4d; + info.spd[0][0][0x82] = 0x54; + info.spd[0][0][0x83] = 0x33; + info.spd[0][0][0x84] = 0x35; + info.spd[0][0][0x85] = 0x31; + info.spd[0][0][0x86] = 0x53; + info.spd[0][0][0x87] = 0x36; + info.spd[0][0][0x88] = 0x42; + info.spd[0][0][0x89] = 0x46; + info.spd[0][0][0x8a] = 0x52; + info.spd[0][0][0x8b] = 0x38; + info.spd[0][0][0x8c] = 0x43; + info.spd[0][0][0x8d] = 0x2d; + info.spd[0][0][0x8e] = 0x48; + info.spd[0][0][0x8f] = 0x39; + info.spd[0][0][0x90] = 0x20; + info.spd[0][0][0x91] = 0x20; + info.spd[0][0][0x92] = 0x4e; + info.spd[0][0][0x93] = 0x30; + info.spd[0][0][0x94] = 0x80; + info.spd[0][0][0x95] = 0xad; + + info.spd[1][0][0x02] = 0x0b; + info.spd[1][0][0x03] = 0x03; + info.spd[1][0][0x04] = 0x03; + info.spd[1][0][0x07] = 0x09; + info.spd[1][0][0x08] = 0x03; + info.spd[1][0][0x0a] = 0x01; + info.spd[1][0][0x0b] = 0x08; + info.spd[1][0][0x0c] = 0x0c; + info.spd[1][0][0x0e] = 0x3e; + info.spd[1][0][0x0f] = 0x00; + info.spd[1][0][0x10] = 0x69; + info.spd[1][0][0x11] = 0x78; + info.spd[1][0][0x12] = 0x69; + info.spd[1][0][0x13] = 0x30; + info.spd[1][0][0x14] = 0x69; + info.spd[1][0][0x15] = 0x11; + info.spd[1][0][0x16] = 0x20; + info.spd[1][0][0x17] = 0x89; + info.spd[1][0][0x18] = 0x00; + info.spd[1][0][0x19] = 0x05; + info.spd[1][0][0x1a] = 0x3c; + info.spd[1][0][0x1b] = 0x3c; + info.spd[1][0][0x1c] = 0x00; + info.spd[1][0][0x1d] = 0xf0; + info.spd[1][0][0x1f] = 0x05; + info.spd[1][0][0x20] = 0x00; + info.spd[1][0][0x3e] = 0x05; + info.spd[1][0][0x3f] = 0x00; + info.spd[1][0][0x75] = 0x80; + info.spd[1][0][0x76] = 0xad; + info.spd[1][0][0x77] = 0x01; + info.spd[1][0][0x78] = 0x10; + info.spd[1][0][0x79] = 0x52; + info.spd[1][0][0x7a] = 0x26; + info.spd[1][0][0x7b] = 0x50; + info.spd[1][0][0x7c] = 0xf4; + info.spd[1][0][0x7d] = 0x7d; + info.spd[1][0][0x7e] = 0xb0; + info.spd[1][0][0x7f] = 0xcf; + info.spd[1][0][0x80] = 0x48; + info.spd[1][0][0x81] = 0x4d; + info.spd[1][0][0x82] = 0x54; + info.spd[1][0][0x83] = 0x33; + info.spd[1][0][0x84] = 0x35; + info.spd[1][0][0x85] = 0x31; + info.spd[1][0][0x86] = 0x53; + info.spd[1][0][0x87] = 0x36; + info.spd[1][0][0x88] = 0x42; + info.spd[1][0][0x89] = 0x46; + info.spd[1][0][0x8a] = 0x52; + info.spd[1][0][0x8b] = 0x38; + info.spd[1][0][0x8c] = 0x43; + info.spd[1][0][0x8d] = 0x2d; + info.spd[1][0][0x8e] = 0x48; + info.spd[1][0][0x8f] = 0x39; + info.spd[1][0][0x90] = 0x20; + info.spd[1][0][0x91] = 0x20; + info.spd[1][0][0x92] = 0x4e; + info.spd[1][0][0x93] = 0x30; + info.spd[1][0][0x94] = 0x80; + info.spd[1][0][0x95] = 0xad; + +#endif + info.is_x16_module[0][0] = + (info.spd[0][0][RANKS_AND_DQ] & 7) - 1; + info.density[0][0] = info.spd[0][0][DENSITY] & 0xF; + + info.is_x16_module[1][0] = + (info.spd[1][0][RANKS_AND_DQ] & 7) - 1; + info.density[1][0] = info.spd[1][0][DENSITY] & 0xF; + } + +#if CONFIG_COLLECT_TIMESTAMPS + after_spd = rdtsc(); +#endif + + write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & 0xfc); +#if !REAL + my_read_msr (MTRRphysMask_MSR (3)); +#endif + + collect_system_info(&info); + calculate_timings(&info); + +#if !REAL + pci_mm_write8(NORTHBRIDGE, 0xdf, 0x82); +#endif + + if (!s3resume) { + u8 reg8 = pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2); + if (x2ca8 == 0 && (reg8 & 0x80)) { + /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9. + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8 | 0x08); + */ + + /* Clear bit7. */ + pci_write8(SOUTHBRIDGE, GEN_PMCON_2, + (reg8 & ~(1 << 7))); + + printk(BIOS_INFO, + "Interrupted RAM init, reset required.\n"); + outb(0x6, 0xcf9); +#if REAL + while (1) { + asm volatile ("hlt"); + } +#endif + } + } +#if !REAL + gav(read_mchbar8(0x2ca8)); ///!!!! +#endif + + if (!s3resume && x2ca8 == 0) + pci_mm_write8(SOUTHBRIDGE, GEN_PMCON_2, + pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80); + + compute_derived_timings(&info); + + if (x2ca8 == 0) { + gav(read_mchbar8(0x164)); + write_mchbar8(0x164, 0x26); + write_mchbar16(0x2c20, 0x10); + } + + write_mchbar32(0x18b4, read_mchbar32(0x18b4) | 0x210000); /* OK */ + write_mchbar32(0x1890, read_mchbar32(0x1890) | 0x2000000); /* OK */ + write_mchbar32(0x18b4, read_mchbar32(0x18b4) | 0x8000); + + gav(pci_mm_read32(0xff, 2, 1, 0x50)); // !!!! + pci_mm_write8(0xff, 2, 1, 0x54, 0x12); + + gav(read_mchbar16(0x2c10)); // !!!! + write_mchbar16(0x2c10, 0x412); + gav(read_mchbar16(0x2c10)); // !!!! + write_mchbar16(0x2c12, read_mchbar16(0x2c12) | 0x100); /* OK */ + + gav(read_mchbar8(0x2ca8)); // !!!! + write_mchbar32(0x1804, + (read_mchbar32(0x1804) & 0xfffffffc) | 0x8400080); + + pci_mm_read32(0xff, 2, 1, 0x6c); // !!!! + pci_mm_write32(0xff, 2, 1, 0x6c, 0x40a0a0); + gav(read_mchbar32(0x1c04)); // !!!! + gav(read_mchbar32(0x1804)); // !!!! + + if (x2ca8 == 0) { + write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1); + } + + write_mchbar32(0x18d8, 0x120000); + write_mchbar32(0x18dc, 0x30a484a); + pci_mm_write32(0xff, 2, 1, 0xe0, 0x0); + pci_mm_write32(0xff, 2, 1, 0xf4, 0x9444a); + write_mchbar32(0x18d8, 0x40000); + write_mchbar32(0x18dc, 0xb000000); + pci_mm_write32(0xff, 2, 1, 0xe0, 0x60000); + pci_mm_write32(0xff, 2, 1, 0xf4, 0x0); + write_mchbar32(0x18d8, 0x180000); + write_mchbar32(0x18dc, 0xc0000142); + pci_mm_write32(0xff, 2, 1, 0xe0, 0x20000); + pci_mm_write32(0xff, 2, 1, 0xf4, 0x142); + write_mchbar32(0x18d8, 0x1e0000); + + gav(read_mchbar32(0x18dc)); // !!!! + write_mchbar32(0x18dc, 0x3); + gav(read_mchbar32(0x18dc)); // !!!! + + if (x2ca8 == 0) { + write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1); // guess + } + + write_mchbar32(0x188c, 0x20bc09); + pci_mm_write32(0xff, 2, 1, 0xd0, 0x40b0c09); + write_mchbar32(0x1a10, 0x4200010e); + write_mchbar32(0x18b8, read_mchbar32(0x18b8) | 0x200); + gav(read_mchbar32(0x1918)); // !!!! + write_mchbar32(0x1918, 0x332); + + gav(read_mchbar32(0x18b8)); // !!!! + write_mchbar32(0x18b8, 0xe00); + gav(read_mchbar32(0x182c)); // !!!! + write_mchbar32(0x182c, 0x10202); + gav(pci_mm_read32(0xff, 2, 1, 0x94)); // !!!! + pci_mm_write32(0xff, 2, 1, 0x94, 0x10202); + write_mchbar32(0x1a1c, read_mchbar32(0x1a1c) & 0x8fffffff); + write_mchbar32(0x1a70, read_mchbar32(0x1a70) | 0x100000); + + write_mchbar32(0x18b4, read_mchbar32(0x18b4) & 0xffff7fff); + gav(read_mchbar32(0x1a68)); // !!!! + write_mchbar32(0x1a68, 0x343800); + gav(read_mchbar32(0x1e68)); // !!!! + gav(read_mchbar32(0x1a68)); // !!!! + + if (x2ca8 == 0) { + write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1); // guess + } + + pci_mm_read32(0xff, 2, 0, 0x048); // !!!! + pci_mm_write32(0xff, 2, 0, 0x048, 0x140000); + pci_mm_read32(0xff, 2, 0, 0x058); // !!!! + pci_mm_write32(0xff, 2, 0, 0x058, 0x64555); + pci_mm_read32(0xff, 2, 0, 0x058); // !!!! + pci_mm_read32(0xff, 0, 0, 0xd0); // !!!! + pci_mm_write32(0xff, 0, 0, 0xd0, 0x180); + gav(read_mchbar32(0x1af0)); // !!!! + gav(read_mchbar32(0x1af0)); // !!!! + write_mchbar32(0x1af0, 0x1f020003); + gav(read_mchbar32(0x1af0)); // !!!! + + if (((x2ca8 == 0))) { + write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) | 1); // guess + } + + gav(read_mchbar32(0x1890)); // !!!! + write_mchbar32(0x1890, 0x80102); + gav(read_mchbar32(0x18b4)); // !!!! + write_mchbar32(0x18b4, 0x216000); + write_mchbar32(0x18a4, 0x22222222); + write_mchbar32(0x18a8, 0x22222222); + write_mchbar32(0x18ac, 0x22222); + + udelay(1000); + + if (x2ca8 == 0) { + if (s3resume) { +#if REAL && 0 + info.reg2ca9_bit0 = 0; + info.reg274265[0][0] = 5; + info.reg274265[0][1] = 5; + info.reg274265[0][2] = 0xe; + info.reg274265[1][0] = 5; + info.reg274265[1][1] = 5; + info.reg274265[1][2] = 0xe; + info.delay46_ps[0] = 0xa86; + info.delay46_ps[1] = 0xa86; + info.delay54_ps[0] = 0xdc6; + info.delay54_ps[1] = 0xdc6; +#else + info.reg2ca9_bit0 = 0; + info.reg274265[0][0] = 3; + info.reg274265[0][1] = 5; + info.reg274265[0][2] = 0xd; + info.reg274265[1][0] = 4; + info.reg274265[1][1] = 5; + info.reg274265[1][2] = 0xd; + info.delay46_ps[0] = 0x110a; + info.delay46_ps[1] = 0xb58; + info.delay54_ps[0] = 0x144a; + info.delay54_ps[1] = 0xe98; +#endif + restore_274265(&info); + } else + set_274265(&info); + int j; + printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", info.reg2ca9_bit0); + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) + printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + i, j, info.reg274265[i][j]); + for (i = 0; i < 2; i++) + printk(BIOS_DEBUG, "delay46_ps[%d] = %x\n", i, + info.delay46_ps[i]); + for (i = 0; i < 2; i++) + printk(BIOS_DEBUG, "delay54_ps[%d] = %x\n", i, + info.delay54_ps[i]); + + set_2dxx_series(&info); + + if (!(deven & 8)) { + read_mchbar32(0x2cb0); + write_mchbar32(0x2cb0, 0x40); + } + + udelay(1000); + + if (deven & 8) { + write_mchbar32(0xff8, 0x1800 | read_mchbar32(0xff8)); + read_mchbar32(0x2cb0); + write_mchbar32(0x2cb0, 0x00); + pci_mm_read8(0, 0x2, 0x0, 0x4c); + pci_mm_read8(0, 0x2, 0x0, 0x4c); + pci_mm_read8(0, 0x2, 0x0, 0x4e); + + read_mchbar8(0x1150); + read_mchbar8(0x1151); + read_mchbar8(0x1022); + read_mchbar8(0x16d0); + write_mchbar32(0x1300, 0x60606060); + write_mchbar32(0x1304, 0x60606060); + write_mchbar32(0x1308, 0x78797a7b); + write_mchbar32(0x130c, 0x7c7d7e7f); + write_mchbar32(0x1310, 0x60606060); + write_mchbar32(0x1314, 0x60606060); + write_mchbar32(0x1318, 0x60606060); + write_mchbar32(0x131c, 0x60606060); + write_mchbar32(0x1320, 0x50515253); + write_mchbar32(0x1324, 0x54555657); + write_mchbar32(0x1328, 0x58595a5b); + write_mchbar32(0x132c, 0x5c5d5e5f); + write_mchbar32(0x1330, 0x40414243); + write_mchbar32(0x1334, 0x44454647); + write_mchbar32(0x1338, 0x48494a4b); + write_mchbar32(0x133c, 0x4c4d4e4f); + write_mchbar32(0x1340, 0x30313233); + write_mchbar32(0x1344, 0x34353637); + write_mchbar32(0x1348, 0x38393a3b); + write_mchbar32(0x134c, 0x3c3d3e3f); + write_mchbar32(0x1350, 0x20212223); + write_mchbar32(0x1354, 0x24252627); + write_mchbar32(0x1358, 0x28292a2b); + write_mchbar32(0x135c, 0x2c2d2e2f); + write_mchbar32(0x1360, 0x10111213); + write_mchbar32(0x1364, 0x14151617); + write_mchbar32(0x1368, 0x18191a1b); + write_mchbar32(0x136c, 0x1c1d1e1f); + write_mchbar32(0x1370, 0x10203); + write_mchbar32(0x1374, 0x4050607); + write_mchbar32(0x1378, 0x8090a0b); + write_mchbar32(0x137c, 0xc0d0e0f); + write_mchbar8(0x11cc, 0x4e); + write_mchbar32(0x1110, 0x73970404); + write_mchbar32(0x1114, 0x72960404); + write_mchbar32(0x1118, 0x6f950404); + write_mchbar32(0x111c, 0x6d940404); + write_mchbar32(0x1120, 0x6a930404); + write_mchbar32(0x1124, 0x68a41404); + write_mchbar32(0x1128, 0x66a21404); + write_mchbar32(0x112c, 0x63a01404); + write_mchbar32(0x1130, 0x609e1404); + write_mchbar32(0x1134, 0x5f9c1404); + write_mchbar32(0x1138, 0x5c961404); + write_mchbar32(0x113c, 0x58a02404); + write_mchbar32(0x1140, 0x54942404); + write_mchbar32(0x1190, 0x900080a); + write_mchbar16(0x11c0, 0xc40b); + write_mchbar16(0x11c2, 0x303); + write_mchbar16(0x11c4, 0x301); + read_mchbar32(0x1190); + write_mchbar32(0x1190, 0x8900080a); + write_mchbar32(0x11b8, 0x70c3000); + write_mchbar8(0x11ec, 0xa); + write_mchbar16(0x1100, 0x800); + read_mchbar32(0x11bc); + write_mchbar32(0x11bc, 0x1e84800); + write_mchbar16(0x11ca, 0xfa); + write_mchbar32(0x11e4, 0x4e20); + write_mchbar8(0x11bc, 0xf); + write_mchbar16(0x11da, 0x19); + write_mchbar16(0x11ba, 0x470c); + write_mchbar32(0x1680, 0xe6ffe4ff); + write_mchbar32(0x1684, 0xdeffdaff); + write_mchbar32(0x1688, 0xd4ffd0ff); + write_mchbar32(0x168c, 0xccffc6ff); + write_mchbar32(0x1690, 0xc0ffbeff); + write_mchbar32(0x1694, 0xb8ffb0ff); + write_mchbar32(0x1698, 0xa8ff0000); + write_mchbar32(0x169c, 0xc00); + write_mchbar32(0x1290, 0x5000000); + } + + write_mchbar32(0x124c, 0x15040d00); + write_mchbar32(0x1250, 0x7f0000); + write_mchbar32(0x1254, 0x1e220004); + write_mchbar32(0x1258, 0x4000004); + write_mchbar32(0x1278, 0x0); + write_mchbar32(0x125c, 0x0); + write_mchbar32(0x1260, 0x0); + write_mchbar32(0x1264, 0x0); + write_mchbar32(0x1268, 0x0); + write_mchbar32(0x126c, 0x0); + write_mchbar32(0x1270, 0x0); + write_mchbar32(0x1274, 0x0); + } + + if ((deven & 8) && x2ca8 == 0) { + write_mchbar16(0x1214, 0x320); + write_mchbar32(0x1600, 0x40000000); + read_mchbar32(0x11f4); + write_mchbar32(0x11f4, 0x10000000); + read_mchbar16(0x1230); + write_mchbar16(0x1230, 0x8000); + write_mchbar32(0x1400, 0x13040020); + write_mchbar32(0x1404, 0xe090120); + write_mchbar32(0x1408, 0x5120220); + write_mchbar32(0x140c, 0x5120330); + write_mchbar32(0x1410, 0xe090220); + write_mchbar32(0x1414, 0x1010001); + write_mchbar32(0x1418, 0x1110000); + write_mchbar32(0x141c, 0x9020020); + write_mchbar32(0x1420, 0xd090220); + write_mchbar32(0x1424, 0x2090220); + write_mchbar32(0x1428, 0x2090330); + write_mchbar32(0x142c, 0xd090220); + write_mchbar32(0x1430, 0x1010001); + write_mchbar32(0x1434, 0x1110000); + write_mchbar32(0x1438, 0x11040020); + write_mchbar32(0x143c, 0x4030220); + write_mchbar32(0x1440, 0x1060220); + write_mchbar32(0x1444, 0x1060330); + write_mchbar32(0x1448, 0x4030220); + write_mchbar32(0x144c, 0x1010001); + write_mchbar32(0x1450, 0x1110000); + write_mchbar32(0x1454, 0x4010020); + write_mchbar32(0x1458, 0xb090220); + write_mchbar32(0x145c, 0x1090220); + write_mchbar32(0x1460, 0x1090330); + write_mchbar32(0x1464, 0xb090220); + write_mchbar32(0x1468, 0x1010001); + write_mchbar32(0x146c, 0x1110000); + write_mchbar32(0x1470, 0xf040020); + write_mchbar32(0x1474, 0xa090220); + write_mchbar32(0x1478, 0x1120220); + write_mchbar32(0x147c, 0x1120330); + write_mchbar32(0x1480, 0xa090220); + write_mchbar32(0x1484, 0x1010001); + write_mchbar32(0x1488, 0x1110000); + write_mchbar32(0x148c, 0x7020020); + write_mchbar32(0x1490, 0x1010220); + write_mchbar32(0x1494, 0x10210); + write_mchbar32(0x1498, 0x10320); + write_mchbar32(0x149c, 0x1010220); + write_mchbar32(0x14a0, 0x1010001); + write_mchbar32(0x14a4, 0x1110000); + write_mchbar32(0x14a8, 0xd040020); + write_mchbar32(0x14ac, 0x8090220); + write_mchbar32(0x14b0, 0x1111310); + write_mchbar32(0x14b4, 0x1111420); + write_mchbar32(0x14b8, 0x8090220); + write_mchbar32(0x14bc, 0x1010001); + write_mchbar32(0x14c0, 0x1110000); + write_mchbar32(0x14c4, 0x3010020); + write_mchbar32(0x14c8, 0x7090220); + write_mchbar32(0x14cc, 0x1081310); + write_mchbar32(0x14d0, 0x1081420); + write_mchbar32(0x14d4, 0x7090220); + write_mchbar32(0x14d8, 0x1010001); + write_mchbar32(0x14dc, 0x1110000); + write_mchbar32(0x14e0, 0xb040020); + write_mchbar32(0x14e4, 0x2030220); + write_mchbar32(0x14e8, 0x1051310); + write_mchbar32(0x14ec, 0x1051420); + write_mchbar32(0x14f0, 0x2030220); + write_mchbar32(0x14f4, 0x1010001); + write_mchbar32(0x14f8, 0x1110000); + write_mchbar32(0x14fc, 0x5020020); + write_mchbar32(0x1500, 0x5090220); + write_mchbar32(0x1504, 0x2071310); + write_mchbar32(0x1508, 0x2071420); + write_mchbar32(0x150c, 0x5090220); + write_mchbar32(0x1510, 0x1010001); + write_mchbar32(0x1514, 0x1110000); + write_mchbar32(0x1518, 0x7040120); + write_mchbar32(0x151c, 0x2090220); + write_mchbar32(0x1520, 0x70b1210); + write_mchbar32(0x1524, 0x70b1310); + write_mchbar32(0x1528, 0x2090220); + write_mchbar32(0x152c, 0x1010001); + write_mchbar32(0x1530, 0x1110000); + write_mchbar32(0x1534, 0x1010110); + write_mchbar32(0x1538, 0x1081310); + write_mchbar32(0x153c, 0x5041200); + write_mchbar32(0x1540, 0x5041310); + write_mchbar32(0x1544, 0x1081310); + write_mchbar32(0x1548, 0x1010001); + write_mchbar32(0x154c, 0x1110000); + write_mchbar32(0x1550, 0x1040120); + write_mchbar32(0x1554, 0x4051210); + write_mchbar32(0x1558, 0xd051200); + write_mchbar32(0x155c, 0xd051200); + write_mchbar32(0x1560, 0x4051210); + write_mchbar32(0x1564, 0x1010001); + write_mchbar32(0x1568, 0x1110000); + write_mchbar16(0x1222, 0x220a); + write_mchbar16(0x123c, 0x1fc0); + write_mchbar16(0x1220, 0x1388); + } + + read_mchbar32(0x2c80); // !!!! + write_mchbar32(0x2c80, 0x1053688); + read_mchbar32(0x1c04); // !!!! + write_mchbar32(0x1804, 0x406080); + + read_mchbar8(0x2ca8); + + if (x2ca8 == 0) { + write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & ~3); + write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4); + write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10); +#if REAL + while (1) { + asm volatile ("hlt"); + } +#else + printf("CP5\n"); + exit(0); +#endif + } + + write_mchbar8(0x2ca8, read_mchbar8(0x2ca8)); + read_mchbar32(0x2c80); // !!!! + write_mchbar32(0x2c80, 0x53688); + pci_mm_write32(0xff, 0, 0, 0x60, 0x20220); + read_mchbar16(0x2c20); // !!!! + read_mchbar16(0x2c10); // !!!! + read_mchbar16(0x2c00); // !!!! + write_mchbar16(0x2c00, 0x8c0); + udelay(1000); + write_1d0(0, 0x33d, 0, 0); + write_500(&info, 0, 0, 0xb61, 0, 0); + write_500(&info, 1, 0, 0xb61, 0, 0); + write_mchbar32(0x1a30, 0x0); + write_mchbar32(0x1a34, 0x0); + write_mchbar16(0x614, + 0xb5b | (info.populated_ranks[1][0][0] * + 0x404) | (info.populated_ranks[0][0][0] * + 0xa0)); + write_mchbar16(0x616, 0x26a); + write_mchbar32(0x134, 0x856000); + write_mchbar32(0x160, 0x5ffffff); + read_mchbar32(0x114); // !!!! + write_mchbar32(0x114, 0xc2024440); + read_mchbar32(0x118); // !!!! + write_mchbar32(0x118, 0x4); + for (channel = 0; channel < NUM_CHANNELS; channel++) + write_mchbar32(0x260 + (channel << 10), + 0x30809ff | + ((info. + populated_ranks_mask[channel] & 3) << 20)); + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_mchbar16(0x31c + (channel << 10), 0x101); + write_mchbar16(0x360 + (channel << 10), 0x909); + write_mchbar16(0x3a4 + (channel << 10), 0x101); + write_mchbar16(0x3e8 + (channel << 10), 0x101); + write_mchbar32(0x320 + (channel << 10), 0x29002900); + write_mchbar32(0x324 + (channel << 10), 0x0); + write_mchbar32(0x368 + (channel << 10), 0x32003200); + write_mchbar16(0x352 + (channel << 10), 0x505); + write_mchbar16(0x354 + (channel << 10), 0x3c3c); + write_mchbar16(0x356 + (channel << 10), 0x1040); + write_mchbar16(0x39a + (channel << 10), 0x73e4); + write_mchbar16(0x3de + (channel << 10), 0x77ed); + write_mchbar16(0x422 + (channel << 10), 0x1040); + } + + write_1d0(0x4, 0x151, 4, 1); + write_1d0(0, 0x142, 3, 1); + my_read_msr(0x1ac); // !!!! + write_500(&info, 1, 1, 0x6b3, 4, 1); + write_500(&info, 1, 1, 0x6cf, 4, 1); + + rmw_1d0(0x21c, 0x38, 0, 6, 1); + + write_1d0(((!info.populated_ranks[1][0][0]) << 1) | ((!info. + populated_ranks[0] + [0][0]) << 0), + 0x1d1, 3, 1); + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_mchbar16(0x38e + (channel << 10), 0x5f5f); + write_mchbar16(0x3d2 + (channel << 10), 0x5f5f); + } + + set_334(0); + + program_base_timings(&info); + + write_mchbar8(0x5ff, read_mchbar8(0x5ff) | 0x80); /* OK */ + + write_1d0(0x2, 0x1d5, 2, 1); + write_1d0(0x20, 0x166, 7, 1); + write_1d0(0x0, 0xeb, 3, 1); + write_1d0(0x0, 0xf3, 6, 1); + + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (lane = 0; lane < 9; lane++) { + u16 addr = 0x125 + get_lane_offset(0, 0, lane); + u8 a; + a = read_500(&info, channel, addr, 6); // = 0x20040080 //!!!! + write_500(&info, channel, a, addr, 6, 1); + } + + udelay(1000); + + info.cached_training = get_cached_training(); + + if (s3resume) { + if (info.cached_training == NULL) { + u32 reg32; + printk(BIOS_ERR, + "Couldn't find training data. Rebooting\n"); + reg32 = inl(DEFAULT_PMBASE + 0x04); + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + outb(0xe, 0xcf9); + +#if REAL + while (1) { + asm volatile ("hlt"); + } +#else + printf("CP5\n"); + exit(0); +#endif + } + int tm; + info.training = *info.cached_training; + for (tm = 0; tm < 4; tm++) + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + for (lane = 0; lane < 9; lane++) + write_500(&info, + channel, + info.training. + lane_timings + [tm][channel] + [slot][rank] + [lane], + get_timing_register_addr + (lane, tm, + slot, rank), + 9, 0); + write_1d0(info.cached_training->reg_178, 0x178, 7, 1); + write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1); + } + + read_mchbar32(0x1f4); // !!!! + write_mchbar32(0x1f4, 0x20000); + write_mchbar32(0x1f0, 0x1d000200); + read_mchbar8(0x1f0); // !!!! + write_mchbar8(0x1f0, 0x1); + read_mchbar8(0x1f0); // !!!! + + program_board_delay(&info); + + write_mchbar8(0x5ff, 0x0); /* OK */ + write_mchbar8(0x5ff, 0x80); /* OK */ + write_mchbar8(0x5f4, 0x1); /* OK */ + + write_mchbar32(0x130, read_mchbar32(0x130) & 0xfffffffd); // | 2 when ? + while (read_mchbar32(0x130) & 1) ; + gav(read_1d0(0x14b, 7)); // = 0x81023100 + write_1d0(0x30, 0x14b, 7, 1); + read_1d0(0xd6, 6); // = 0xfa008080 // !!!! + write_1d0(7, 0xd6, 6, 1); + read_1d0(0x328, 6); // = 0xfa018080 // !!!! + write_1d0(7, 0x328, 6, 1); + + for (channel = 0; channel < NUM_CHANNELS; channel++) + set_4cf(&info, channel, + info.populated_ranks[channel][0][0] ? 8 : 0); + + read_1d0(0x116, 4); // = 0x4040432 // !!!! + write_1d0(2, 0x116, 4, 1); + read_1d0(0xae, 6); // = 0xe8088080 // !!!! + write_1d0(0, 0xae, 6, 1); + read_1d0(0x300, 4); // = 0x48088080 // !!!! + write_1d0(0, 0x300, 6, 1); + read_mchbar16(0x356); // !!!! + write_mchbar16(0x356, 0x1040); + read_mchbar16(0x756); // !!!! + write_mchbar16(0x756, 0x1040); + write_mchbar32(0x140, read_mchbar32(0x140) & ~0x07000000); + write_mchbar32(0x138, read_mchbar32(0x138) & ~0x07000000); + write_mchbar32(0x130, 0x31111301); + while (read_mchbar32(0x130) & 1) ; + + { + u32 t; + u8 val_a1; + val_a1 = read_1d0(0xa1, 6); // = 0x1cf4040 // !!!! + t = read_1d0(0x2f3, 6); // = 0x10a4040 // !!!! + rmw_1d0(0x320, 0x07, + (t & 4) | ((t & 8) >> 2) | ((t & 0x10) >> 4), 6, 1); + rmw_1d0(0x14b, 0x78, + ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 & + 4), 7, + 1); + rmw_1d0(0xce, 0x38, + ((((val_a1 >> 2) & 4) | (val_a1 & 8)) >> 2) | (val_a1 & + 4), 6, + 1); + } + + for (channel = 0; channel < NUM_CHANNELS; channel++) + set_4cf(&info, channel, + info.populated_ranks[channel][0][0] ? 9 : 1); + + rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!! + read_mchbar32(0x144); // !!!! + write_1d0(2, 0xae, 6, 1); + write_1d0(2, 0x300, 6, 1); + write_1d0(2, 0x121, 3, 1); + read_1d0(0xd6, 6); // = 0xfa00c0c7 // !!!! + write_1d0(4, 0xd6, 6, 1); + read_1d0(0x328, 6); // = 0xfa00c0c7 // !!!! + write_1d0(4, 0x328, 6, 1); + + for (channel = 0; channel < NUM_CHANNELS; channel++) + set_4cf(&info, channel, + info.populated_ranks[channel][0][0] ? 9 : 0); + + write_mchbar32(0x130, + 0x11111301 | (info. + populated_ranks[1][0][0] << 30) | (info. + populated_ranks + [0][0] + [0] << + 29)); + while (read_mchbar8(0x130) & 1) ; // !!!! + read_1d0(0xa1, 6); // = 0x1cf4054 // !!!! + read_1d0(0x2f3, 6); // = 0x10a4054 // !!!! + read_1d0(0x21c, 6); // = 0xafa00c0 // !!!! + write_1d0(0, 0x21c, 6, 1); + read_1d0(0x14b, 7); // = 0x810231b0 // !!!! + write_1d0(0x35, 0x14b, 7, 1); + + for (channel = 0; channel < NUM_CHANNELS; channel++) + set_4cf(&info, channel, + info.populated_ranks[channel][0][0] ? 0xb : 0x2); + + set_334(1); + + write_mchbar8(0x1e8, 0x4); /* OK */ + + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_500(&info, channel, + 0x3 & ~(info.populated_ranks_mask[channel]), 0x6b7, 2, + 1); + write_500(&info, channel, 0x3, 0x69b, 2, 1); + } + write_mchbar32(0x2d0, (read_mchbar32(0x2d0) & 0xff2c01ff) | 0x200000); /* OK */ + write_mchbar16(0x6c0, 0x14a0); /* OK */ + write_mchbar32(0x6d0, (read_mchbar32(0x6d0) & 0xff0080ff) | 0x8000); /* OK */ + write_mchbar16(0x232, 0x8); + write_mchbar32(0x234, (read_mchbar32(0x234) & 0xfffbfffb) | 0x40004); /* 0x40004 or 0 depending on ? */ + write_mchbar32(0x34, (read_mchbar32(0x34) & 0xfffffffd) | 5); /* OK */ + write_mchbar32(0x128, 0x2150d05); + write_mchbar8(0x12c, 0x1f); /* OK */ + write_mchbar8(0x12d, 0x56); /* OK */ + write_mchbar8(0x12e, 0x31); + write_mchbar8(0x12f, 0x0); /* OK */ + write_mchbar8(0x271, 0x2); /* OK */ + write_mchbar8(0x671, 0x2); /* OK */ + write_mchbar8(0x1e8, 0x4); /* OK */ + for (channel = 0; channel < NUM_CHANNELS; channel++) + write_mchbar32(0x294 + (channel << 10), + (info.populated_ranks_mask[channel] & 3) << 16); + write_mchbar32(0x134, (read_mchbar32(0x134) & 0xfc01ffff) | 0x10000); /* OK */ + write_mchbar32(0x134, (read_mchbar32(0x134) & 0xfc85ffff) | 0x850000); /* OK */ + for (channel = 0; channel < NUM_CHANNELS; channel++) + write_mchbar32(0x260 + (channel << 10), + (read_mchbar32(0x260 + (channel << 10)) & + ~0xf00000) | 0x8000000 | ((info. + populated_ranks_mask + [channel] & 3) << + 20)); + + if (!s3resume) + jedec_init(&info); + + int totalrank = 0; + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + if (info.populated_ranks[channel][slot][rank]) { + jedec_read(&info, channel, slot, rank, + totalrank, 0xa, 0x400); + totalrank++; + } + + write_mchbar8(0x12c, 0x9f); + + read_mchbar8(0x271); // 2 // !!!! + write_mchbar8(0x271, 0xe); + read_mchbar8(0x671); // !!!! + write_mchbar8(0x671, 0xe); + + if (!s3resume) { + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_mchbar32(0x294 + (channel << 10), + (info. + populated_ranks_mask[channel] & 3) << + 16); + write_mchbar16(0x298 + (channel << 10), + (info. + populated_ranks[channel][0][0]) | (info. + populated_ranks + [channel] + [0] + [1] + << + 5)); + write_mchbar32(0x29c + (channel << 10), 0x77a); + } + read_mchbar32(0x2c0); /// !!! + write_mchbar32(0x2c0, 0x6009cc00); + + { + u8 a, b; + a = read_mchbar8(0x243); // !!!! + b = read_mchbar8(0x643); // !!!! + write_mchbar8(0x243, a | 2); + write_mchbar8(0x643, b | 2); + } + + write_1d0(7, 0x19b, 3, 1); + write_1d0(7, 0x1c0, 3, 1); + write_1d0(4, 0x1c6, 4, 1); + write_1d0(4, 0x1cc, 4, 1); + read_1d0(0x151, 4); // = 0x408c6d74 // !!!! + write_1d0(4, 0x151, 4, 1); + write_mchbar32(0x584, 0xfffff); + write_mchbar32(0x984, 0xfffff); + + for (channel = 0; channel < NUM_CHANNELS; channel++) + for (slot = 0; slot < NUM_SLOTS; slot++) + for (rank = 0; rank < NUM_RANKS; rank++) + if (info. + populated_ranks[channel][slot] + [rank]) + config_rank(&info, s3resume, + channel, slot, + rank); + + write_mchbar8(0x243, 0x1); + write_mchbar8(0x643, 0x1); + } + + /* was == 1 but is common */ + pci_mm_write16(NORTHBRIDGE, 0xc8, 3); + write_26c(0, 0x820); + write_26c(1, 0x820); + write_mchbar32(0x130, read_mchbar32(0x130) | 2); + /* end */ + + if (s3resume) { + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_mchbar32(0x294 + (channel << 10), + (info. + populated_ranks_mask[channel] & 3) << + 16); + write_mchbar16(0x298 + (channel << 10), + (info. + populated_ranks[channel][0][0]) | (info. + populated_ranks + [channel] + [0] + [1] + << + 5)); + write_mchbar32(0x29c + (channel << 10), 0x77a); + } + read_mchbar32(0x2c0); /// !!! + write_mchbar32(0x2c0, 0x6009cc00); + } + + write_mchbar32(0xfa4, read_mchbar32(0xfa4) & ~0x01000002); + write_mchbar32(0xfb0, 0x2000e019); + +#if !REAL + printf("CP16\n"); +#endif + +#if CONFIG_COLLECT_TIMESTAMPS + before_training = rdtsc(); +#endif + + if (!s3resume) + ram_training(&info); + +#if CONFIG_COLLECT_TIMESTAMPS + after_training = rdtsc(); +#endif + + dump_timings(&info); + +#if 0 + ram_check(0x100000, 0x200000); +#endif + program_modules_memory_map(&info, 0); + program_total_memory_map(&info); + + if (info.non_interleaved_part_mb != 0 && info.interleaved_part_mb != 0) + write_mchbar8(0x111, 0x20 | (0 << 2) | (1 << 6) | (0 << 7)); + else if (have_match_ranks(&info, 0, 4) && have_match_ranks(&info, 1, 4)) + write_mchbar8(0x111, 0x20 | (3 << 2) | (0 << 6) | (1 << 7)); + else if (have_match_ranks(&info, 0, 2) && have_match_ranks(&info, 1, 2)) + write_mchbar8(0x111, 0x20 | (3 << 2) | (0 << 6) | (0 << 7)); + else + write_mchbar8(0x111, 0x20 | (3 << 2) | (1 << 6) | (0 << 7)); + + write_mchbar32(0xfac, read_mchbar32(0xfac) & ~0x80000000); // OK + write_mchbar32(0xfb4, 0x4800); // OK + write_mchbar32(0xfb8, (info.revision < 8) ? 0x20 : 0x0); // OK + write_mchbar32(0xe94, 0x7ffff); // OK + write_mchbar32(0xfc0, 0x80002040); // OK + write_mchbar32(0xfc4, 0x701246); // OK + write_mchbar8(0xfc8, read_mchbar8(0xfc8) & ~0x70); // OK + write_mchbar32(0xe5c, 0x1000000 | read_mchbar32(0xe5c)); // OK + write_mchbar32(0x1a70, (read_mchbar32(0x1a70) | 0x00200000) & ~0x00100000); // OK + write_mchbar32(0x50, 0x700b0); // OK + write_mchbar32(0x3c, 0x10); // OK + write_mchbar8(0x1aa8, (read_mchbar8(0x1aa8) & ~0x35) | 0xa); // OK + write_mchbar8(0xff4, read_mchbar8(0xff4) | 0x2); // OK + write_mchbar32(0xff8, (read_mchbar32(0xff8) & ~0xe008) | 0x1020); // OK + +#if REAL + write_mchbar32(0xd00, IOMMU_BASE2 | 1); + write_mchbar32(0xd40, IOMMU_BASE1 | 1); + write_mchbar32(0xdc0, IOMMU_BASE4 | 1); + + write32(IOMMU_BASE1 | 0xffc, 0x80000000); + write32(IOMMU_BASE2 | 0xffc, 0xc0000000); + write32(IOMMU_BASE4 | 0xffc, 0x80000000); + +#else + { + u32 eax; + eax = read32(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000; // = 0xe911714b// OK + write32(0xffc + (read_mchbar32(0xd00) & ~1), eax); // OK + eax = read32(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000; // = 0xe911714b// OK + write32(0xffc + (read_mchbar32(0xdc0) & ~1), eax); // OK + } +#endif + + { + u32 eax; + + eax = info.fsb_frequency / 9; + write_mchbar32(0xfcc, (read_mchbar32(0xfcc) & 0xfffc0000) | (eax * 0x280) | (eax * 0x5000) | eax | 0x40000); // OK + write_mchbar32(0x20, 0x33001); //OK + } + + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_mchbar32(0x220 + (channel << 10), read_mchbar32(0x220 + (channel << 10)) & ~0x7770); //OK + if (info.max_slots_used_in_channel == 1) + write_mchbar16(0x237 + (channel << 10), (read_mchbar16(0x237 + (channel << 10)) | 0x0201)); //OK + else + write_mchbar16(0x237 + (channel << 10), (read_mchbar16(0x237 + (channel << 10)) & ~0x0201)); //OK + + write_mchbar8(0x241 + (channel << 10), read_mchbar8(0x241 + (channel << 10)) | 1); // OK + + if (info.clock_speed_index <= 1 + && (info.silicon_revision == 2 + || info.silicon_revision == 3)) + write_mchbar32(0x248 + (channel << 10), (read_mchbar32(0x248 + (channel << 10)) | 0x00102000)); // OK + else + write_mchbar32(0x248 + (channel << 10), (read_mchbar32(0x248 + (channel << 10)) & ~0x00102000)); // OK + } + + write_mchbar32(0x115, read_mchbar32(0x115) | 0x1000000); // OK + + { + u8 al; + al = 0xd; + if (!(info.silicon_revision == 0 || info.silicon_revision == 1)) + al += 2; + al |= ((1 << (info.max_slots_used_in_channel - 1)) - 1) << 4; + write_mchbar32(0x210, (al << 16) | 0x20); // OK + } + + for (channel = 0; channel < NUM_CHANNELS; channel++) { + write_mchbar32(0x288 + (channel << 10), 0x70605040); // OK + write_mchbar32(0x28c + (channel << 10), 0xfffec080); // OK + write_mchbar32(0x290 + (channel << 10), 0x282091c | ((info.max_slots_used_in_channel - 1) << 0x16)); // OK + } + u32 reg1c; + pci_mm_read32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK + reg1c = read32(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK + pci_mm_read32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK + write32(DEFAULT_EPBAR | 0x01c, reg1c); // OK + read_mchbar8(0xe08); // = 0x0 + pci_mm_read32(NORTHBRIDGE, 0xe4); // = 0x316126 + write_mchbar8(0x1210, read_mchbar8(0x1210) | 2); // OK + write_mchbar32(0x1200, 0x8800440); // OK + write_mchbar32(0x1204, 0x53ff0453); // OK + write_mchbar32(0x1208, 0x19002043); // OK + write_mchbar16(0x1214, 0x320); // OK + + if (info.revision == 0x10 || info.revision == 0x11) { + write_mchbar16(0x1214, 0x220); // OK + write_mchbar8(0x1210, read_mchbar8(0x1210) | 0x40); // OK + } + + write_mchbar8(0x1214, read_mchbar8(0x1214) | 0x4); // OK + write_mchbar8(0x120c, 0x1); // OK + write_mchbar8(0x1218, 0x3); // OK + write_mchbar8(0x121a, 0x3); // OK + write_mchbar8(0x121c, 0x3); // OK + write_mchbar16(0xc14, 0x0); // OK + write_mchbar16(0xc20, 0x0); // OK + write_mchbar32(0x1c, 0x0); // OK + + /* revision dependent here. */ + + write_mchbar16(0x1230, read_mchbar16(0x1230) | 0x1f07); // OK + + if (info.uma_enabled) + write_mchbar32(0x11f4, read_mchbar32(0x11f4) | 0x10000000); // OK + + write_mchbar16(0x1230, read_mchbar16(0x1230) | 0x8000); // OK + write_mchbar8(0x1214, read_mchbar8(0x1214) | 1); // OK + + u8 bl, ebpb; + u16 reg_1020; + + reg_1020 = read_mchbar32(0x1020); // = 0x6c733c // OK + write_mchbar8(0x1070, 0x1); // OK + + write_mchbar32(0x1000, 0x100); // OK + write_mchbar8(0x1007, 0x0); // OK + + if (reg_1020 != 0) { + write_mchbar16(0x1018, 0x0); // OK + bl = reg_1020 >> 8; + ebpb = reg_1020 & 0xff; + } else { + ebpb = 0; + bl = 8; + } + + my_read_msr(0x1a2); + + write_mchbar32(0x1014, 0xffffffff); // OK + + write_mchbar32(0x1010, ((((ebpb + 0x7d) << 7) / bl) & 0xff) * (! !reg_1020)); // OK + + write_mchbar8(0x101c, 0xb8); // OK + + write_mchbar8(0x123e, (read_mchbar8(0x123e) & 0xf) | 0x60); // OK + if (reg_1020 != 0) { + write_mchbar32(0x123c, (read_mchbar32(0x123c) & ~0x00900000) | 0x600000); // OK + write_mchbar8(0x101c, 0xb8); // OK + } + + setup_heci_uma(&info); + + if (info.uma_enabled) { + u16 ax; + write_mchbar32(0x11b0, read_mchbar32(0x11b0) | 0x4000); // OK + write_mchbar32(0x11b4, read_mchbar32(0x11b4) | 0x4000); // OK + write_mchbar16(0x1190, read_mchbar16(0x1190) | 0x4000); // OK + + ax = read_mchbar16(0x1190) & 0xf00; // = 0x480a // OK + write_mchbar16(0x1170, ax | (read_mchbar16(0x1170) & 0x107f) | 0x4080); // OK + write_mchbar16(0x1170, read_mchbar16(0x1170) | 0x1000); // OK +#if REAL + udelay(1000); +#endif + u16 ecx; + for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--) ; // OK + write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000); // OK + } + + pci_mm_write8(SOUTHBRIDGE, GEN_PMCON_2, + pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80); + udelay(10000); + write_mchbar16(0x2ca8, 0x0); + +#if REAL + udelay(1000); + dump_timings(&info); + if (!s3resume) + save_timings(&info); +#endif +} + +#if REAL +unsigned long get_top_of_ram(void) +{ + /* Base of TSEG is top of usable DRAM */ + u32 tom = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + return (unsigned long)tom; +} +#endif + +#if !REAL +int main(void) +{ + raminit(0); + return 0; +} +#endif diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/nehalem/raminit.h new file mode 100644 index 0000000..c6beb17 --- /dev/null +++ b/src/northbridge/intel/nehalem/raminit.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef RAMINIT_H +#define RAMINIT_H + +#include "nehalem.h" + +void raminit(int s3resume); +int fixup_sandybridge_errata(void); + +#endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/nehalem/raminit_fake.c b/src/northbridge/intel/nehalem/raminit_fake.c new file mode 100644 index 0000000..df06040 --- /dev/null +++ b/src/northbridge/intel/nehalem/raminit_fake.c @@ -0,0 +1,2056 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static u32 gav_real(int line, u32 in) +{ + // printf ("%d: GAV: %x\n", line, in); + return in; +} + +#define gav(x) gav_real (__LINE__, (x)) + +#include <parse.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + +static void pm_wait(u16 us); + +#define ARRAY_SIZE(array) (sizeof (array) / sizeof (array[0])) + +#define CONFIG_SMM_TSEG_SIZE (8 << 20) + +#define MTRR_TYPE_WRPROT 5 +#define MTRRdefTypeEn (1 << 11) +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) +#define MTRRcap_MSR 0x0fe + +#include "include/cpu/intel/speedstep.h" +#include "include/cpu/intel/turbo.h" + +#define PCI_VENDOR_ID 0x00 /* 16 bits */ +#define PCI_COMMAND 0x04 /* 16 bits */ +#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ +#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ +#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ +#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ +#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ +#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ +#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ +#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ +#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ +#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ +#define PCI_REVISION_ID 8 +#define PCI_DEVICE_ID 2 + +#define CONFIG_MMCONF_BASE_ADDRESS 0xe0000000 + +#define PCI_SUBSYSTEM_VENDOR_ID 0x2c + +static void write32(u32 addr, u32 val) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (op.is_in || op.data_width != 32 || op.addr != addr || op.val != val + || op.type != MEM) { + printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, + op.addr, op.val); + exit(1); + } +} + +static void write16(u32 addr, u16 val) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val + || op.type != MEM) { + printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, + op.addr, op.val); + exit(1); + } +} + +static void write8(u32 addr, u8 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 8 || op.addr != addr || op.val != val + || op.type != MEM) { + printf("Bad %d\n", __LINE__); + exit(1); + } +} + +static int smbus_read_byte(u32 dev, u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (!op.is_in || op.data_width != 8 || op.addr != addr + || op.type != SMBUS || op.dev != dev) { + printf("Bad %d: %x, %d vs %x, %d\n", __LINE__, op.addr, SMBUS, + addr, op.type); + exit(1); + } + return (signed short)op.val; +} + +static int smbus_block_read(u32 dev, u32 addr, u32 len, u8 * block) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (!op.is_in || op.data_width != len || op.addr != addr + || op.type != OPCODE_SMBUS_BLOCK || op.dev != dev) { + printf("Bad %d: %x, %d vs %x, %d\n", __LINE__, op.addr, + OPCODE_SMBUS_BLOCK, addr, op.type); + exit(1); + } + memcpy(block, &op.val, len); + return 0; +} + +static int smbus_block_write(u32 dev, u32 addr, u32 len, const u8 * block) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (op.is_in || op.data_width != len || op.addr != addr + || op.type != OPCODE_SMBUS_BLOCK || op.dev != dev + || memcmp(block, &op.val, len) != 0) { + printf("Bad %d: %x, %d vs %x, %d\n", __LINE__, op.addr, + OPCODE_SMBUS_BLOCK, addr, op.type); + exit(1); + } + return 0; +} + +static void smbus_write_byte(u32 dev, u32 addr, u8 val) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (op.is_in || op.data_width != 8 || op.addr != addr + || op.type != SMBUS || op.dev != dev || op.val != val) { + printf("Bad %d: %x, %d vs %x, %d\n", __LINE__, addr, SMBUS, + op.addr, op.type); + exit(1); + } +} + +static void write_mchbar32(u32 addr, u32 val) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (op.is_in || op.data_width != 32 || op.addr != addr || op.val != val + || op.type != OPCODE_MCHBAR) { + printf("Bad [%x] = %x vs [%x] = %llx\n", addr, val, op.addr, + op.val); + exit(1); + } +} + +static void write_acpi32(u32 addr, u32 val) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (op.is_in || op.data_width != 32 || op.addr != addr || op.val != val + || op.type != ACPI) { + printf("Bad [%x] = %x vs [%x] = %llx\n", addr, val, op.addr, + op.val); + exit(1); + } +} + +static void write_mchbar16(u32 addr, u16 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val + || op.type != OPCODE_MCHBAR) { + printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, + op.addr, op.val); + exit(1); + } +} + +static void write_acpi16(u32 addr, u16 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val + || op.type != ACPI) { + printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, + op.addr, op.val); + exit(1); + } +} + +static void write_tco16(u32 addr, u16 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 16 || op.addr != addr || op.val != val + || op.type != TCO) { + printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, + op.addr, op.val); + exit(1); + } +} + +static void write_tco8(u32 addr, u8 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 8 || op.addr != addr || op.val != val + || op.type != TCO) { + printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, + op.addr, op.val); + exit(1); + } +} + +static void write_mchbar8(u32 addr, u8 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 8 || op.addr != addr || op.val != val + || op.type != OPCODE_MCHBAR) { + printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, + op.addr, op.val); + exit(1); + } +} + +static u32 read_mchbar32(u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (!op.is_in || op.data_width != 32 || op.addr != addr + || op.type != OPCODE_MCHBAR) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u32 read_mchbar32_bypass(u32 addr) +{ + return read_mchbar32(addr); +} + +static u32 read_acpi32(u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (!op.is_in || op.data_width != 32 || op.addr != addr + || op.type != ACPI) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u16 read_mchbar16(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 16 || op.addr != addr + || op.type != OPCODE_MCHBAR) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u16 read_tco16(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 16 || op.addr != addr + || op.type != TCO) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u16 read_acpi16(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 16 || op.addr != addr + || op.type != ACPI) { + printf("Bad %d: %x, 16 vs %x, %d\n", __LINE__, addr, op.addr, + op.data_width); + exit(1); + } + return op.val; +} + +static u8 read_mchbar8(u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (!op.is_in || op.data_width != 8 || op.addr != addr + || op.type != OPCODE_MCHBAR) { + printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr); + exit(1); + } + return op.val; +} + +static u8 read_tco8(u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (!op.is_in || op.data_width != 8 || op.addr != addr + || op.type != TCO) { + printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr); + exit(1); + } + return op.val; +} + +static u32 read32(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 32 || op.addr != addr + || op.type != MEM) { + printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr); + exit(1); + } + return op.val; +} + +static u64 read64(u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (!op.is_in || op.data_width != 64 || op.addr != addr + || op.type != MEM) { + printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr); + exit(1); + } + return op.val; +} + +static void clflush(u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + + if (op.addr != addr || op.type != CLFLUSH) { + printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr); + exit(1); + } +} + +static void read128(u32 addr, u64 * out) +{ + out[0] = read64(addr); + out[1] = read64(addr + 8); +} + +static u16 read16(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 16 || op.addr != addr + || op.type != MEM) { + printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr); + exit(1); + } + return op.val; +} + +static u8 read8(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 8 || op.addr != addr + || op.type != MEM) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u8 inb(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 8 || op.addr != addr + || op.type != PCIO) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static void outb(u8 val, u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCIO + || op.val != val) { + printf("Bad %d: %x, %x, 8, %d, 0 vs %x, %llx, %d, %d, %d\n", + __LINE__, addr, val, PCIO, op.addr, op.val, + op.data_width, op.type, op.is_in); + printf("%x, %llx, %d\n", val, op.val, op.val != val); + exit(1); + } +} + +static void outw(u16 val, u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 16 || op.addr != addr + || op.type != PCIO || op.val != val) { + printf("Bad %d: %x, %x vs %x, %llx\n", __LINE__, addr, val, + op.addr, op.val); + exit(1); + } +} + +static void outl(u32 val, u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 32 || op.addr != addr + || op.type != PCIO || op.val != val) { + printf("Bad %d\n", __LINE__); + exit(1); + } +} + +static u32 inl(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 32 || op.addr != addr + || op.type != PCIO) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u16 inw(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 16 || op.addr != addr + || op.type != PCIO) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static void pci_mm_write8(int bus, int dev, int func, u32 addr, u8 val) +{ + struct opcode op; + if (bus == 0xff) { + write8(DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | + (func << 12) | addr, val); + return; + } + + fetch_opcode(&op); + if (op.is_in || op.data_width != 8 || op.addr != addr + || op.type != PCIMM || op.dev != dev || op.func != func + || op.bus != bus || op.val != val) { + printf("Bad %d\n", __LINE__); + exit(1); + } +} + +static void pci_write8(int bus, int dev, int func, u32 addr, u8 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCI + || op.dev != dev || op.func != func || op.bus != bus + || op.val != val) { + printf("Bad %d\n", __LINE__); + exit(1); + } +} + +static void pci_write16(int bus, int dev, int func, u32 addr, u16 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 16 || op.addr != addr || op.type != PCI + || op.dev != dev || op.func != func || op.bus != bus + || op.val != val) { + printf("Bad %d\n", __LINE__); + exit(1); + } +} + +static void pci_mm_write16(int bus, int dev, int func, u32 addr, u16 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.data_width != 16 || op.addr != addr + || op.type != PCIMM || op.dev != dev || op.func != func + || op.bus != bus || op.val != val) { + printf("Bad %d\n", __LINE__); + exit(1); + } +} + +static void pci_mm_write32(int bus, int dev, int func, u32 addr, u32 val) +{ + struct opcode op; + if (bus == 0xff) { + write32(DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | + (func << 12) | addr, val); + return; + } + + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + + if (op.is_in || op.data_width != 32 || op.addr != addr + || op.type != PCIMM || op.dev != dev || op.func != func + || op.bus != bus || op.val != val) { + printf("Bad %d\n", __LINE__); + exit(1); + } +} + +static void pci_write32(int bus, int dev, int func, u32 addr, u32 val) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (op.is_in || op.data_width != 32 || op.addr != addr || op.type != PCI + || op.dev != dev || op.func != func || op.bus != bus + || op.val != val) { + printf("Bad %d\n", __LINE__); + exit(1); + } +} + +static u8 pci_read8(int bus, int dev, int func, u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 8 || op.addr != addr || op.type != PCI + || op.dev != dev || op.func != func || op.bus != bus) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u8 nvram_read(u8 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.addr != addr || op.type != NVRAM) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static void nvram_write(u8 addr, u8 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.addr != addr || op.type != NVRAM || op.val != val) { + printf("Bad %d\n", __LINE__); + exit(1); + } +} + +static u8 pci_mm_read8(int bus, int dev, int func, u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 8 || op.addr != addr + || op.type != PCIMM || op.dev != op.dev || op.func != op.func + || op.bus != op.bus) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u16 pci_mm_read16(int bus, int dev, int func, u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (!op.is_in || op.data_width != 16 || op.addr != addr + || op.type != PCIMM || op.dev != dev || op.func != func + || op.bus != bus) { + printf("Bad %d: %x vs %x\n", __LINE__, addr, op.addr); + exit(1); + } + return op.val; +} + +static u16 pci_read16(int bus, int dev, int func, u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.data_width != 16 || op.addr != addr + || op.type != PCI || op.dev != op.dev || op.func != op.func + || op.bus != op.bus) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u32 pci_mm_read32(int bus, int dev, int func, u32 addr) +{ + struct opcode op; + + if (bus == 0xff) + return read32(DEFAULT_PCIEXBAR | (bus << 20) | (dev << 15) | + (func << 12) | addr); + + fetch_opcode(&op); + if (!op.is_in || op.data_width != 32 || op.addr != addr + || op.type != PCIMM || op.dev != op.dev || op.func != op.func + || op.bus != op.bus) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u32 pci_read32(int bus, int dev, int func, u32 addr) +{ + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (!op.is_in || op.data_width != 32 || op.addr != addr + || op.type != PCI || op.dev != op.dev || op.func != op.func + || op.bus != op.bus) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +struct cpuid_result { + u32 eax, ebx; +}; + +struct cpuid_result cpuid_ext(u32 eax, u32 ecx) +{ + struct cpuid_result ret; + struct opcode op; + if (!fetch_opcode(&op)) { + printf("EOF\n"); + exit(1); + } + if (op.addr != eax || op.type != CPUID || op.ecx != ecx) { + printf("Bad %d\n", __LINE__); + exit(1); + } + ret.eax = op.val; + ret.ebx = op.val >> 32; + return ret; +} + +static u64 my_read_msr(u32 addr) +{ + struct opcode op; + fetch_opcode(&op); + if (!op.is_in || op.addr != addr || op.type != MSR) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static u64 my_write_msr(u32 addr, u64 val) +{ + struct opcode op; + fetch_opcode(&op); + if (op.is_in || op.addr != addr || op.type != MSR || op.val != val) { + printf("Bad %d\n", __LINE__); + exit(1); + } + return op.val; +} + +static void die(const char *msg) +{ + printf("%s\n", msg); + exit(1); +} + +static void intel_early_me_init(void) +{ +} + +static unsigned intel_early_me_uma_size(void) +{ + u32 t; + t = pci_mm_read32(HECIDEV, 0x44); + if (t & 0x10000) + return t & 0x3F; + return 0; +} + +static u8 read_mchbar8_bypass(u32 addr) +{ + return read_mchbar8(addr); +} + +#define printk(condition, fmt, args...) printf(fmt, ## args) + +#define udelay(x) + +#if 1 +static const struct ram_training *get_cached_training(void) +{ + return NULL; +#if 0 + static const struct ram_training ret = { +#if 1 + .lane_timings = { + { + { + { + {5, 5, 3, 4, 4, 3, 4, 4, 21}, + {5, 4, 2, 5, 4, 3, 4, 4, 21} + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + { + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + }, + { + { + { + {0x6e, 0x64, 0x7b, 0x56, 0xbd, 0xa0, 0xae, + 0xad, 0x100}, + {0x6e, 0x67, 0x7a, 0x54, 0xbd, 0x9f, 0xac, + 0xac, 0x100} + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + { + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + }, + { + { + { + {0x59, 0x55, 0x6d, 0x44, 0xa3, 0x76, 0x90, + 0x81, 0x80}, + {0x58, 0x51, 0x6b, 0x41, 0xa1, 0x75, 0x8e, + 0x7f, 0x80}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + { + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + }, + { + { + { + {0x78, 0x74, 0x8b, 0x64, 0xc1, 0x94, 0xaf, + 0x9d, 0x80}, + {0x76, 0x6e, 0x88, 0x60, 0xbe, 0x93, 0xae, + 0x9d, 0x80}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + { + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + } + }, + .reg_178 = 0x42, + .reg_10b = 1, + .v775 = {19, 35}, + .v777 = { + { + { + { + {0x01, 0x25}, + {0x01, 0x25}, + {0x01, 0x21}, + {0x02, 0x22}, + {0x00, 0x23}, + {0x00, 0x21}, + {0x01, 0x22}, + {0x01, 0x22}, + {0x00, 0x00} + }, + { + {0x01, 0x24}, + {0x02, 0x23}, + {0x01, 0x20}, + {0x01, 0x24}, + {0x00, 0x22}, + {0x01, 0x21}, + {0x01, 0x21}, + {0x02, 0x21}, + {0x00, 0x00} + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + } + }, + { + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + } + } + }, + { + { + { + {0x00, 0x25}, + {0x01, 0x24}, + {0x01, 0x20}, + {0x01, 0x22}, + {0x00, 0x22}, + {0x00, 0x21}, + {0x01, 0x23}, + {0x00, 0x22}, + {0x00, 0x00} + }, + { + {0x00, 0x26}, + {0x01, 0x22}, + {0x01, 0x20}, + {0x01, 0x24}, + {0x00, 0x23}, + {0x00, 0x21}, + {0x01, 0x22}, + {0x01, 0x22}, + {0x00, 0x00} + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + } + }, + { + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + } + } + } + }, + .v1065 = { + { + {0x9c, 0x92, 0xab, 0x85, 0xec, 0xd0, 0xdd, 0xdc, + 0x00}, + {0x9c, 0x96, 0xab, 0x82, 0xec, 0xcf, 0xdb, 0xdb, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + }, + { + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} + } + }, + .v1209 = { + { + {0x59, 0x55, 0x6d, 0x44, 0xa3, 0x76, 0x90, 0x81, + 0x00}, + {0x58, 0x51, 0x6b, 0x41, 0xa1, 0x75, 0x8e, 0x7f, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + } + }, + .v1353 = { + { + { + {0x5d, 0x93}, + {0x59, 0x90}, + {0x70, 0xa6}, + {0x49, 0x7f}, + {0xa5, 0xdd}, + {0x79, 0xb0}, + {0x94, 0xca}, + {0x83, 0xb8}, + {0x00, 0x00}, + }, + { + {0x5c, 0x91}, + {0x53, 0x89}, + {0x6d, 0xa4}, + {0x45, 0x7c}, + {0xa3, 0xd9}, + {0x77, 0xaf}, + {0x94, 0xc9}, + {0x82, 0xb8}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + } + }, + { + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + }, + { + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + {0x00, 0x00}, + } + } + }, +#else + .lane_timings = { + { + { + { + {5, 5, 3, 5, 4, 4, 5, 3, 21}, + {6, 5, 4, 4, 4, 3, 4, 4, 21} + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + { + { + {3, 4, 5, 3, 2, 4, 4, 4, 21}, + {3, 3, 5, 4, 2, 5, 3, 4, 21}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + }, + { + { + { + {0x6f, 0x66, 0x82, 0x58, 0xc5, 0xa6, 0xb4, + 0xb1, 0x100}, + {0x70, 0x67, 0x84, 0x59, 0xc5, 0xa3, 0xb4, + 0xb2, 0x100} + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + { + { + {0x91, 0x87, 0x98, 0x76, 0xdc, 0xb7, 0xcf, + 0xc5, 0x100}, + {0x92, 0x8d, 0x9b, 0x76, 0xde, 0xb9, 0xce, + 0xc6, 0x100}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + }, + { + { + { + {0x5f, 0x5b, 0x74, 0x4a, 0xa9, 0x7c, 0x95, + 0x85, 0x80}, + {0x5d, 0x59, 0x72, 0x49, 0xa8, 0x7a, 0x96, + 0x85, 0x80}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + { + { + {0x5b, 0x53, 0x6c, 0x49, 0xa8, 0x7a, 0x92, + 0x84, 0x80}, + {0x5b, 0x51, 0x6c, 0x48, 0xa7, 0x79, 0x91, + 0x82, 0x80}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + }, + { + { + { + {0x7e, 0x7a, 0x92, 0x6a, 0xc7, 0x9b, 0xb6, + 0xa4, 0x80}, + {0x7d, 0x77, 0x8f, 0x69, 0xc6, 0x98, 0xb6, + 0xa4, 0x80}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + { + { + {0x78, 0x6f, 0x89, 0x65, 0xc4, 0x97, 0xaf, + 0x9f, 0x80}, + {0x78, 0x6b, 0x89, 0x64, 0xc2, 0x96, 0xae, + 0x9d, 0x80}, + }, + { + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, 0}, + } + }, + } + }, + .reg_178 = 0, + .reg_10b = 1, +#endif + }; + return &ret; +#endif +} +#endif + +static void pre_raminit_3(int x2ca8) +{ + u8 t; + int i; + + gav(t = nvram_read(0x33)); + if (x2ca8 == 0) { + nvram_write(0x33, t & ~0x40); + gav(read32(DEFAULT_RCBA | 0x3598)); + write32(DEFAULT_RCBA | 0x3598, 0x1); + pci_write16(0, 0x1d, 0x0, 0x20, 0x2000); + gav(pci_read8(0, 0x1d, 0x0, 0x4)); // = 0xff + pci_write8(0, 0x1d, 0x0, 0x4, 0xff); + pci_write16(0, 0x1d, 0x1, 0x20, 0x2020); + gav(pci_read8(0, 0x1d, 0x1, 0x4)); // = 0xff + pci_write8(0, 0x1d, 0x1, 0x4, 0xff); + pci_write16(0, 0x1d, 0x2, 0x20, 0x2040); + gav(pci_read8(0, 0x1d, 0x2, 0x4)); // = 0xff + pci_write8(0, 0x1d, 0x2, 0x4, 0xff); + pci_write16(0, 0x1d, 0x3, 0x20, 0x2060); + gav(pci_read8(0, 0x1d, 0x3, 0x4)); // = 0xff + pci_write8(0, 0x1d, 0x3, 0x4, 0xff); + pci_write16(0, 0x1a, 0x0, 0x20, 0x2080); + gav(pci_read8(0, 0x1a, 0x0, 0x4)); // = 0xff + pci_write8(0, 0x1a, 0x0, 0x4, 0xff); + pci_write16(0, 0x1a, 0x1, 0x20, 0x20a0); + gav(pci_read8(0, 0x1a, 0x1, 0x4)); // = 0xff + pci_write8(0, 0x1a, 0x1, 0x4, 0xff); + pci_write16(0, 0x1a, 0x2, 0x20, 0x20e0); + gav(pci_read8(0, 0x1a, 0x2, 0x4)); // = 0xff + pci_write8(0, 0x1a, 0x2, 0x4, 0xff); + for (i = 0; i < 15; i++) { + gav(inw(0x2010)); // = 0xff + gav(inw(0x2012)); // = 0xff + gav(inw(0x2030)); // = 0xff + gav(inw(0x2032)); // = 0xff + gav(inw(0x2050)); // = 0xff + gav(inw(0x2052)); // = 0xff + gav(inw(0x2070)); // = 0xff + gav(inw(0x2072)); // = 0xff + gav(inw(0x2090)); // = 0xff + gav(inw(0x2092)); // = 0xff + gav(inw(0x20b0)); // = 0xff + gav(inw(0x20b2)); // = 0xff + gav(inw(0x20f0)); // = 0xff + gav(inw(0x20f2)); // = 0xff + if (i != 14) + pm_wait(0x400); /* <10 */ + } + pci_write16(0, 0x1d, 0x0, 0x20, 0x0); + gav(pci_read8(0, 0x1d, 0x0, 0x4)); // = 0xff + pci_write8(0, 0x1d, 0x0, 0x4, 0xfe); + pci_write16(0, 0x1d, 0x1, 0x20, 0x0); + gav(pci_read8(0, 0x1d, 0x1, 0x4)); // = 0xff + pci_write8(0, 0x1d, 0x1, 0x4, 0xfe); + pci_write16(0, 0x1d, 0x2, 0x20, 0x0); + gav(pci_read8(0, 0x1d, 0x2, 0x4)); // = 0xff + pci_write8(0, 0x1d, 0x2, 0x4, 0xfe); + pci_write16(0, 0x1d, 0x3, 0x20, 0x0); + gav(pci_read8(0, 0x1d, 0x3, 0x4)); // = 0xff + pci_write8(0, 0x1d, 0x3, 0x4, 0xfe); + pci_write16(0, 0x1a, 0x0, 0x20, 0x0); + gav(pci_read8(0, 0x1a, 0x0, 0x4)); // = 0xff + pci_write8(0, 0x1a, 0x0, 0x4, 0xfe); + pci_write16(0, 0x1a, 0x1, 0x20, 0x0); + gav(pci_read8(0, 0x1a, 0x1, 0x4)); // = 0xff + pci_write8(0, 0x1a, 0x1, 0x4, 0xfe); + pci_write16(0, 0x1a, 0x2, 0x20, 0x0); + gav(pci_read8(0, 0x1a, 0x2, 0x4)); // = 0xff + pci_write8(0, 0x1a, 0x2, 0x4, 0xfe); + write32(DEFAULT_RCBA | 0x3598, 0x0); + } +} + +static void pm_wait(u16 us) +{ + u32 base = read_acpi32(8); + u32 ticks = (us * 358) / 100; + while (((read_acpi32(8) - base) & 0xffffff) < ticks) ; +} + +static void pre_raminit1(void) +{ + u16 si; + + outb(0x0, 0x62); + + unsigned number_cores; + struct cpuid_result result; + unsigned threads_per_package, threads_per_core; + + /* Logical processors (threads) per core */ + result = cpuid_ext(0xb, 0); + threads_per_core = result.ebx & 0xffff; + + /* Logical processors (threads) per package */ + result = cpuid_ext(0xb, 1); + threads_per_package = result.ebx & 0xffff; + + if (threads_per_package == 0 || threads_per_core == 0 + || threads_per_package % threads_per_core) + number_cores = 1; + else + number_cores = threads_per_package / threads_per_core; + + u8 al = nvram_read(0x4c); + if (number_cores <= 1) + si = 0; + else if (!(al & 1)) + si = 1; + else if (number_cores <= 2) + si = 0; + else if (!(al & 2)) + si = 2; + else + si = 0; + if (!(nvram_read(0x55) & 2)) + si |= 0x100; + /* bit 0 = disable multicore, + bit 1 = disable quadcore, + bit 8 = disable hyperthreading. */ + pci_write32(QUICKPATH_BUS, 0x0, 0x0, 0x80, + (pci_read32(0xff, 0x0, 0x0, 0x80) & 0xfffffefc) | 0x10000 | + si); + + outb(0x1, 0x62); + outb(0x4, 0x62); + pci_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1); + gav(read32(DEFAULT_RCBA | 0x3410)); + write32(DEFAULT_RCBA | 0x3410, 0xc61); + gav(read32(DEFAULT_RCBA | 0x3410)); + pci_write32(SOUTHBRIDGE, PMBASE, 0x400); + pci_write8(SOUTHBRIDGE, ACPI_CNTL, 0x80); + + u16 t4041 = read_tco16(0x8); + gav(t4041); + write_tco16(0x8, t4041); + + pci_write32(SOUTHBRIDGE, 0xd0, 0x0); + + pci_write16(SOUTHBRIDGE, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN); + + u32 t4046 = pci_read32(SOUTHBRIDGE, 0xdc); + gav(t4046); + pci_write32(SOUTHBRIDGE, BIOS_CNTL, t4046); + pci_write32(QUICKPATH_BUS, 0x0, 0x1, 0x50, DEFAULT_PCIEXBAR | 1); + pci_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1); + gav(read32(DEFAULT_RCBA | 0x3410)); + write32(DEFAULT_RCBA | 0x3410, 0xc61); + + pci_write32(SOUTHBRIDGE, LPC_GEN1_DEC, 0x7c1601); + pci_write32(SOUTHBRIDGE, LPC_GEN3_DEC, 0x1c1681); + outb(0x2, 0x62); + + my_write_msr(0x79, 0xffec1410); + //Unrecognised: [ffff000:fc22] 00c0.00c1 Microcode Update: ERROR: Cannot fake write in a post-hook. + + //Unrecognised: [ffff000:fb6a] 00c8.00c9 CPUID: eax: 00000006; ecx: 0000008b => 00000005.00000002.00000001.00000000 + + { + u8 reg8; + struct cpuid_result result; + result = cpuid_ext(0x6, 0x8b); + if (!(result.eax & 0x2)) { + reg8 = ((my_read_msr(MSR_FSB_CLOCK_VCC) & 0xff00) >> 8) + 1; + my_write_msr(IA32_PERF_CTL, + (my_read_msr(IA32_PERF_CTL) & ~0xffULL) | reg8); + my_write_msr(MSR_IA32_MISC_ENABLES, + (my_read_msr(MSR_IA32_MISC_ENABLES) & + ~0x0000004000000000ULL) | 0x10000); + } + + reg8 = ((my_read_msr(MSR_FSB_CLOCK_VCC) & 0xff00) >> 8); + my_write_msr(IA32_PERF_CTL, (my_read_msr(IA32_PERF_CTL) & ~0xffULL) | reg8); + my_write_msr(MSR_IA32_MISC_ENABLES, my_read_msr(MSR_IA32_MISC_ENABLES) | 0x10000); + my_write_msr(0x1f1, my_read_msr(0x1f1) | 1); + } + + outb(0x5, 0x62); + + /*Unrecognised: [ffff000:fc9f] 00ed.00ee LAPIC: [00000300] <= 000c4500 + + Unrecognised: [ffff000:fc9f] 00ed.00ef LAPIC: [00000300] => 000c0500 + */ + outb(0x3, 0x62); + + outb(0x0, 0x62); + outb(0x2, 0x62); + outb(0x2c, 0x62); + outb(0x12, 0x62); + outb(0x30, 0x62); + /*Unrecognised: addr ff7ff7da val ff7ff856 */ + + outb(0x13, 0x62); + outb(0x28, 0x62); + outb(0x29, 0x62); + outb(0x17, 0x62); + outb(0x27, 0x62); + outb(0x4a, 0x62); + /*Unrecognised: addr ff7ff7da val ff7ff856 */ + + gav(pci_mm_read16(SOUTHBRIDGE, PMBASE)); // = 0x1001 + + outb(0x11, 0x62); + outb(0x40, 0x62); + + pci_write32(NORTHBRIDGE, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1); + + pci_write32(0, 0x1f, 0x3, SMB_BASE, SMBUS_IO_BASE); + pci_write32(0, 0x1f, 0x3, HOSTC, 0x1); + gav(pci_read16(0, 0x1f, 0x3, 0x4)); // = 0x1 + pci_write16(0, 0x1f, 0x3, 0x4, 0x1); + + pci_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1); + pci_mm_write32(NORTHBRIDGE, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1); + pci_mm_write32(NORTHBRIDGE, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1); + gav(pci_mm_read8(HECIDEV, PCI_VENDOR_ID)); // = 0x86 + pci_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1); + gav(pci_read32(SOUTHBRIDGE, PMBASE)); // = 0x1001 + pci_write32(SOUTHBRIDGE, PMBASE, 0x1001); + gav(pci_read8(SOUTHBRIDGE, ACPI_CNTL)); // = 0x80 + pci_write8(SOUTHBRIDGE, ACPI_CNTL, 0x80); + gav(pci_read8(SOUTHBRIDGE, 0xa6)); // = 0x2 + pci_write8(SOUTHBRIDGE, 0xa6, 0x2); + gav(pci_read32(SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1 + pci_write32(SOUTHBRIDGE, GPIOBASE, DEFAULT_GPIOBASE | 1); + gav(pci_read8(SOUTHBRIDGE, GPIO_CNTL)); // = 0x10 + pci_write8(SOUTHBRIDGE, GPIO_CNTL, 0x10); + gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6 + gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6 + gav(read32(DEFAULT_RCBA | 0x3598)); + gav(pci_read32(0, 0x1d, 0x0, 0xfc)); // = 0x20191708 + pci_write32(0, 0x1d, 0x0, 0xfc, 0x20191708); + gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6 + gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6 + gav(pci_read8(0, 0x1d, 0x0, 0x88)); // = 0xa0 + pci_write8(0, 0x1d, 0x0, 0x88, 0xa0); + gav(pci_read32(0, 0x1a, 0x0, 0xfc)); // = 0x20191708 + pci_write32(0, 0x1a, 0x0, 0xfc, 0x20191708); + gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6 + gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6 + gav(pci_read8(0, 0x1a, 0x0, 0x88)); // = 0xa0 + pci_write8(0, 0x1a, 0x0, 0x88, 0xa0); + write8(DEFAULT_RCBA | 0x14, 0x11); + write16(DEFAULT_RCBA | 0x50, 0x7654); + enable_hpet(); + u32 t4143 = read32(0xfed00010); + gav(t4143); + write32(0xfed00010, t4143 | 1); + + + gav(read8(DEFAULT_RCBA | 0x3428)); + write8(DEFAULT_RCBA | 0x3428, 0x1d); + pci_mm_write32(0, 0x1f, 0x6, 0x40, 0x40000000); + pci_mm_write32(0, 0x1f, 0x6, 0x44, 0x0); + gav(pci_mm_read32(0, 0x1f, 0x6, 0x40)); // = 0x40000004 + pci_mm_write32(0, 0x1f, 0x6, 0x40, 0x40000005); + u16 t4; + t4 = read16(0x4000001a); + gav(t4); + write16(0x4000001a, (t4 & ~0xf) | 0x10f0); + gav(pci_mm_read32(0, 0x1f, 0x6, 0x40)); // = 0x40000005 + pci_mm_write32(0, 0x1f, 0x6, 0x40, 0x40000004); + pci_mm_write32(0, 0x1f, 0x6, 0x40, 0x0); + + pci_read16(SOUTHBRIDGE, PMBASE); // = 0x1001 + pci_read16(SOUTHBRIDGE, GPIOBASE); // = DEFAULT_GPIOBASE | 1 + gav(read8(DEFAULT_RCBA | 0x3414)); + gav(read_acpi16(0x0)); + + u16 pm1cnt; + gav(pm1cnt = read_acpi16(0x4)); + s3resume = ((pm1cnt >> 10) & 7) == 5; + if (s3resume) { + u8 ra2, ra4; + gav(ra2 = pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_2)); // = 0xa0 + gav(ra4 = pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_3)); // = 0x9 + if (!(ra2 & 0x20)) { + s3resume = 0; + write_acpi16(0x4, 0); + } + } + + pci_mm_write8(SOUTHBRIDGE, GEN_PMCON_3, + (gav(pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_3)) & ~2) | 1); + + pci_mm_write8(0, 0x3, 0x0, 0x4, 0x0); + write16(DEFAULT_RCBA | 0x3124, 0x2321); + pci_mm_write8(SOUTHBRIDGE, 0xdc, 0x0); + + pci_mm_write32(SOUTHBRIDGE, RCBA, DEFAULT_RCBA | 1); + gav(pci_mm_read16(SOUTHBRIDGE, LPC_IO_DEC)); // = 0x10 + pci_mm_write16(SOUTHBRIDGE, LPC_IO_DEC, 0x10); + pci_mm_write16(SOUTHBRIDGE, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + GAMEH_LPC_EN | GAMEL_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | + COMA_LPC_EN); +} + +static void pre_raminit_2(void) +{ + pci_mm_write16(SOUTHBRIDGE, GPIOBASE, DEFAULT_GPIOBASE); + pci_mm_read8(SOUTHBRIDGE, GPIO_CNTL); // = 0x10 + pci_mm_write8(SOUTHBRIDGE, GPIO_CNTL, 0x10); + gav(inw(DEFAULT_GPIOBASE | 0x38)); // = 0x10 + + outl(0x1963a5ff, DEFAULT_GPIOBASE); + outl(0xffffffff, DEFAULT_GPIOBASE | 0xc); + outl(0x87bf6aff, DEFAULT_GPIOBASE | 0x4); + outl(0x0, DEFAULT_GPIOBASE | 0x18); + outl(0x120c6, DEFAULT_GPIOBASE | 0x2c); + outl(0x27706fe, DEFAULT_GPIOBASE | 0x30); + outl(0x29fffff, DEFAULT_GPIOBASE | 0x38); + outl(0x1b01f9f4, DEFAULT_GPIOBASE | 0x34); + outl(0x0, DEFAULT_GPIOBASE | 0x40); + outl(0x0, DEFAULT_GPIOBASE | 0x48); + outl(0xf00, DEFAULT_GPIOBASE | 0x44); + + pci_mm_write16(SOUTHBRIDGE, PMBASE, DEFAULT_PMBASE); + gav(pci_mm_read8(SOUTHBRIDGE, ACPI_CNTL)); // = 0x80 + pci_mm_write8(SOUTHBRIDGE, ACPI_CNTL, 0x80); + pci_mm_write32(SOUTHBRIDGE, ETR3, gav(pci_mm_read32(SOUTHBRIDGE, ETR3)) & ~ETR3_CF9GR); // OK + pci_mm_write32(SOUTHBRIDGE, LPC_GEN1_DEC, 0xc0681); + + gav(read32(DEFAULT_RCBA | 0x3400)); + write32(DEFAULT_RCBA | 0x3400, 0x1c); + gav(read32(DEFAULT_RCBA | 0x3410)); + write32(DEFAULT_RCBA | 0x3410, 0xc61); + + gav(read_tco16(0x8)); + write_tco16(0x8, 0x800); + write_tco8(0x6, gav(read_tco8(0x6)) | 0x2); + + gav(inb(0x61)); // = 0x2 + outb(0x3c, 0x61); + + enable_hpet(); + + if (pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_3) & 4) { + nvram_write(0xa, nvram_read(0xa) | 0x70); + nvram_write(0xb, nvram_read(0xb) | 0x80); + nvram_write(0xa, nvram_read(0xa) & ~0x50); + nvram_write(0xb, nvram_read(0xb) & ~0x80); + } + gav(read32(DEFAULT_RCBA | 0x3410)); + write32(DEFAULT_RCBA | 0x3410, 0xc61); + gav(pci_read8(SOUTHBRIDGE, 0x8)); // = 0x6 + gav(inl(DEFAULT_GPIOBASE)); // = 0x6 + outl(0x7963a5ff, DEFAULT_GPIOBASE); + gav(inl(DEFAULT_GPIOBASE | 0x4)); // = 0x7963a5ff + outl(0x87bf6aff, DEFAULT_GPIOBASE | 0x4); + outl(gav(inl(DEFAULT_GPIOBASE | 0xc)) | 0x40000000, + DEFAULT_GPIOBASE | 0xc); + gav(inl(DEFAULT_GPIOBASE | 0x60)); // = 0xfffbfffb + outl(0x41000000, DEFAULT_GPIOBASE | 0x60); + pci_write32(SOUTHBRIDGE, LPC_GEN3_DEC, 0x1c1681); + pci_write32(SOUTHBRIDGE, LPC_GEN2_DEC, 0xc15e1); + pci_write32(SOUTHBRIDGE, LPC_GEN1_DEC, 0x7c1601); + gav(inl(DEFAULT_GPIOBASE | 0xc)); // = 0x7c1601 + outb(0x15, 0x62); + outb(0x16, 0x62); + + + gav(pci_read32(NORTHBRIDGE, D0F0_MCHBAR_LO)); // = DEFAULT_MCHBAR | 1 +} + +static void enable_hpet(void) +{ +#if REAL + u32 reg32; + + /* Move HPET to default address 0xfed00000 and enable it */ + reg32 = RCBA32(HPTC); + reg32 |= (1 << 7); // HPET Address Enable + reg32 &= ~(3 << 0); + RCBA32(HPTC) = reg32; +#else + write32(DEFAULT_RCBA | HPTC, 0x80); +#endif +} + +static void pre_raminit_4a(void) +{ +#if !REAL + int i; + + outb(0x55, 0x62); + + outb(0x32, 0x62); + /*Unrecognised: addr ff7ff7da val ff7ff856 */ + + gav(pci_read32(0, 0x1f, 0x3, 0x0)); // = 0x3b308086 + pci_write32(0, 0x1f, 0x3, 0x20, 0x1100); + gav(pci_read8(0, 0x1f, 0x3, 0x4)); // = 0x1 + pci_write8(0, 0x1f, 0x3, 0x4, 0x1); + gav(pci_read8(0, 0x1f, 0x3, 0x40)); // = 0x1 + pci_write8(0, 0x1f, 0x3, 0x40, 0x9); + gav(pci_read8(0, 0x1f, 0x3, 0x40)); // = 0x1 + pci_write8(0, 0x1f, 0x3, 0x40, 0x1); + + outb(0x4f, 0x62); + outb(0x50, 0x62); + /*Unrecognised: addr ff7ff7da val ff7ff856 */ + + gav(pci_read8(NORTHBRIDGE, D0F0_CAPID0 + 8)); // = 0x88 + my_read_msr(0x17); // !!! + /*Unrecognised: [0000:fffaf715] 1a183.1a184 Microcode Update: ERROR: Cannot fake write in a post-hook. */ + + my_read_msr(0x17); // !!! + /*Unrecognised: [0000:fffaf715] 1a25d.1a25e Microcode Update: ERROR: Cannot fake write in a post-hook. */ + + outb(0x48, 0x62); + if (x2ca8 != 0) { + outb(0x42, 0x15ec); + gav(inb(0x15ee)); // = 0x42 + } +#endif + u16 t3; + + if (x2ca8 == 0) { + gav(t3 = inw(DEFAULT_GPIOBASE | 0x38)); + outw(t3 & ~0x400, DEFAULT_GPIOBASE | 0x38); + gav(smbus_read_byte(0x5c, 0x06)); + smbus_write_byte(0x5c, 0x06, 0x8f); + +#if !REAL + for (i = 0; i < 5; i++) + pm_wait(0x3e8); +#endif + + gav(smbus_read_byte(0x5c, 0x07)); + smbus_write_byte(0x5c, 0x07, 0x8f); + +#if !REAL + for (i = 0; i < 5; i++) + pm_wait(0x3e8); +#endif + gav(pci_mm_read16(SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1 + outw(t3 | 0x400, DEFAULT_GPIOBASE | 0x38); +#if !REAL + outb(0x42, 0x15ec); + gav(inb(0x15ee)); // = 0x42 + gav(pci_mm_read16(SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1 +#endif + } + + gav(t3 = inw(DEFAULT_GPIOBASE | 0x38)); + outw(t3 & ~0x400, DEFAULT_GPIOBASE | 0x38); + + gav(smbus_read_byte(0x57, 0x55)); + gav(pci_mm_read16(SOUTHBRIDGE, GPIOBASE)); // = DEFAULT_GPIOBASE | 1 + outw(t3 | 0x400, DEFAULT_GPIOBASE | 0x38); + +#if !REAL + outb(0x42, 0x62); + gav(read_tco16(0x6)); + pci_mm_write32(NORTHBRIDGE, PCI_SUBSYSTEM_VENDOR_ID, 0x219317aa); + pci_mm_write32(0, 0x1, 0x0, 0x8c, 0x219417aa); + pci_mm_write32(0xff, 0, 0, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa); + pci_mm_write32(0xff, 0, 1, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa); + pci_mm_write32(0xff, 2, 0, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa); + pci_mm_write32(0xff, 2, 1, PCI_SUBSYSTEM_VENDOR_ID, 0x219617aa); + pci_mm_write32(NORTHBRIDGE, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1); + pci_mm_write32(NORTHBRIDGE, D0F0_MCHBAR_HI, 0x0); + pci_mm_write32(NORTHBRIDGE, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1); + pci_mm_write32(NORTHBRIDGE, D0F0_DMIBAR_HI, 0x0); + pci_mm_write32(NORTHBRIDGE, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); + pci_mm_write32(NORTHBRIDGE, D0F0_EPBAR_HI, 0x0); + pci_mm_read32(NORTHBRIDGE, D0F0_MCHBAR_LO); // = DEFAULT_MCHBAR | 1 + pci_mm_read32(NORTHBRIDGE, D0F0_MCHBAR_HI); // = 0x0 +#endif +} + +static void dmi_setup(void) +{ + gav(read8(DEFAULT_DMIBAR | 0x254)); + write8(DEFAULT_DMIBAR | 0x254, 0x1); + gav(pci_mm_read32(SOUTHBRIDGE, 0xec)); // = 0x2b83806 + write16(DEFAULT_DMIBAR | 0x1b8, 0x18f2); + pci_mm_write16(NORTHBRIDGE, D0F0_DEVEN, + pci_mm_read16(NORTHBRIDGE, D0F0_DEVEN) & 0xfeff); + read_mchbar16(0x48); + write_mchbar16(0x48, 0x2); + my_read_msr(0x17); + + pci_mm_read32(NORTHBRIDGE, D0F0_DMIBAR_LO); // = DEFAULT_DMIBAR | 1 + if (pci_mm_read16(0, 0x1, 0x0, 0x0) != 0xffff) { + gav(pci_mm_read16(0, 0x1, 0x0, 0xac)); + pci_mm_write32(0, 0x1, 0x0, 0x200, + pci_mm_read32(0, 0x1, 0x0, 0x200) & ~0x100); + pci_mm_write8(0, 0x1, 0x0, 0x1f8, + (pci_mm_read8(0, 0x1, 0x0, 0x1f8) & ~1) | 4); + u32 t4431 = read32(DEFAULT_DMIBAR | 0xd68); + gav(t4431); + write32(DEFAULT_DMIBAR | 0xd68, t4431 | 0x08000000); + pci_mm_write32(0, 0x1, 0x0, 0x200, + pci_mm_read32(0, 0x1, 0x0, 0x200) & ~0x00200000); + gav(pci_mm_read8(0, 0x1, 0x0, 0xd60)); // = 0x0 + gav(pci_mm_read8(0, 0x1, 0x0, 0xd60)); // = 0x0 + pci_mm_write8(0, 0x1, 0x0, 0xd60, 0x3); + gav(pci_mm_read16(0, 0x1, 0x0, 0xda8)); // = 0xbf9 + gav(pci_mm_read16(0, 0x1, 0x0, 0xda8)); // = 0xbf9 + pci_mm_write16(0, 0x1, 0x0, 0xda8, 0xf9); + pci_mm_read16(0, 0x1, 0x0, 0xda8); // = 0xf9 + pci_mm_read16(0, 0x1, 0x0, 0xda8); // = 0xf9 + pci_mm_write16(0, 0x1, 0x0, 0xda8, 0x79); + pci_mm_read8(0, 0x1, 0x0, 0xd0); // = 0x2 + pci_mm_read8(0, 0x1, 0x0, 0xd0); // = 0x2 + pci_mm_write8(0, 0x1, 0x0, 0xd0, 0x1); + pci_mm_read16(0, 0x1, 0x0, 0x224); // = 0xd + pci_mm_read32(NORTHBRIDGE, D0F0_CAPID0); // = 0x10c0009 + pci_mm_read32(NORTHBRIDGE, D0F0_CAPID0 + 4); // = 0x316126 + pci_mm_read16(0, 0x1, 0x0, 0x224); // = 0xd + pci_mm_write16(0, 0x1, 0x0, 0x224, 0x1d); + pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff + pci_mm_read16(0, 0x1, 0x0, 0x224); // = 0x1d + pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff + pci_mm_write16(0, 0x1, 0x0, 0xac, 0x4d01); + pci_mm_read16(0, 0x1, 0x0, 0x224); // = 0x1d + pci_mm_read8(0, 0x1, 0x0, 0xba); // = 0x0 + pci_mm_read16(0, 0x1, 0x0, 0x0); // = 0x8086 + pci_mm_read32(0, 0x1, 0x0, 0xc00); // = 0xffffffff + pci_mm_write32(0, 0x1, 0x0, 0xc00, 0xffffc0fc); + pci_mm_read32(0, 0x1, 0x0, 0xc04); // = 0x9600000f + pci_mm_write32(0, 0x1, 0x0, 0xc04, 0x96000000); + pci_mm_read32(0, 0x1, 0x0, 0xc04); // = 0x96000000 + pci_mm_write32(0, 0x1, 0x0, 0xc04, 0x16000000); + pci_mm_write32(0, 0x1, 0x0, 0xc08, 0x0); + } else + pci_mm_read16(0, 0x1, 0x0, 0x0); // = 0xffff + + + pci_mm_read32(NORTHBRIDGE, D0F0_DMIBAR_LO); // = DEFAULT_DMIBAR | 1 + pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff + pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff + pci_mm_write32(HECIDEV, HECIBAR, DEFAULT_HECIBAR); + pci_mm_write32(HECIDEV, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000, + DEFAULT_GPIOBASE | 0x38); + gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e + + pci_mm_write32(0, 0x2, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x215a17aa); + pci_mm_write8(NORTHBRIDGE, D0F0_DEVEN, + pci_mm_read8(NORTHBRIDGE, D0F0_DEVEN) | 2); + + pci_mm_write16(0, 0x1, 0x0, 0x224, + pci_mm_read16(0, 0x1, 0x0, 0x224) | 1); + pci_mm_write16(NORTHBRIDGE, D0F0_GGC, + pci_mm_read16(NORTHBRIDGE, D0F0_GGC) | 2); + + pci_mm_read32(NORTHBRIDGE, D0F0_MCHBAR_LO); // = DEFAULT_MCHBAR | 1 + pci_mm_read32(NORTHBRIDGE, D0F0_MCHBAR_HI); // = 0x0 + pci_mm_read32(NORTHBRIDGE, D0F0_DMIBAR_LO); // = DEFAULT_DMIBAR | 1 + pci_mm_read32(NORTHBRIDGE, D0F0_DMIBAR_HI); // = 0x0 + + const struct { + int dev, func; + } bridges[] = { { + 0x1e, 0}, { + 0x1c, 0}, { + 0x1c, 1}, { + 0x1c, 2}, { + 0x1c, 3}, { + 0x1c, 4}, { + 0x1c, 5}, { + 0x1c, 6}, { + 0x1c, 7}}; + for (i = 0; i < sizeof(bridges) / sizeof(bridges[0]); i++) { + u16 dev; + pci_mm_write32(0, bridges[i].dev, bridges[i].func, 0x18, + 0x20200); + for (dev = 0; dev < 0x20; dev++) { + u16 vendor = pci_mm_read16(2, dev, 0x0, 0x0); + if (vendor == 0xffff) + continue; + pci_mm_read16(2, dev, 0x0, 0xa); + } + pci_mm_write32(0, bridges[i].dev, bridges[i].func, 0x18, 0x0); + } + + pci_mm_read16(0, 0x1, 0x0, 0x0); // = 0x8086 + pci_mm_read8(NORTHBRIDGE, D0F0_CAPID0 + 6); // = 0x31 + pci_mm_read8(0, 0x1, 0x0, 0xba); // = 0x0 + pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff + pci_mm_read8(NORTHBRIDGE, D0F0_CAPID0 + 6); // = 0x31 + pci_mm_read8(0, 0x6, 0x0, 0xba); // = 0xff + pci_mm_read16(0, 0x1, 0x0, 0x11a); // = 0x2 + pci_mm_read16(0, 0x6, 0x0, 0x11a); // = 0xffff + pci_mm_read16(0, 0x1, 0x0, 0x0); // = 0x8086 + pci_mm_read32(0, 0x1, 0x0, 0x18); // = 0x0 + pci_mm_write32(0, 0x1, 0x0, 0x18, 0x0); + pci_mm_read16(0, 0x6, 0x0, 0x0); // = 0xffff +} + +static void pre_raminit_5(int s3resume) +{ + int i; + + for (i = 0x10; i < 0x28;) { + u32 s; + pci_mm_read32(0, 0x2, 0x0, i); // = 0xffffffff + pci_mm_read32(0, 0x2, 0x0, i); // = 0xffffffff + pci_mm_write32(0, 0x2, 0x0, i, 0x0); + pci_mm_read32(0, 0x2, 0x0, i); // = 0xffffffff + pci_mm_write32(0, 0x2, 0x0, i, 0xffffffff); + s = pci_mm_read32(0, 0x2, 0x0, i); + if (s != 0xffffffff && s != 0) { + if (s & 1) { + pci_mm_write32(0, 0x2, 0x0, i, s & 0x7); + i += 4; + } else { + pci_mm_read32(0, 0x2, 0x0, i); // = 0xffffffff + pci_mm_write32(0, 0x2, 0x0, i, s & 0xf); + i += 8; + } + } else + i += 4; + } + pci_mm_read8(0, 0x1d, 0x0, 0x80); // = 0x0 + pci_mm_write8(0, 0x1d, 0x0, 0x80, 0x1); + pci_mm_read8(0, 0x1a, 0x0, 0x80); // = 0x0 + pci_mm_write8(0, 0x1a, 0x0, 0x80, 0x1); + pci_mm_write32(HECIDEV, PCI_SUBSYSTEM_VENDOR_ID, 0x215f17aa); + pci_mm_write32(0, 0x16, 0x2, PCI_SUBSYSTEM_VENDOR_ID, 0x216117aa); + pci_mm_write32(0, 0x16, 0x3, PCI_SUBSYSTEM_VENDOR_ID, 0x216217aa); + pci_mm_write32(0, 0x1a, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x216317aa); + pci_mm_write32(0, 0x1b, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x215e17aa); + pci_mm_write32(0, 0x1c, 0x0, 0x94, 0x216417aa); + pci_mm_write32(0, 0x1c, 0x1, 0x94, 0x216417aa); + pci_mm_write32(0, 0x1c, 0x2, 0x94, 0x216417aa); + pci_mm_write32(0, 0x1c, 0x3, 0x94, 0x216417aa); + pci_mm_write32(0, 0x1c, 0x4, 0x94, 0x216417aa); + pci_mm_write32(0, 0x1d, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x216317aa); + pci_mm_write32(0, 0x1e, 0x0, 0x54, 0x216517aa); + pci_mm_write32(SOUTHBRIDGE, PCI_SUBSYSTEM_VENDOR_ID, 0x216617aa); + pci_mm_write32(0, 0x1f, 0x3, PCI_SUBSYSTEM_VENDOR_ID, 0x216717aa); + pci_mm_write32(0, 0x1f, 0x5, PCI_SUBSYSTEM_VENDOR_ID, 0x216a17aa); + pci_mm_write32(0, 0x1f, 0x6, PCI_SUBSYSTEM_VENDOR_ID, 0x219017aa); + pci_mm_read8(0, 0x1d, 0x0, 0x80); // = 0x1 + pci_mm_write8(0, 0x1d, 0x0, 0x80, 0x0); + pci_mm_read8(0, 0x1a, 0x0, 0x80); // = 0x1 + pci_mm_write8(0, 0x1a, 0x0, 0x80, 0x0); + pci_mm_write32(13, 0x0, 0x0, PCI_SUBSYSTEM_VENDOR_ID, 0x213317aa); + pci_mm_write32(13, 0x0, 0x1, PCI_SUBSYSTEM_VENDOR_ID, 0x213417aa); + pci_mm_write32(13, 0x0, 0x3, PCI_SUBSYSTEM_VENDOR_ID, 0x213617aa); + + pci_mm_write32(HECIDEV, HECIBAR, DEFAULT_HECIBAR); + pci_mm_write32(HECIDEV, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + write_acpi16(0x2, 0x0); + write_acpi32(0x28, 0x0); + write_acpi32(0x2c, 0x0); + if (!s3resume) { + gav(read_acpi32(0x4)); + gav(read_acpi32(0x20)); + gav(read_acpi32(0x34)); + write_acpi16(0x0, 0x900); + write_acpi32(0x20, 0xffff7ffe); + write_acpi32(0x34, 0x56974); + pci_mm_write8(SOUTHBRIDGE, GEN_PMCON_3, + pci_mm_read8(SOUTHBRIDGE, GEN_PMCON_3) | 2); + } + + gav(read32(DEFAULT_RCBA | 0x3410)); + + if (gav(read32(DEFAULT_RCBA | 0x3804)) & 0x4000) { + u32 v; + + write8(DEFAULT_RCBA | 0x3894, 0x6); + write8(DEFAULT_RCBA | 0x3895, 0x50); + write8(DEFAULT_RCBA | 0x3896, 0x3b); + write8(DEFAULT_RCBA | 0x3897, 0x14); + write8(DEFAULT_RCBA | 0x3898, 0x2); + write8(DEFAULT_RCBA | 0x3899, 0x3); + write8(DEFAULT_RCBA | 0x389a, 0x20); + write8(DEFAULT_RCBA | 0x389b, 0x5); + write8(DEFAULT_RCBA | 0x389c, 0x9f); + write8(DEFAULT_RCBA | 0x389d, 0x20); + write8(DEFAULT_RCBA | 0x389e, 0x1); + write8(DEFAULT_RCBA | 0x389f, 0x6); + write8(DEFAULT_RCBA | 0x3890, 0xc); + gav(read8(DEFAULT_RCBA | 0x3890)); + write32(DEFAULT_RCBA | 0x3808, 0x0); + gav(read32(DEFAULT_RCBA | 0x3808)); + write16(DEFAULT_RCBA | 0x3891, 0x4242); + gav(read16(DEFAULT_RCBA | 0x3891)); + gav(read8(DEFAULT_RCBA | 0x3890)); + write8(DEFAULT_RCBA | 0x3890, 0xc); + gav(read8(DEFAULT_RCBA | 0x3890)); + if ((gav(read32(DEFAULT_RCBA | 0x3810)) & 0x20) || WTF1) + v = 0x2005; + else + v = 0x2015; + write32(DEFAULT_RCBA | 0x38c8, v); + write32(DEFAULT_RCBA | 0x38c4, 0x800000 | v); + gav(read32(DEFAULT_RCBA | 0x38b0)); + write32(DEFAULT_RCBA | 0x38b0, 0x1000); + gav(read32(DEFAULT_RCBA | 0x38b4)); + gav(read32(DEFAULT_RCBA | 0x38b0)); + write32(DEFAULT_RCBA | 0x38b0, 0x4); + gav(read32(DEFAULT_RCBA | 0x38b4)); + write32(DEFAULT_RCBA | 0x3874, 0x1fff07d0); + } + gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0x1fff07d0 + + set_fsb_frequency (); + + outb(0x44, 0x62); + outb(0x3c, 0x62); + nvram_read(0x71); + my_read_msr (MTRRcap_MSR); + my_read_msr (MTRRphysMask_MSR (0)); + my_read_msr (MTRRphysMask_MSR (1)); + my_read_msr (MTRRphysMask_MSR (2)); + my_read_msr (MTRRphysMask_MSR (3)); + + gav(read32(DEFAULT_RCBA | 0x3410)); + write32(DEFAULT_RCBA | 0x3410, 0xc61); + + gav(read8(0xfed40000)); + pci_mm_read32(0xff, 0, 0, 0x88); + read_mchbar32(0x28); + gav(read8(0xfed30008)); +} diff --git a/src/northbridge/intel/nehalem/raminit_tables.c b/src/northbridge/intel/nehalem/raminit_tables.c new file mode 100644 index 0000000..3546061 --- /dev/null +++ b/src/northbridge/intel/nehalem/raminit_tables.c @@ -0,0 +1,1278 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* [CHANNEL][EXT_REVISON][LANE][2*SLOT+RANK][CLOCK_SPEED] */ +const u8 u8_FFFD1240[2][5][9][4][4] = { + { + { + { + {0x3b, 0x53, 0x57, 0x5c}, + {0x3b, 0x52, 0x57, 0x5c}, + {0x3b, 0x4d, 0x51, 0x54}, + {0x3b, 0x4d, 0x51, 0x54} + }, + { + {0x46, 0x63, 0x6b, 0x74}, + {0x46, 0x62, 0x6b, 0x73}, + {0x46, 0x5d, 0x65, 0x6c}, + {0x46, 0x5d, 0x65, 0x6c} + }, + { + {0x51, 0x71, 0x7e, 0x8a}, + {0x51, 0x71, 0x7d, 0x8a}, + {0x51, 0x6c, 0x77, 0x82}, + {0x51, 0x6c, 0x77, 0x82} + }, + { + {0x5c, 0x7b, 0x8a, 0x99}, + {0x5c, 0x7b, 0x89, 0x98}, + {0x5c, 0x75, 0x83, 0x90}, + {0x5c, 0x75, 0x83, 0x90} + }, + { + {0x65, 0x81, 0x91, 0xa2}, + {0x65, 0x81, 0x91, 0xa1}, + {0x65, 0x7c, 0x8b, 0x9a}, + {0x65, 0x7c, 0x8b, 0x9a} + }, + { + {0x70, 0x8b, 0x9e, 0xb1}, + {0x70, 0x8b, 0x9d, 0xb0}, + {0x70, 0x86, 0x97, 0xa9}, + {0x70, 0x86, 0x97, 0xa9} + }, + { + {0x73, 0x8f, 0xa3, 0xb7}, + {0x73, 0x8f, 0xa3, 0xb6}, + {0x73, 0x8a, 0x9d, 0xaf}, + {0x73, 0x8a, 0x9d, 0xaf}, + }, + { + {0x78, 0x99, 0xaf, 0xc5}, + {0x78, 0x98, 0xae, 0xc4}, + {0x78, 0x93, 0xa8, 0xbd}, + {0x78, 0x93, 0xa8, 0xbd}, + }, + { + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94} + }, + }, + { + { + {0x3b, 0x53, 0x57, 0x5c}, + {0x3b, 0x52, 0x57, 0x5c}, + {0x3b, 0x4d, 0x51, 0x54}, + {0x3b, 0x4d, 0x51, 0x54} + }, + { + {0x46, 0x63, 0x6b, 0x74}, + {0x46, 0x62, 0x6b, 0x73}, + {0x46, 0x5d, 0x65, 0x6c}, + {0x46, 0x5d, 0x65, 0x6c} + }, + { + {0x51, 0x71, 0x7e, 0x8a}, + {0x51, 0x71, 0x7d, 0x8a}, + {0x51, 0x6c, 0x77, 0x82}, + {0x51, 0x6c, 0x77, 0x82} + }, + { + {0x5c, 0x7b, 0x8a, 0x99}, + {0x5c, 0x7b, 0x89, 0x98}, + {0x5c, 0x75, 0x83, 0x90}, + {0x5c, 0x75, 0x83, 0x90} + }, + { + {0x65, 0x81, 0x91, 0xa2}, + {0x65, 0x81, 0x91, 0xa1}, + {0x65, 0x7c, 0x8b, 0x9a}, + {0x65, 0x7c, 0x8b, 0x9a} + }, + { + {0x70, 0x8b, 0x9e, 0xb1}, + {0x70, 0x8b, 0x9d, 0xb0}, + {0x70, 0x86, 0x97, 0xa9}, + {0x70, 0x86, 0x97, 0xa9} + }, + { + {0x73, 0x8f, 0xa3, 0xb7}, + {0x73, 0x8f, 0xa3, 0xb6}, + {0x73, 0x8a, 0x9d, 0xaf}, + {0x73, 0x8a, 0x9d, 0xaf} + }, + { + {0x78, 0x99, 0xaf, 0xc5}, + {0x78, 0x98, 0xae, 0xc4}, + {0x78, 0x93, 0xa8, 0xbd}, + {0x78, 0x93, 0xa8, 0xbd} + }, + { + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94} + }, + }, + { + { + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e} + }, + { + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e} + }, + { + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d} + }, + { + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d} + }, + { + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92} + }, + { + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92} + }, + { + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1} + }, + { + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1} + }, + { + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94} + }, + }, + { + { + {0x55, 0x5b, 0x62, 0x61}, + {0x55, 0x5b, 0x62, 0x61}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e} + }, + { + {0x55, 0x5b, 0x62, 0x61}, + {0x55, 0x5b, 0x62, 0x61}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e} + }, + { + {0x5d, 0x67, 0x71, 0x73}, + {0x5d, 0x67, 0x71, 0x73}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d} + }, + { + {0x5d, 0x67, 0x71, 0x73}, + {0x5d, 0x67, 0x71, 0x73}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d} + }, + { + {0x6b, 0x7a, 0x88, 0x8f}, + {0x6b, 0x7a, 0x88, 0x8f}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92} + }, + { + {0x6b, 0x7a, 0x88, 0x8f}, + {0x6b, 0x7a, 0x88, 0x8f}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92} + }, + { + {0x75, 0x87, 0x98, 0xa2}, + {0x75, 0x87, 0x98, 0xa2}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1} + }, + { + {0x75, 0x87, 0x98, 0xa2}, + {0x75, 0x87, 0x98, 0xa2}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1} + }, + { + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94} + }, + }, + { + { + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e} + }, + { + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e} + }, + { + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d} + }, + { + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d} + }, + { + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92} + }, + { + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92} + }, + { + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1} + }, + { + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1} + }, + { + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94} + }, + }, + }, + { + { + { + {0x41, 0x59, 0x5f, 0x65}, + {0x41, 0x59, 0x5f, 0x65}, + {0x41, 0x53, 0x58, 0x5d}, + {0x41, 0x53, 0x58, 0x5d} + }, + { + {0x4b, 0x69, 0x73, 0x7d}, + {0x4b, 0x69, 0x73, 0x7d}, + {0x4b, 0x63, 0x6c, 0x75}, + {0x4b, 0x63, 0x6c, 0x75}, + }, + { + {0x54, 0x72, 0x7f, 0x8b}, + {0x54, 0x72, 0x7f, 0x8b}, + {0x54, 0x6c, 0x78, 0x83}, + {0x54, 0x6c, 0x78, 0x83}, + }, + { + {0x61, 0x81, 0x91, 0xa2}, + {0x61, 0x81, 0x91, 0xa2}, + {0x61, 0x7b, 0x8a, 0x99}, + {0x61, 0x7b, 0x8a, 0x99}, + }, + { + {0x6a, 0x87, 0x99, 0xab}, + {0x6a, 0x87, 0x99, 0xab}, + {0x6a, 0x82, 0x92, 0xa3}, + {0x6a, 0x82, 0x92, 0xa3}, + }, + { + {0x71, 0x8b, 0x9e, 0xb1}, + {0x71, 0x8b, 0x9e, 0xb1}, + {0x71, 0x86, 0x98, 0xa9}, + {0x71, 0x86, 0x98, 0xa9}, + }, + { + {0x75, 0x95, 0xab, 0xc0}, + {0x75, 0x95, 0xab, 0xc0}, + {0x75, 0x90, 0xa4, 0xb8}, + {0x75, 0x90, 0xa4, 0xb8}, + }, + { + {0x7d, 0x9f, 0xb6, 0xce}, + {0x7d, 0x9f, 0xb6, 0xce}, + {0x7d, 0x99, 0xb0, 0xc6}, + {0x7d, 0x99, 0xb0, 0xc6}, + }, + { + {0x61, 0x7e, 0x80, 0x9f}, + {0x61, 0x7e, 0x95, 0x9f}, + {0x61, 0x7e, 0x80, 0x9f}, + {0x61, 0x7e, 0x80, 0x9f}, + }, + }, + { + { + {0x41, 0x59, 0x5f, 0x65}, + {0x41, 0x59, 0x5f, 0x65}, + {0x41, 0x53, 0x58, 0x5d}, + {0x41, 0x53, 0x58, 0x5d}, + }, + { + {0x4b, 0x69, 0x73, 0x7d}, + {0x4b, 0x69, 0x73, 0x7d}, + {0x4b, 0x63, 0x6c, 0x75}, + {0x4b, 0x63, 0x6c, 0x75}, + }, + { + {0x54, 0x72, 0x7f, 0x8b}, + {0x54, 0x72, 0x7f, 0x8b}, + {0x54, 0x6c, 0x78, 0x83}, + {0x54, 0x6c, 0x78, 0x83}, + }, + { + {0x61, 0x81, 0x91, 0xa2}, + {0x61, 0x81, 0x91, 0xa2}, + {0x61, 0x7b, 0x8a, 0x99}, + {0x61, 0x7b, 0x8a, 0x99}, + }, + { + {0x6a, 0x87, 0x99, 0xab}, + {0x6a, 0x87, 0x99, 0xab}, + {0x6a, 0x82, 0x92, 0xa3}, + {0x6a, 0x82, 0x92, 0xa3}, + }, + { + {0x71, 0x8b, 0x9e, 0xb1}, + {0x71, 0x8b, 0x9e, 0xb1}, + {0x71, 0x86, 0x98, 0xa9}, + {0x71, 0x86, 0x98, 0xa9}, + }, + { + {0x75, 0x95, 0xab, 0xc0}, + {0x75, 0x95, 0xab, 0xc0}, + {0x75, 0x90, 0xa4, 0xb8}, + {0x75, 0x90, 0xa4, 0xb8}, + }, + { + {0x7d, 0x9f, 0xb6, 0xce}, + {0x7d, 0x9f, 0xb6, 0xce}, + {0x7d, 0x99, 0xb0, 0xc6}, + {0x7d, 0x99, 0xb0, 0xc6}, + }, + { + {0x61, 0x7e, 0x80, 0x9f}, + {0x61, 0x7e, 0x80, 0x9f}, + {0x61, 0x7e, 0x80, 0x9f}, + {0x61, 0x7e, 0x80, 0x9f}, + }, + }, + { + { + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + }, + { + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + }, + { + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + }, + { + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + }, + { + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + }, + { + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + }, + { + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + }, + { + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + }, + { + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + }, + }, + { + { + {0x56, 0x5d, 0x65, 0x64}, + {0x56, 0x5d, 0x65, 0x64}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + }, + { + {0x56, 0x5d, 0x65, 0x64}, + {0x56, 0x5d, 0x65, 0x64}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + }, + { + {0x5e, 0x68, 0x72, 0x74}, + {0x5e, 0x68, 0x72, 0x74}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + }, + { + {0x5e, 0x68, 0x72, 0x74}, + {0x5e, 0x68, 0x72, 0x74}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + }, + { + {0x68, 0x76, 0x83, 0x89}, + {0x68, 0x76, 0x83, 0x89}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + }, + { + {0x68, 0x76, 0x83, 0x89}, + {0x68, 0x76, 0x83, 0x89}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + }, + { + {0x70, 0x80, 0x90, 0x98}, + {0x70, 0x80, 0x90, 0x98}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + }, + { + {0x70, 0x80, 0x90, 0x98}, + {0x70, 0x80, 0x90, 0x98}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + }, + { + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + }, + }, + { + { + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + }, + { + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + {0x57, 0x5e, 0x66, 0x6e}, + }, + { + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + }, + { + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + {0x5e, 0x69, 0x73, 0x7d}, + }, + { + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + }, + { + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + {0x69, 0x77, 0x85, 0x92}, + }, + { + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + }, + { + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + {0x70, 0x80, 0x91, 0xa1}, + }, + { + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + {0x5c, 0x79, 0x87, 0x94}, + } + } + } +}; + +const u16 u16_FFFE0EB8[2][4] = { + {0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000} +}; + +/* [CARD][LANE][CLOCK_SPEED] */ +const u16 u16_ffd1188[2][9][4] = { + { + {0xfff9, 0xfff7, 0xfff5, 0xfff2}, + {0xfff9, 0xfff7, 0xfff5, 0xfff2}, + {0xfffb, 0xfff9, 0xfff7, 0xfff6}, + {0xfffb, 0xfff9, 0xfff7, 0xfff6}, + {0xfffc, 0xfffb, 0xfffa, 0xfff8}, + {0xfffc, 0xfffb, 0xfffa, 0xfff8}, + {0xfffd, 0xfffc, 0xfffb, 0xfffa}, + {0xfffd, 0xfffc, 0xfffb, 0xfffa}, + {0x0000, 0x0000, 0x0000, 0x0000} + }, + { + {0x0001, 0x0001, 0x0001, 0x0002}, + {0xfffa, 0xfff8, 0xfff6, 0xfff4}, + {0x0001, 0x0002, 0x0002, 0x0003}, + {0xffe2, 0xffd8, 0xffce, 0xffc4}, + {0x0021, 0x002d, 0x0038, 0x0043}, + {0x0004, 0x0005, 0x0006, 0x0007}, + {0x000e, 0x0013, 0x0018, 0x001d}, + {0x0009, 0x000c, 0x000f, 0x0012}, + {0x0000, 0x0000, 0x0000, 0x0000} + } +}; + +/* [REVISION][CHANNEL][CLOCK_INDEX][?] */ +const u8 u8_FFFD1891[2][2][4][12] = { + { + { + {0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x08, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00}, + }, + { + {0x04, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x05, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x07, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x08, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, + 0x00}, + } + }, + { + { + {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x0c, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, + 0x00}, + }, + { + {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, + 0x00}, + {0x0c, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x74} + } + } +}; + +const u8 u8_FFFD17E0[2][5][4][4] = { + { + { + {0x00, 0x0c, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x23, 0x19, 0x0f, 0x05}, + {0x23, 0x19, 0x0f, 0x05}, + }, + { + {0x00, 0x0c, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x23, 0x19, 0x0f, 0x05}, + {0x23, 0x19, 0x0f, 0x05}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x44, 0x45, 0x47, 0x05}, + {0x44, 0x45, 0x47, 0x05}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x44, 0x45, 0x46, 0x44}, + {0x44, 0x45, 0x46, 0x44}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x2a, 0x24, 0x1e, 0x16}, + {0x2a, 0x24, 0x1e, 0x16}, + }, + }, + { + { + {0x00, 0x08, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x27, 0x1e, 0x16, 0x0d}, + {0x27, 0x1e, 0x16, 0x0d}, + }, + { + {0x00, 0x08, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x27, 0x1e, 0x16, 0x0d}, + {0x27, 0x1e, 0x16, 0x0d}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x44, 0x45, 0x47, 0x05}, + {0x44, 0x45, 0x47, 0x05}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x43, 0x44, 0x45, 0x43}, + {0x43, 0x44, 0x45, 0x43}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x2a, 0x24, 0x1e, 0x16}, + {0x2a, 0x24, 0x1e, 0x16}, + }, + }, +}; + +const u8 u8_FFFD0C78[2][5][4][2][2][4] = { + { + { + { + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + }, + { + { + {0x00, 0x02, 0x0d, 0x0f}, + {0x00, 0x02, 0x0d, 0x0f}, + }, + { + {0x00, 0x02, 0x0d, 0x0f}, + {0x00, 0x02, 0x0d, 0x0f}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + }, + { + { + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + }, + { + { + {0x00, 0x02, 0x0d, 0x0f}, + {0x00, 0x02, 0x0d, 0x0f}, + }, + { + {0x00, 0x02, 0x0d, 0x0f}, + {0x00, 0x02, 0x0d, 0x0f}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + }, + { + { + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + }, + { + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + }, + { + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + }, + { + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + }, + }, + { + { + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + }, + { + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + }, + { + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + }, + { + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + }, + }, + { + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + { + { + {0x04, 0x06, 0x08, 0x0a}, + {0x04, 0x06, 0x08, 0x0a}, + }, + { + {0x04, 0x06, 0x08, 0x0a}, + {0x04, 0x06, 0x08, 0x0a}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + }, + }, + { + { + { + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + }, + { + { + {0x00, 0x06, 0x0d, 0x0f}, + {0x00, 0x06, 0x0d, 0x0f}, + }, + { + {0x00, 0x06, 0x0d, 0x0f}, + {0x00, 0x06, 0x0d, 0x0f}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + }, + { + { + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + }, + { + { + {0x00, 0x06, 0x13, 0x17}, + {0x00, 0x06, 0x13, 0x17}, + }, + { + {0x00, 0x06, 0x13, 0x17}, + {0x00, 0x06, 0x13, 0x17}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + }, + { + { + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + }, + { + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + }, + { + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + }, + { + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + { + {0x04, 0x05, 0x07, 0x08}, + {0x04, 0x05, 0x07, 0x08}, + }, + }, + }, + { + { + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + }, + { + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + }, + { + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + }, + { + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + { + {0x06, 0x07, 0x09, 0x0b}, + {0x06, 0x07, 0x09, 0x0b}, + }, + }, + }, + { + { + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + { + {0x00, 0x00, 0x03, 0x04}, + {0x00, 0x00, 0x03, 0x04}, + }, + }, + { + { + {0x04, 0x06, 0x08, 0x0a}, + {0x00, 0x06, 0x0d, 0x0f}, + }, + { + {0x00, 0x06, 0x0d, 0x0f}, + {0x00, 0x06, 0x0d, 0x0f}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + { + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + { + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + }, + }, + }, + }, +}; + +const u16 u16_fffd0c68[3] = { 0x04c3, 0x064d, 0x068b }; + +const u16 u16_fffd0c70[2][2] = { + {0x06c0, 0x06c9}, + {0x06a4, 0x06ad} +}; + +const u16 u16_fffd0c50[3][2][2] = { + { + {0x04b9, 0x04af}, + {0x04a5, 0x049b} + }, + { + {0x0625, 0x062f}, + {0x0639, 0x0643}, + }, + { + {0x0663, 0x066d}, + {0x0677, 0x0681} + } +}; + +/* [CLOCK_INDEX] */ +const u16 min_cycletime[4] = { 0x09c4, 0x0753, 0x05dc, 0x0000 }; + +/* [CLOCK_INDEX] */ +const u16 min_cas_latency_time[4] = { 0x30d4, 0x2bf2, 0x2904, 0x0000 }; + +/* [CHANNEL][EXT_SILICON_REVISION][?][CLOCK_INDEX] */ +/* On other mobos may also depend on slot and rank. */ +const u8 u8_FFFD0EF8[2][5][4][4] = { + { + { + {0x00, 0x00, 0x03, 0x04,}, + {0x00, 0x02, 0x0d, 0x0f,}, + {0x00, 0x00, 0x00, 0x00,}, + {0x00, 0x00, 0x00, 0x00,}, + }, + { + {0x00, 0x00, 0x03, 0x04,}, + {0x00, 0x02, 0x0d, 0x0f,}, + {0x00, 0x00, 0x00, 0x00,}, + {0x00, 0x00, 0x00, 0x00,}, + }, + { + {0x09, 0x0c, 0x0f, 0x12,}, + {0x09, 0x0c, 0x0f, 0x12,}, + {0x09, 0x0c, 0x0f, 0x12,}, + {0x09, 0x0c, 0x0f, 0x12,}, + }, + { + {0x06, 0x08, 0x0a, 0x0c,}, + {0x06, 0x08, 0x0a, 0x0c,}, + {0x06, 0x08, 0x0a, 0x0c,}, + {0x06, 0x08, 0x0a, 0x0c,}, + }, + { + {0x00, 0x00, 0x00, 0x00,}, + {0x07, 0x0a, 0x0d, 0x10,}, + {0x04, 0x06, 0x08, 0x0a,}, + {0x04, 0x06, 0x08, 0x0a,}, + }, + }, + { + { + {0x00, 0x00, 0x03, 0x04,}, + {0x00, 0x06, 0x0d, 0x0f,}, + {0x00, 0x00, 0x00, 0x00,}, + {0x00, 0x00, 0x00, 0x00,}, + }, + { + {0x00, 0x00, 0x03, 0x04,}, + {0x00, 0x06, 0x13, 0x17,}, + {0x00, 0x00, 0x00, 0x00,}, + {0x00, 0x00, 0x00, 0x00,}, + }, + { + {0x09, 0x0c, 0x0f, 0x12,}, + {0x09, 0x0c, 0x0f, 0x12,}, + {0x09, 0x0c, 0x0f, 0x12,}, + {0x09, 0x0c, 0x0f, 0x12,}, + }, + { + {0x09, 0x0c, 0x10, 0x13,}, + {0x09, 0x0c, 0x10, 0x13,}, + {0x09, 0x0c, 0x10, 0x13,}, + {0x09, 0x0c, 0x10, 0x13,}, + }, + { + {0x00, 0x00, 0x00, 0x00,}, + {0x07, 0x0a, 0x0d, 0x10,}, + {0x04, 0x06, 0x08, 0x0a,}, + {0x04, 0x06, 0x08, 0x0a,}, + }, + }, +}; + +/* [CLOCK_SPEED] */ +const u8 u8_FFFD1218[4] = { + 0x15, 0x15, 0x15, 0x12 +}; + +const u8 reg178_min[] = { 1, 3, 4, 7 }; +const u8 reg178_max[] = { 62, 60, 59, 56 }; +const u8 reg178_step[] = { 5, 4, 3, 2 }; + +const u16 u16_ffd1178[2][4] = { + {0xfffb, 0xfffa, 0xfff8, 0xfff7}, + {0xfffb, 0xfffa, 0xfff8, 0xfff7}, +}; + +const u16 u16_fe0eb8[2][4] = { + {0x0000, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0000, 0x0000, 0x0000} +}; + +const u8 lut16[4] = { 14, 13, 14, 14 };

1 0

New patch to review for coreboot: 426d7e0 Use tsc for 2065x
by Vladimir Serbinenko 12 Nov '13

12 Nov '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4043 -gerrit commit 426d7e037791e3e2db858a649f688bbc2b3f67e2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Nov 12 21:59:10 2013 +0100 Use tsc for 2065x For nehalem raminit we need a udelay. Use common tsc framework for it. Change-Id: I360a6db1ec1ba32c92698a7d6f6968c93ead5c52 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/model_2065x/Kconfig | 3 ++- src/cpu/intel/model_2065x/Makefile.inc | 6 ++++++ src/cpu/intel/model_2065x/tsc_freq.c | 31 +++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 019309d..b0f4e65 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE select SSE2 - select UDELAY_LAPIC + select UDELAY_TSC + select TSC_CONSTANT_RATE select SMM_TSEG select HAVE_INIT_TIMER select CPU_MICROCODE_IN_CBFS diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 963fb1b..3b3fc4e 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -3,10 +3,16 @@ subdirs-y += ../../x86/name subdirs-y += ../../x86/cache subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/tsc subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode subdirs-y += ../../x86/smm + +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c + ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/cpu/intel/model_2065x/tsc_freq.c b/src/cpu/intel/model_2065x/tsc_freq.c new file mode 100644 index 0000000..7d388be --- /dev/null +++ b/src/cpu/intel/model_2065x/tsc_freq.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include "model_2065x.h" + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff); +}

1 0

Patch merged into coreboot/master: c5e947e rename status-related stuff to board_status
by gerrit＠coreboot.org 12 Nov '13

12 Nov '13

the following patch was just integrated into master: commit c5e947ef17d98722d27a67d65a84a28fd5861dbd Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Nov 11 18:43:39 2013 -0800 rename status-related stuff to board_status This just moves stuff to be more clear about the purpose of the script. Other suggestions are welcome. Change-Id: Ic6095fd4eb347daa5a03eff21b5952d2d42a6bfd Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/4038 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/4038 for details. -gerrit

1 0

Patch set updated for coreboot: aa13263 cbfs: 64-bit cleanups
by Ronald G. Minnich 12 Nov '13

12 Nov '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4037 -gerrit commit aa13263050983040fc46df9ce4bdf32a25619615 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Nov 11 10:36:28 2013 -0800 cbfs: 64-bit cleanups cbfs used u32 in a number of cases where uintptr_t was correct. This change builds for both 64-bit and 32-bit boards. Also, add a function to convert a network byte order element of the struct to a void *. Change-Id: If42c722a8a9e8d565d3827f65ed6c2cb8e90ba60 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> --- src/lib/cbfs.c | 36 ++++++++++++++++++++++++++---------- src/lib/cbmem.c | 2 +- src/lib/selfboot.c | 9 +++++---- 3 files changed, 32 insertions(+), 15 deletions(-) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 4ccc9e6..4576f7e 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -254,13 +254,27 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) #else +static void *cbfs_pointer(u64 value) +{ + void *v; + + /* there has to be a better way to do this. Do we need + * CONFIG_WORD_SIZE or something? + */ +#if (CONFIG_ARCH_X86 == 1) || (CONFIG_ARCH_ARMV7 == 1) + v = (void *)ntohl(value); +#else + v = (void *)ntohll(value); +#endif + return v; +} + void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) cbfs_get_file_content(media, name, CBFS_TYPE_STAGE); - /* this is a mess. There is no ntohll. */ - /* for now, assume compatible byte order until we solve this. */ - uint32_t entry; + + void *load, *entry; uint32_t final_size; if (stage == NULL) @@ -271,29 +285,30 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) (uint32_t) stage->load, stage->memlen, stage->entry); + load = cbfs_pointer(stage->load); final_size = cbfs_decompress(stage->compression, ((unsigned char *) stage) + sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, + load, stage->len); if (!final_size) return (void *) -1; /* Stages rely the below clearing so that the bss is initialized. */ - memset((void *)((uintptr_t)stage->load + final_size), 0, + memset((load + final_size), 0, stage->memlen - final_size); DEBUG("stage loaded.\n"); - entry = stage->entry; - // entry = ntohll(stage->entry); + entry = cbfs_pointer(stage->entry); - return (void *) entry; + return entry; } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ int cbfs_execute_stage(struct cbfs_media *media, const char *name) { + void * entry; struct cbfs_stage *stage = (struct cbfs_stage *) cbfs_get_file_content(media, name, CBFS_TYPE_STAGE); @@ -307,8 +322,9 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name) } /* FIXME: This isn't right */ - LOG("run @ %p\n", (void *) ntohl((uint32_t) stage->entry)); - return run_address((void *)(uintptr_t)ntohll(stage->entry)); + entry = cbfs_pointer(stage->entry); + LOG("run @ %p\n", entry); + return run_address(entry); } #if !CONFIG_ALT_CBFS_LOAD_PAYLOAD diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index de49816..6449b55 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -200,7 +200,7 @@ void *cbmem_add(u32 id, u64 size) cbmem_toc[0].base += size; cbmem_toc[0].size -= size; - return (void *)(u32)cbmem_toc[i].base; + return (void *)(uintptr_t)cbmem_toc[i].base; } void *cbmem_find(u32 id) diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index f69ad14..222eae2 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -305,7 +305,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) static int build_self_segment_list( struct segment *head, struct lb_memory *mem, - struct cbfs_payload *payload, u32 *entry) + struct cbfs_payload *payload, uintptr_t *entry) { struct segment *new; struct segment *ptr; @@ -332,8 +332,9 @@ static int build_self_segment_list( new->s_memsz = ntohl(segment->mem_len); new->compression = ntohl(segment->compression); - new->s_srcaddr = (u32) ((unsigned char *)first_segment) - + ntohl(segment->offset); + new->s_srcaddr = (uintptr_t) + ((unsigned char *)first_segment) + + ntohl(segment->offset); new->s_filesz = ntohl(segment->len); printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); @@ -504,7 +505,7 @@ static int load_self_segments( void *selfload(struct lb_memory *mem, struct cbfs_payload *payload) { - u32 entry=0; + uintptr_t entry = 0; struct segment head; /* Preprocess the self segments */

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New patch to review for coreboot: 36424f7 cbfstool: add aarch64 as a name
by Ronald G. Minnich 12 Nov '13

12 Nov '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4042 -gerrit commit 36424f7f368408eda313b53331f7f246f5929fb0 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Tue Nov 12 09:03:33 2013 -0800 cbfstool: add aarch64 as a name Change-Id: I1d8ee785ca4877d41d3082e1dab7471eb67aa602 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> --- util/cbfstool/cbfs.h | 1 + util/cbfstool/cbfstool.c | 2 +- util/cbfstool/common.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index 35d0670..962bbad 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -41,6 +41,7 @@ struct cbfs_header { #define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF #define CBFS_ARCHITECTURE_X86 0x00000001 #define CBFS_ARCHITECTURE_ARMV7 0x00000010 +#define CBFS_ARCHITECTURE_AARCH64 0x00000020 #define CBFS_FILE_MAGIC "LARCHIVE" diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 34002a9..6f169bb 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -582,7 +582,7 @@ static void usage(char *name) "Updates the FIT table with microcode entries\n" "\n" "ARCHes:\n" - " armv7, x86\n" + " aarch64, armv7, x86\n" "TYPEs:\n", name, name ); print_supported_filetypes(); diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index aa98696..ec3c6f6 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -154,6 +154,7 @@ static struct { uint32_t arch; const char *name; } arch_names[] = { + { CBFS_ARCHITECTURE_AARCH64, "aarch64" }, { CBFS_ARCHITECTURE_ARMV7, "armv7" }, { CBFS_ARCHITECTURE_X86, "x86" }, { CBFS_ARCHITECTURE_UNKNOWN, "unknown" }

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New patch to review for coreboot: b24c6ee Asus F2A85-M Fix S3 memory power cut-off
by Rudolf Marek 12 Nov '13

12 Nov '13

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4041 -gerrit commit b24c6eed3842af7db855f67c6d17193eedd6de86 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue Nov 12 16:46:47 2013 +0100 Asus F2A85-M Fix S3 memory power cut-off The power to memory is lost during the the suspend, activate the 3VSBSW# which switches the power during S3 suspend sequence. Change-Id: Id953313ee4400a03a2ad8ca09e39a5e0d5f92524 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/asus/f2a85-m/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 5d01bb4..031bb50 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -90,6 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sbxxx_enable_48mhzout(); it8712f_kill_watchdog(); it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + it8712f_enable_3vsbsw(); console_init(); /* turn on secondary smbus at b20 */

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Patch merged into coreboot/master: 7b4a99c AMD Hudson: Move function s3_resume_init_data to southbridge
by gerrit＠coreboot.org 12 Nov '13

12 Nov '13

the following patch was just integrated into master: commit 7b4a99c66569c74243f44ec7c09f0fd6e5f6802e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Nov 5 13:58:50 2013 +0800 AMD Hudson: Move function s3_resume_init_data to southbridge Besides the AGESA static settings, the settings in mainboard/buildOpt.c also change the final configuration. We need to make sure the settings in FchParam in resume stage are the same as they were in cold boot stage, otherwise the board can not wake up more than once. Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180. (USB keyboard doesn't work when board wakes up. It is not introduced by this patch. It needs more debugging.) Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/3932 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek(a)assembler.cz> See http://review.coreboot.org/3932 for details. -gerrit

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coreboot-gerrit November 2013