[M] Change in coreboot[master]: soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headers

[David Hendricks (Code Review)]

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, David Hendricks, Arthur Heymans, Tim Chu.

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73171 )

Change subject: soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headers
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Patch Set 4:

(1 comment)

Patchset:

PS4: 
This patchset implements a suggestion from CB:72611 to split MSR headers into different files. Some of the MSRs on SPR are laid out differently from previous generations, so it made sense to split the headers apart.

For this patch set, I went through the EDS docs for SKX, CPX, and SPR to figure out which MSRs are common or not. SKX and CPX are fairly similar, particularly fields in MSR_POWER_CTL. However there are some differences, for example in the number of MC banks implemented. SPR (CB:73172) has a lot more differences.

For now I tried to leave formatting the same (simple cut+paste from one header to another). We may want to re-formatt these files later on using the updated .clang-format from Elyes (CB:64779).