Change in coreboot[master]: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62662 )

Change subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
......................................................................

mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP

In order to enable the UFS controller (PCI device 12.7), the PCI
specification says that the device at function 0 in the same slot must
also be enabled, which is the ISH. Therefore, this CL enables both
the UFS controller and ISH.

TEST=Boot to kernel and check lspci output
     00:12.0 Serial controller: Intel Corporation Device 54fc
     00:12.7 Mass storage controller [0109]: Intel Corporation
     Device 54ff

Signed-off-by: Meera Ravindranath 
Signed-off-by: Rizwan Qureshi 
Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62662
Reviewed-by: Lean Sheng Tan 
Reviewed-by: Kangheui Won 
Reviewed-by: Angel Pons 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/adlrvp/devicetree_n.cb
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve
  Lean Sheng Tan: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved
  Kangheui Won: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index 57a3701..40dba8b 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -270,6 +270,8 @@
    	device ref gspi0 on end
    	device ref p2sb on end
    	device ref emmc on end
+		device ref ish on end
+		device ref ufs on end
    	device ref hda on
    		chip drivers/intel/soundwire
    			device generic 0 on