[S] Change in coreboot[master]: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger.

Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/72735

to look at the new patch set (#2).

Change subject: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges
......................................................................

soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges

Commit b171f768127d ("soc/amd/*: Hook up GPP bridges ops to devicetree")
missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge
PCIe ports, so add them. Those devices were previously covered by the
PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that
got removed in the referenced commit.

Signed-off-by: Felix Held 
Change-Id: I55434bf486569b32901b3840193a09cc5955abb2
---
M src/soc/amd/cezanne/chipset.cb
1 file changed, 19 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/72735/2