[S] Change in coreboot[main]: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD

[Subrata Banik (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85131?usp=email )

Change subject: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD
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Patch Set 13:

(1 comment)

Patchset:

PS6:
> According to [baseboard/fatcat/ramstage.c](https://github.com/coreboot/coreboot/blob/main/src/mainboard/google/fatcat/v...), I can deduce that the intention is to at least support MCH IDs `b001`, `b002`, `b004`, and `b00a`. It turns out that `b001`, `b004`, and `b00a` are from the PTL H12Xe family, while `b002` is from the PTL H4Xe family. These two families have different IA, GT, and SA I_TRIP</sub>_NOM values.
>
> The [Panther Lake chip.h](https://github.com/coreboot/coreboot/blob/main/src/soc/intel/pantherlake/chi...) does not permit having per-SKU values. Before I start making potentially unnecessary architectural changes, I would like to know if some SKUs are specific to certain variants or not. I need to know if a single value per variant is going to work or not, just like it was working for Meteor Lake rex.

I assume this is more specific question for Intel team if we can support single value that works for different SKUs ? can you please help to get such data. The plan is to use PTL-UH (PTL_U actually) combination so, I don't mind to lowering the power envelop based on PTL-U configuration that is applicable for all OEM devices