HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32699
Change subject: sb/i82801gx: Don't rewrite over BCTRL ......................................................................
sb/i82801gx: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h>, and BCTRL also at 0x3e, is real registry name for D30:F0 (see ICH7 Family Datasheet page 355) The write on that register is already done some lines above. So remove wrong register name and the wrong code line.
Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/i82801gx/pci.c 1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/32699/1
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index c54769f..22c5165 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -46,9 +46,6 @@ reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8);
- /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900;
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32699 )
Change subject: sb/i82801gx: Don't rewrite over BCTRL ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32699/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32699/1//COMMIT_MSG@9 PS1, Line 9: PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h>, which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82).
Same header file also defines PCI_BRIDGE_CONTROL as 0x3e. So BCTRL is nothing special.
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32699
to look at the new patch set (#2).
Change subject: sb/i82801gx: Don't rewrite over BCTRL ......................................................................
sb/i82801gx: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82).
BCTRL registry for D30:F0 is defined at offset 0x3e for i82801gx (see ICH7 Family Datasheet page 355). The write on that register is already done some lines above. So remove wrong register name and the wrong code line.
Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/i82801gx/pci.c 1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/32699/2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32699 )
Change subject: sb/i82801gx: Don't rewrite over BCTRL ......................................................................
sb/i82801gx: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82).
BCTRL registry for D30:F0 is defined at offset 0x3e for i82801gx (see ICH7 Family Datasheet page 355). The write on that register is already done some lines above. So remove wrong register name and the wrong code line.
Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/32699 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/southbridge/intel/i82801gx/pci.c 1 file changed, 0 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index c54769f..22c5165 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -46,9 +46,6 @@ reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8);
- /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900;
-
HAOUAS Elyes (Code Review) -
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)