Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin.
Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )
Change subject: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes
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Patch Set 8:
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/pcielane.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/afd027c4_30cd5555?usp... :
PS8, Line 131: gpio5 = 0x20;
When PCIEPCS1 == 0, PCIEX1_2 remains not working with X_QSW_SEL2,3,4 being 111 and the following log:
Sorry, I forgot to write that this was just observed on patchset 8.
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