[S] Change in coreboot[main]: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug

[Arthur Heymans (Code Review)]

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Tim Chu.

Hello Andrey Petrov, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Shuo Liu, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/80579?usp=email

to look at the new patch set (#5).

The following approvals got outdated and were removed:
Code-Review+1 by Felix Singer, Code-Review+1 by Nico Huber, Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins)

Change subject: drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug
......................................................................

drivers/intel/fsp: Work around multi socket Xeon-SP pipe init bug

Starting with Intel CPX there is a bug in the reference code during
the Pipe init. This code synchronises the CAR between sockets in FSP-M.
This code implicitly assumes that the top of FSP heap is FspStackBase +
FspStackSize and the bottom is the bottom of CAR.

Work around this issue by making that implicit assumption done in FSP
explicit in the coreboot linker script and allocation.

Signed-off-by: Arthur Heymans 
Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4
---
M src/arch/x86/car.ld
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/memory_init.c
M src/soc/intel/xeon_sp/cpx/Kconfig
M src/soc/intel/xeon_sp/spr/Kconfig
5 files changed, 26 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80579/5