[M] Change in coreboot[main]: soc/amd/genoa: Add PCI interrupt support

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78392?usp=email )

Change subject: soc/amd/genoa: Add PCI interrupt support
......................................................................

soc/amd/genoa: Add PCI interrupt support

This patch adds PCI interrupt details as per the Processor Programming
Reference (PPR) version 0.25 (#55901), table 319.

Change-Id: I81251bd60aac1d7bd3181699d3adca315291f336
Signed-off-by: Varshit Pandya 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78392
Reviewed-by: Felix Held 
Tested-by: build bot (Jenkins) 
---
A src/soc/amd/genoa/acpi/pci_int_defs.asl
A src/soc/amd/genoa/acpi/soc.asl
A src/soc/amd/genoa/include/soc/amd_pci_int_defs.h
3 files changed, 160 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/soc/amd/genoa/acpi/pci_int_defs.asl b/src/soc/amd/genoa/acpi/pci_int_defs.asl
new file mode 100644
index 0000000..22455c5
--- /dev/null
+++ b/src/soc/amd/genoa/acpi/pci_int_defs.asl
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* PCI IRQ mapping registers, C00h-C01h. */
+OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
+	Field(PRQM, ByteAcc, NoLock, Preserve) {
+	PRQI, 0x00000008,
+	PRQD, 0x00000008,  /* Offset: 1h */
+}
+
+/*
+ * All PIC indexes are prefixed with P.
+ * All IO-APIC indexes are prefixed with I.
+ */
+IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+	PIRA, 0x00000008,	/* Index 0: INTA */
+	PIRB, 0x00000008,	/* Index 1: INTB */
+	PIRC, 0x00000008,	/* Index 2: INTC */
+	PIRD, 0x00000008,	/* Index 3: INTD */
+	PIRE, 0x00000008,	/* Index 4: INTE */
+	PIRF, 0x00000008,	/* Index 5: INTF */
+	PIRG, 0x00000008,	/* Index 6: INTG */
+	PIRH, 0x00000008,	/* Index 7: INTH */
+
+	Offset (0x10),
+	PSCI, 0x00000008,	/* Index 0x10: SCI */
+	PSB0, 0x00000008,	/* Index 0x11: SMBUS0 */
+	PASF, 0x00000008,	/* Index 0x12: ASF */
+
+	Offset (0x16),
+	PPMN, 0x00000008,	/* Index 0x16: PerMon */
+
+	Offset (0x1a),
+	PSIO, 0x00000008,	/* Index 0x1A: SDIO */
+
+	Offset (0x50),
+	PGP0, 0x00000008,	/* Index 0x50: GPP0 */
+	PGP1, 0x00000008,	/* Index 0x51: GPP1 */
+	PGP2, 0x00000008,	/* Index 0x52: GPP2 */
+	PGP3, 0x00000008,	/* Index 0x53: GPP3 */
+
+	Offset (0x62),
+	PGPI, 0x00000008,	/* Index 0x62: GPIO */
+
+	Offset (0x70),
+	PI20, 0x00000008,	/* Index 0x70: I2C0/I3C0 */
+	PI21, 0x00000008,	/* Index 0x71: I2C1/I3C1 */
+	PI22, 0x00000008,	/* Index 0x72: I2C2/I3C2 */
+	PI23, 0x00000008,	/* Index 0x73: I2C3/I3C3 */
+	PUA0, 0x00000008,	/* Index 0x74: UART0 */
+	PUA1, 0x00000008,	/* Index 0x75: UART1 */
+	PI24, 0x00000008,	/* Index 0x76: I2C4 */
+	PI25, 0x00000008,	/* Index 0x77: I2C5 */
+	PUA2, 0x00000008,	/* Index 0x78: UART2 */
+	PUA3, 0x00000008,	/* Index 0x79: UART3 */
+
+	/* IO-APIC IRQs */
+	Offset (0x80),
+	IORA, 0x00000008,	/* Index 0x80: INTA */
+	IORB, 0x00000008,	/* Index 0x81: INTB */
+	IORC, 0x00000008,	/* Index 0x82: INTC */
+	IORD, 0x00000008,	/* Index 0x83: INTD */
+	IORE, 0x00000008,	/* Index 0x84: INTE */
+	IORF, 0x00000008,	/* Index 0x85: INTF */
+	IORG, 0x00000008,	/* Index 0x86: INTG */
+	IORH, 0x00000008,	/* Index 0x87: INTH */
+
+	Offset (0x90),
+	ISCI, 0x00000008,	/* Index 0x90: SCI */
+	ISB0, 0x00000008,	/* Index 0x91: SMBUS0 */
+	IASF, 0x00000008,	/* Index 0x92: ASF */
+
+	Offset (0x96),
+	IPMN, 0x00000008,	/* Index 0x96: PerMon */
+
+	Offset (0x9a),
+	ISIO, 0x00000008,	/* Index 0x9A: SDIO */
+
+	Offset (0xD0),
+	IGP0, 0x00000008,	/* Index 0xD0: GPP0 */
+	IGP1, 0x00000008,	/* Index 0xD1: GPP1 */
+	IGP2, 0x00000008,	/* Index 0xD2: GPP2 */
+	IGP3, 0x00000008,	/* Index 0xD3: GPP3 */
+
+	Offset (0xE2),
+	IGPI, 0x00000008,	/* Index 0xE2: GPIO */
+
+	Offset (0xF0),
+	II20, 0x00000008,	/* Index 0xF0: I2C0/I3C0 */
+	II21, 0x00000008,	/* Index 0xF1: I2C1/I3C1 */
+	II22, 0x00000008,	/* Index 0xF2: I2C2/I3C2 */
+	II23, 0x00000008,	/* Index 0xF3: I2C3/I3C3 */
+	IUA0, 0x00000008,	/* Index 0xF4: UART0 */
+	IUA1, 0x00000008,	/* Index 0xF5: UART1 */
+	II24, 0x00000008,	/* Index 0xF6: I2C4 */
+	II25, 0x00000008,	/* Index 0xF7: I2C5 */
+	IUA2, 0x00000008,	/* Index 0xF8: UART2 */
+	IUA3, 0x00000008,	/* Index 0xF9: UART3 */
+}
diff --git a/src/soc/amd/genoa/acpi/soc.asl b/src/soc/amd/genoa/acpi/soc.asl
new file mode 100644
index 0000000..88b0df8
--- /dev/null
+++ b/src/soc/amd/genoa/acpi/soc.asl
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope(_SB) {
+	/* global utility methods expected within the _SB scope */
+	#include "pci_int_defs.asl"
+} /* End _SB scope */
diff --git a/src/soc/amd/genoa/include/soc/amd_pci_int_defs.h b/src/soc/amd/genoa/include/soc/amd_pci_int_defs.h
new file mode 100644
index 0000000..7d2bb39
--- /dev/null
+++ b/src/soc/amd/genoa/include/soc/amd_pci_int_defs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_GENOA_AMD_PCI_INT_DEFS_H
+#define AMD_GENOA_AMD_PCI_INT_DEFS_H
+
+/*
+ *  * PIRQ and device routing - these define the index into the
+ *   * FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
+ *    */
+
+#define PIRQ_NC		0x1f	/* Not Used */
+#define PIRQ_A		0x00	/* INT A */
+#define PIRQ_B		0x01	/* INT B */
+#define PIRQ_C		0x02	/* INT C */
+#define PIRQ_D		0x03	/* INT D */
+#define PIRQ_E		0x04	/* INT E */
+#define PIRQ_F		0x05	/* INT F */
+#define PIRQ_G		0x06	/* INT G */
+#define PIRQ_H		0x07	/* INT H */
+#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings */
+#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
+#define PIRQ_HPET_L	0x0a	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_HPET_H	0x0b	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_SIRQA	0x0c	/* Serial IRQ INTA */
+#define PIRQ_SIRQB	0x0d	/* Serial IRQ INTB */
+#define PIRQ_SIRQC	0x0e	/* Serial IRQ INTC */
+#define PIRQ_SIRQD	0x0f	/* Serial IRQ INTD */
+#define PIRQ_SCI	0x10	/* SCI IRQ */
+#define PIRQ_SMBUS	0x11	/* SMBUS0 */
+#define PIRQ_ASF	0x12	/* ASF */
+/* 0x13-0x15 reserved */
+#define PIRQ_PMON	0x16	/* Performance Monitor */
+/* 0x17-0x19 reserved */
+#define PIRQ_SDIO	0x1a	/* SDIO */
+/* 0x1b-0x49 reserved */
+#define PIRQ_GPP0	0x50	/* GPPInt0 */
+#define PIRQ_GPP1	0x51	/* GPPInt1 */
+#define PIRQ_GPP2	0x52	/* GPPInt2 */
+#define PIRQ_GPP3	0x53	/* GPPInt3 */
+/* 0x54-0x59 reserved */
+#define PIRQ_SCI	0x60	/* SCI Interrupt */
+#define PIRQ_SMI	0x61	/* SMI Interrupt */
+#define PIRQ_GPIO	0x62	/* GPIO Interrupt */
+/* 0x63-0x6f reserved */
+#define PIRQ_I2C0	0x70	/* I2C0/I3C0 */
+#define PIRQ_I2C1	0x71	/* I2C1/I3C1 */
+#define PIRQ_I2C2	0x72	/* I2C2/I3C2 */
+#define PIRQ_I2C3	0x73	/* I2C3/I3C3 */
+#define PIRQ_UART0	0x74	/* UART0 */
+#define PIRQ_UART1	0x75	/* UART1 */
+#define PIRQ_I2C4	0x76	/* I2C4 */
+#define PIRQ_I2C5	0x77	/* I2C5 */
+#define PIRQ_UART2	0x78	/* UART2 */
+#define PIRQ_UART3	0x79	/* UART3 */
+
+#endif /* AMD_GENOA_AMD_PCI_INT_DEFS_H */