Attention is currently required from: Jakub Czapiga, Kapil Porwal, Tarun Tuli.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76212?usp=email )
Change subject: mb/google/rex/var/ovis: Enable LAN1 ......................................................................
mb/google/rex/var/ovis: Enable LAN1
This patch performs below operations to enable LAN1. - Add overridetree.cb entry to configure the LAN device. - Complete the LAN1/SD PEREST power sequencing
BUG=b:289395519 TEST=Able to boot google/ovis with LAN1 being enabled.
Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff Signed-off-by: Subrata Banik subratabanik@google.com --- M src/mainboard/google/rex/variants/ovis/gpio.c M src/mainboard/google/rex/variants/ovis/overridetree.cb 2 files changed, 13 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/76212/1
diff --git a/src/mainboard/google/rex/variants/ovis/gpio.c b/src/mainboard/google/rex/variants/ovis/gpio.c index 26e77f5..6c1794d 100644 --- a/src/mainboard/google/rex/variants/ovis/gpio.c +++ b/src/mainboard/google/rex/variants/ovis/gpio.c @@ -400,13 +400,16 @@
/* GPP_H10 : [] ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), + + /* GPP_D02 : [] ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_D02, 0, DEEP), };
static const struct pad_config romstage_gpio_table[] = { /* A20 : [] ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_D02 : [] ==> SD_PERST_L */ - PAD_CFG_GPO(GPP_D02, 1, DEEP), + PAD_CFG_GPO(GPP_D02, 0, DEEP), };
const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index 80a22de..259aaf5 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -55,6 +55,15 @@ device generic 0 alias dptf_policy on end end end + device ref pcie_rp7 on + # Enable LAN1 Card PCIE 7 using clk 2 + register "pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE7 LAN1 card + device ref pcie_rp11 on # Enable SSD Card PCIE 11 using clk 7 register "pcie_rp[PCH_RP(11)]" = "{