[S] Change in coreboot[main]: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD

[Jérémy Compostella (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik.

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85131?usp=email )

Change subject: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD
......................................................................

Patch Set 9:

(1 comment)

Patchset:

PS6:
> > > Actually, the UPDs are still missing (I grepped the wrong directory this morning, I clearly need […]

We needed to wait for 3015 for the `CepEnable` UPD to even exist.

https://review.coreboot.org/c/coreboot/+/86258 introduces 3015 Partial headers. However, in order to fully utilize this feature, we integrated a CL from a subsequent version of the FSP, which exports some extra UPDs. While UPDs were present in version 3015, they are not naively accessible .

To legitimate CL 86258, we can port the extra UPD exportation CL to Google repository once a 3015 is available in this repository.