[S] Change in coreboot[main]: mb/google/brya: Centralize GPIO configuration in trulo baseboard

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83545?usp=email )

Change subject: mb/google/brya: Centralize GPIO configuration in trulo baseboard
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mb/google/brya: Centralize GPIO configuration in trulo baseboard

This change moves the GPIO configuration from the orisa variant to the
trulo baseboard, enabling reuse by other variants in the future.

BUG=b:351976770
TEST=Builds successfully for google/orisa.

Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83545
Reviewed-by: Eric Lai 
Reviewed-by: Dinesh Gehlot 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h
M src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
2 files changed, 13 insertions(+), 20 deletions(-)

Approvals:
  Dinesh Gehlot: Looks good to me, approved
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h
index 9ca9ee7..6bfcc81 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/include/baseboard/gpio.h
@@ -6,10 +6,17 @@
 #include <soc/gpe.h>
 #include <soc/gpio.h>

-/* TODO: Set the correct values */
-#define EC_SCI_GPI		0
-#define GPIO_PCH_WP		0
-#define GPIO_EC_IN_RW		0
-#define GPIO_SLP_S0_GATE	0
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI		GPE0_ESPI
+/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */
+#define GPE_EC_WAKE		GPE0_DW2_17
+/* WP signal to PCH */
+#define GPIO_PCH_WP		GPP_E3
+/* EC in RW or RO */
+#define GPIO_EC_IN_RW		GPP_F18
+/* GPIO IRQ for tight timestamps, MKBP interrupts */
+#define EC_SYNC_IRQ		GPD2_IRQ
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE	GPP_H18

#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
index c362383..c4fe342 100644
--- a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
@@ -3,20 +3,6 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H

-#include <soc/gpe.h>
-#include <soc/gpio.h>
-
-/* eSPI virtual wire reporting */
-#define EC_SCI_GPI		GPE0_ESPI
-/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */
-#define GPE_EC_WAKE		GPE0_DW2_17
-/* WP signal to PCH */
-#define GPIO_PCH_WP		GPP_E3
-/* EC in RW or RO */
-#define GPIO_EC_IN_RW		GPP_F18
-/* GPIO IRQ for tight timestamps, MKBP interrupts */
-#define EC_SYNC_IRQ		GPD2_IRQ
-/* Used to gate SoC's SLP_S0# signal */
-#define GPIO_SLP_S0_GATE	GPP_H18
+#include <baseboard/gpio.h>

#endif