[XS] Change in coreboot[main]: soc/intel/xeon_sp: Clean up device enablement configuration

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82120?usp=email )

Change subject: soc/intel/xeon_sp: Clean up device enablement configuration
......................................................................

soc/intel/xeon_sp: Clean up device enablement configuration

Clean up by using is_devfn_enabled().

Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82120
Reviewed-by: Matt DeVillier 
Reviewed-by: Shuo Liu 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/cpx/romstage.c
1 file changed, 1 insertion(+), 3 deletions(-)

Approvals:
  Shuo Liu: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index fe2ca86..b72417e 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -123,7 +123,6 @@
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-	const struct device *dev;
    const config_t *config = config_of_soc();

/* ErrorLevel - 0 (disable) to 8 (verbose) */
@@ -175,8 +174,7 @@

/* Enable PCH thermal device in FSP, the definition of ThermalDeviceEnable is
       0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI mode */
-	dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
-	m_cfg->ThermalDeviceEnable = dev && dev->enabled;
+	m_cfg->ThermalDeviceEnable = is_devfn_enabled(PCH_DEVFN_THERMAL);

/* Enable VT-d according to DTB */
    m_cfg->VtdSupport = config->vtd_support;