Change in coreboot[master]: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55987 )

Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
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Patch Set 2:

(2 comments)

File src/soc/amd/common/block/cpu/update_microcode.c:

https://review.coreboot.org/c/coreboot/+/55987/comment/90917d93_7679bdab 
PS1, Line 17: bool buffer_valid;
            : uint8_t buffer[CONFIG_SOC_AMD_COMMON_BLOCK_UCODE_SIZE];
> These can live within the scope of `amd_update_microcode_from_cbfs` and marked as static?

Done

https://review.coreboot.org/c/coreboot/+/55987/comment/ef7b5ef3_c661497c 
PS1, Line 85: ucode
> lol, thanks for pointing that out. […]

Done