Change in coreboot[master]: cpu/intel/{haswell,model_{1067,106c,206a,6e,6f}x}: Use SPEED_STEP_ENA...

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46271 )

Change subject: cpu/intel/{haswell,model_{1067,106c,206a,6e,6f}x}: Use SPEED_STEP_ENABLE_BIT macro
......................................................................

cpu/intel/{haswell,model_{1067,106c,206a,6e,6f}x}: Use SPEED_STEP_ENABLE_BIT macro

Change-Id: Ib395a07cd7f028121d1c1a3f31fd5f5cb9a7926e
Signed-off-by: Elyes HAOUAS 
---
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_1067x/model_1067x_init.c
M src/cpu/intel/model_106cx/model_106cx_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/cpu/intel/model_6ex/model_6ex_init.c
M src/cpu/intel/model_6fx/model_6fx_init.c
6 files changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46271/1

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index bf06add..9fd12ad 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -563,7 +563,7 @@
    msr = rdmsr(IA32_MISC_ENABLE);
    msr.lo |= FAST_STRINGS_ENABLE_BIT;
    msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
-	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	msr.lo |= SPEED_STEP_ENABLE_BIT;
    wrmsr(IA32_MISC_ENABLE, msr);

/* Disable Thermal interrupts */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index c130894..563c226 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -184,7 +184,7 @@
    msr.lo |= (1 << 10);	/* FERR# multiplexing */

if (eist)
-		msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+		msr.lo |= SPEED_STEP_ENABLE_BIT;

/* Enable C2E */
    if (((sub_cstates >> (2 * 4)) & 0xf) >= 2)
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 8c462f1..7be47a4 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -50,7 +50,7 @@
    msr.lo |= (1 << 10);	/* FERR# multiplexing */

// TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
-	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+	msr.lo |= SPEED_STEP_ENABLE_BIT;

// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
    wrmsr(IA32_MISC_ENABLE, msr);
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 6e229f6..86cea37 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -324,7 +324,7 @@
    msr = rdmsr(IA32_MISC_ENABLE);
    msr.lo |= FAST_STRINGS_ENABLE_BIT;
    msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
-	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	msr.lo |= SPEED_STEP_ENABLE_BIT;
    wrmsr(IA32_MISC_ENABLE, msr);

/* Disable Thermal interrupts */
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 16c6866..d007c92 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -51,7 +51,7 @@
    msr.lo |= (1 << 10);	/* FERR# multiplexing */

// TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
-	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+	msr.lo |= SPEED_STEP_ENABLE_BIT;

/* Enable C2E */
    msr.lo |= (1 << 26);
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index d0987b4..950027b 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -54,7 +54,7 @@
    msr.lo |= (1 << 10);	/* FERR# multiplexing */

// TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
-	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+	msr.lo |= SPEED_STEP_ENABLE_BIT;

/* Enable C2E */
    msr.lo |= (1 << 26);