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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66579 )
Change subject: soc/intel/cmn: Clear interrupt status after HECI-1 has been received
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Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66579/comment/131f084a_f32c8918
PS4, Line 15: get_me_fw_version
For our case we call get_me_fw_version after EOP and can see this issue. […]
Thanks Johnny for clarification.
The clearing interrupt request has to be done during Host CPU RX cycle. But, coreboot reads the messages in the poll mode. So, I guess your platform might be clearing interrupt status (code @ line# 542 in this file) before the CSE has sends the message. This can happen if CSE is busy when it receives the command from Host, so it may send after few milli seconds.
To confirm this, can you please do additional test : before clearing the interrupt status @line#542, just log the intr status).BTW, remove the fix in the patch in your test. From this test, we will understand if we are clearing the interrupt status before CSE generates.
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/66579/comment/1d6af63e_630a7ab6
PS4, Line 542: clear_int();
Is this too early in your platform? Can you check interrupt status before this code clears?
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