[M] Change in coreboot[master]: spd/lp5: Modify Hynix LPDDR5X memory Speed

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Frank Wu, John Su, Tarun Tuli, Chao Gui, Dtrain Hsu, Subrata Banik, Nick Vaccaro, Eric Lai, Martin Roth.

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73251 )

Change subject: spd/lp5: Modify Hynix LPDDR5X memory Speed
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Patch Set 3: Code-Review+2

(1 comment)

File spd/lp5/memory_parts.json:

https://review.coreboot.org/c/coreboot/+/73251/comment/f11f3d70_1f7c241f 
PS1, Line 207:                 "speedMbps": 8533,
> Sorry pressed enter too soon. Adding Nick, Subrata and Tarun for visibility. […]

Sorry for the confusion. Thinking twice, I would recommend SPD to reflect what the memory part is capable of. If the memory part can support 8533 MT/s, then it should be encoded in the SPD.

Otherwise if any of the future boards support 8533 MT/s and we end up bumping the speed, that will lead to a new SPD binary. That in turn means hardware RAM_ID strapping has to change or we have to put in weird workaround in the SPD gen tool for the current generation of platforms.

Thanks for fixing this.