[S] Change in coreboot[main]: soc/intel: Log CSE Sync Early Sign of Life event from a better place

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85111?usp=email )

Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place
......................................................................

soc/intel: Log CSE Sync Early Sign of Life event from a better place

CSE Sync Early Sign of Life (ESOL) event is logged as soon as the CSE FW
update is complete. This happens irrespective of whether Early Sign of
Life screen is enabled or not. Move CSE Sync ESOL event right before
displaying the ESOL screen.

BUG=b:378458829, b:379585294
TEST=Build Brox BIOS image and boot to OS. Ensure that the ESOL event
for CSE Sync is logged.

Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85111
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
Reviewed-by: Kapil Porwal 
---
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
4 files changed, 10 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index c98ce10..4a03b74 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -439,13 +439,15 @@
     * packed as part of the CBFS then CSE sync will be triggered. CSE sync can take
     * < 1-minute hence, let's inform the end user with an on-screen text message.
     */
-	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()) {
+	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()
+		&& !is_cse_boot_to_rw()) {
    	if (esol_required) {
    		name = "memory training and CSE update";
    	} else {
    		name = "CSE update";
    		esol_required =  true;
    	}
+		elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
    }

if (esol_required)
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index d3a2884..daf2b76 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -208,8 +208,10 @@
    if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) {
    	cse_fill_bp_info();
    	if (CONFIG(CHROMEOS_ENABLE_ESOL) &&
-		    is_cse_fw_update_required() && !is_cse_boot_to_rw())
+		    is_cse_fw_update_required() && !is_cse_boot_to_rw()) {
+			elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
    		ux_inform_user_of_update_operation("CSE update");
+		}
    	cse_fw_sync();
    }

diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 76e0853..07233a9 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -806,7 +806,6 @@
    	return CB_ERR;

printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n");
-	elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
    return CB_SUCCESS;
 }

diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index bc7c20b..82706ed 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -456,8 +456,11 @@
    	elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
    }

-	if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required())
+	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()
+		&& !is_cse_boot_to_rw()) {
    	vga_init_control = VGA_INIT_CONTROL_ENABLE;
+		elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
+	}

if (!vga_init_control)
    	return;