Change in coreboot[master]: cpu/amd: Always fetch CPU addr bits at runtime

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58686 )

Change subject: cpu/amd: Always fetch CPU addr bits at runtime
......................................................................

cpu/amd: Always fetch CPU addr bits at runtime

All supported AMD CPUs support getting the physical address size from cpuid so
there is no need for a Kconfig default value.

Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58686
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
Reviewed-by: Angel Pons 
---
M src/cpu/amd/mtrr/amd_mtrr.c
1 file changed, 2 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index fc3212f..8c703f5 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <arch/cpu.h>
+#include <cpu/cpu.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
@@ -85,7 +86,6 @@

void amd_setup_mtrrs(void)
 {
-	unsigned long address_bits;
    unsigned long i;
    msr_t msr, sys_cfg;
    // Test if this CPU is a Fam 0Fh rev. F or later
@@ -142,13 +142,6 @@

enable_cache();

-	//K8 could be 40, and GH could be 48
-	address_bits = CONFIG_CPU_ADDR_BITS;
-
-	/* AMD specific cpuid function to query number of address bits */
-	if (cpuid_eax(0x80000000) >= 0x80000008)
-		address_bits = cpuid_eax(0x80000008) & 0xff;
-
    /* Now that I have mapped what is memory and what is not
     * Set up the mtrrs so we can cache the memory.
     */
@@ -156,5 +149,5 @@
    // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need
    // variable MTRR to span memory above 4GB
    // Lower revisions K8 need variable MTRR over 4GB
-	x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1);
+	x86_setup_var_mtrrs(cpu_phys_address_size(), has_tom2wb ? 0 : 1);
 }

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.