Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43091 )
Change subject: haswell: drop unused function parameter ......................................................................
haswell: drop unused function parameter
The `chipset_type` parameter is ignored.
Change-Id: Ia3d217178cc9caabf232b3a59f505229cc03135f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/haswell/romstage.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h 3 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43091/1
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 4b56301..381d7bf 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,7 +25,7 @@ /* Perform some early chipset initialization required * before RAM initialization can work */ - haswell_early_initialization(HASWELL_MOBILE); + haswell_early_initialization(); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) { diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index fd188a1..9db6a9d 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -176,7 +176,7 @@ reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); }
-void haswell_early_initialization(int chipset_type) +void haswell_early_initialization(void) { /* Setup all BARs required for early PCIe and raminit */ haswell_setup_bars(); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index bd44168..c393049 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -189,7 +189,7 @@
void intel_northbridge_haswell_finalize_smm(void);
-void haswell_early_initialization(int chipset_type); +void haswell_early_initialization(void); void haswell_late_initialization(void); void set_translation_table(int start, int end, u64 base, int inc); void haswell_unhide_peg(void);
Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43091 )
Change subject: haswell: drop unused function parameter ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43091 )
Change subject: haswell: drop unused function parameter ......................................................................
haswell: drop unused function parameter
The `chipset_type` parameter is ignored.
Change-Id: Ia3d217178cc9caabf232b3a59f505229cc03135f Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43091 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tristan Corrick tristan@corrick.kiwi --- M src/cpu/intel/haswell/romstage.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h 3 files changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Tristan Corrick: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 4b56301..381d7bf 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,7 +25,7 @@ /* Perform some early chipset initialization required * before RAM initialization can work */ - haswell_early_initialization(HASWELL_MOBILE); + haswell_early_initialization(); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) { diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index fd188a1..9db6a9d 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -176,7 +176,7 @@ reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); }
-void haswell_early_initialization(int chipset_type) +void haswell_early_initialization(void) { /* Setup all BARs required for early PCIe and raminit */ haswell_setup_bars(); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index bd44168..c393049 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -189,7 +189,7 @@
void intel_northbridge_haswell_finalize_smm(void);
-void haswell_early_initialization(int chipset_type); +void haswell_early_initialization(void); void haswell_late_initialization(void); void set_translation_table(int start, int end, u64 base, int inc); void haswell_unhide_peg(void);
-
Angel Pons (Code Review) -
Tristan Corrick (Code Review)