Patch set updated for coreboot: 47fd4ff southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6147
-gerrit
commit 47fd4ffc849c71a4f31ddbcaf9795f60d901bb0f Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Sat Jun 28 15:36:57 2014 +1000
southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
Correct mask to select bits 4-6 inclusively as per comment and use bitwise operations while working with bits. First brought to attention by Clang.
Change-Id: I26e7acddbff32e978c2bf984c21d9a63337067f8 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/southbridge/amd/rs690/cmn.c | 4 ++-- src/southbridge/amd/rs780/cmn.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..1716188 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -289,9 +289,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x07; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ - reg += tmp; /* merge */ + reg |= tmp; /* merge */ reg |= 1 << 8; count++; /* CIM said "keep in loop"? */ } else { diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..4aa935f 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -330,9 +330,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + tmp = (reg >> 4) & 0x07; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ - reg += tmp; /* merge */ + reg |= tmp; /* merge */ reg |= 1 << 8; count++; /* CIM said "keep in loop"? */ } else {
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Edward O'Callaghan