[M] Change in coreboot[main]: soc/amd/genoa: add PCI domain resource reporting

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78342?usp=email )

Change subject: soc/amd/genoa: add PCI domain resource reporting
......................................................................

soc/amd/genoa: add PCI domain resource reporting

TEST=None

Signed-off-by: Felix Held 
Change-Id: Ifcd655ea6d5565668ffee36d0d022b2b711c0b00
---
M src/soc/amd/genoa/Kconfig
M src/soc/amd/genoa/Makefile.inc
M src/soc/amd/genoa/chipset.cb
A src/soc/amd/genoa/domain.c
4 files changed, 50 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/78342/1

diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index af4056a..a8f3a4d 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -13,6 +13,10 @@
    select SOC_AMD_COMMON_BLOCK_AOAC
    select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
    select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO
    select SOC_AMD_COMMON_BLOCK_HAS_ESPI
    select SOC_AMD_COMMON_BLOCK_LPC
    select SOC_AMD_COMMON_BLOCK_NONCAR
diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
index 2877fea..de8e2f1 100644
--- a/src/soc/amd/genoa/Makefile.inc
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -14,6 +14,7 @@

ramstage-y	+= aoac.c
 ramstage-y	+= chip.c
+ramstage-y	+= domain.c
 ramstage-y	+= root_complex.c

CPPFLAGS_common += -I$(src)/soc/amd/genoa/include
diff --git a/src/soc/amd/genoa/chipset.cb b/src/soc/amd/genoa/chipset.cb
index 6523617..cac8d4c 100644
--- a/src/soc/amd/genoa/chipset.cb
+++ b/src/soc/amd/genoa/chipset.cb
@@ -5,6 +5,7 @@
    end

device domain 0 on
+		ops genoa_pci_domain_ops
    	device pci 00.0 alias gnb_0 on end
    	device pci 00.2 alias iommu_0 off end
    	device pci 00.3 alias rcec_0 off end
@@ -72,6 +73,7 @@
    end

device domain 1 on
+		ops genoa_pci_domain_ops
    	device pci 00.0 alias gnb_1 on end
    	device pci 00.2 alias iommu_1 off end
    	device pci 00.3 alias rcec_1 off end
@@ -112,6 +114,7 @@
    end

device domain 2 on
+		ops genoa_pci_domain_ops
    	device pci 00.0 alias gnb_2 on end
    	device pci 00.2 alias iommu_2 off end
    	device pci 00.3 alias rcec_2 off end
@@ -152,6 +155,7 @@
    end

device domain 3 on
+		ops genoa_pci_domain_ops
    	device pci 00.0 alias gnb_3 on end
    	device pci 00.2 alias iommu_3 off end
    	device pci 00.3 alias rcec_3 off end
diff --git a/src/soc/amd/genoa/domain.c b/src/soc/amd/genoa/domain.c
new file mode 100644
index 0000000..43e436a
--- /dev/null
+++ b/src/soc/amd/genoa/domain.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/data_fabric.h>
+#include <amdblocks/root_complex.h>
+#include <amdblocks/smn.h>
+#include <arch/ioapic.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <types.h>
+
+#define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
+
+static void genoa_domain_set_resources(struct device *domain)
+{
+	if (domain->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+		printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n",
+		       domain->path.domain.domain);
+		const union df_vga_en vga_en = {
+			.ve = 1,
+			.dst_fabric_id = get_iohc_fabric_id(domain),
+		};
+		data_fabric_broadcast_write32(DF_VGA_EN, vga_en.raw);
+	}
+
+	pci_domain_set_resources(domain);
+
+	/* Enable IOAPIC memory decoding */
+	struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
+	if (res) {
+		const uint32_t iohc_misc_base = get_iohc_misc_smn_base(domain);
+		uint32_t ioapic_base = smn_read32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO);
+		ioapic_base |= (1 << 0);
+		smn_write32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO, ioapic_base);
+	}
+}
+
+struct device_operations genoa_pci_domain_ops = {
+	.read_resources	  = amd_pci_domain_read_resources,
+	.set_resources	  = genoa_domain_set_resources,
+	.scan_bus	  = amd_pci_domain_scan_bus,
+};