Change in coreboot[master]: mb/starlabs/lite: Add Lite Mk IV variant

[Sean Rhodes (Code Review)]

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62706 )

Change subject: mb/starlabs/lite: Add Lite Mk IV variant
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Patch Set 19:

(2 comments)

File src/mainboard/starlabs/lite/variants/glkr/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/62706/comment/26d78b06_4e10320d 
PS18, Line 6: 	# Graphics
            : 	# TODO:
            : 	# register "panel_cfg" = "{
            : 	#	.up_delay_ms			=  0,				// T3
            : 	#	.backlight_on_delay_ms		=  0,				// T7
            : 	#	.backlight_off_delay_ms		=  0,				// T9
            : 	#	.down_delay_ms			=  0,				// T10
            : 	#	.cycle_delay_ms			=  500,				// T12
            : 	#	.backlight_pwm_hz		=  200,				// PWM
            : 	# }"
> Ah, there's CB:31611 if you're interested in libgfxinit

Thanks, will pick it up once APL is done - I think there's only a couple of bugs left.

https://review.coreboot.org/c/coreboot/+/62706/comment/3d54ca30_7b770a74 
PS18, Line 36: 
             : 	register "pcie_rp_clkreq_pin[0]"	= "CLKREQ_DISABLED"
             : 	register "pcie_rp_clkreq_pin[1]"	= "CLKREQ_DISABLED"
             : 	register "pcie_rp_clkreq_pin[2]"	= "CLKREQ_DISABLED"
             : 	register "pcie_rp_clkreq_pin[3]"	= "CLKREQ_DISABLED"
             : 	register "pcie_rp_clkreq_pin[4]"	= "CLKREQ_DISABLED"
             : 	register "pcie_rp_clkreq_pin[5]"	= "CLKREQ_DISABLED"
             : 
             : 	register "pcie_rp_deemphasis_enable[0]"	= "1"
             : 	register "pcie_rp_deemphasis_enable[1]"	= "1"
             : 	register "pcie_rp_deemphasis_enable[2]"	= "1"
             : 	register "pcie_rp_deemphasis_enable[3]"	= "1"
             : 	register "pcie_rp_deemphasis_enable[4]"	= "1"
             : 	register "pcie_rp_deemphasis_enable[5]"	= "1"
> According to FSP debug, FSP is stupid.

Ah that made me giggle :)