Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5983
-gerrit
commit 146521eb6eb8c8f8fccca627f8aaeff0c1c86c06 Author: Martin Roth martin.roth@se-eng.com Date: Thu Jun 12 12:08:26 2014 -0600
bayleybay_fsp: Add bakersport board variant
The Bakersport board is a variant of the Bayley Bay mainboard that uses one ECC DIMM instead of two non-ECC dimms. This commit uses the Bayley Bay mainboard directory and just modifies the required pieces to add the Bakersport board variant. It disables the second DIMM, points to an ECC version of the FSP, and sets the board name to be Bakersport instead of Bayley Bay.
Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa Signed-off-by: Martin Roth martin.roth@se-eng.com --- src/mainboard/intel/Kconfig | 2 ++ src/mainboard/intel/bayleybay_fsp/Kconfig | 8 +++++--- src/mainboard/intel/bayleybay_fsp/romstage.c | 7 +++++++ 3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 4940c54..5e49d8f 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -3,6 +3,8 @@ if VENDOR_INTEL choice prompt "Mainboard model"
+config BOARD_INTEL_BAKERSPORT_FSP + bool "Bakersport FSP-based CRB" config BOARD_INTEL_BAYLEYBAY_FSP bool "Bayley Bay FSP-based CRB" config BOARD_INTEL_COUGAR_CANYON2 diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 8dcc199..f28b8dd 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -17,7 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-if BOARD_INTEL_BAYLEYBAY_FSP +if BOARD_INTEL_BAYLEYBAY_FSP || BOARD_INTEL_BAKERSPORT_FSP
config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -47,7 +47,8 @@ config LOCK_MANAGEMENT_ENGINE
config MAINBOARD_PART_NUMBER string - default "Bayley Bay CRB" + default "Bayley Bay CRB" if BOARD_INTEL_BAYLEYBAY_FSP + default "Bakersport CRB" if BOARD_INTEL_BAKERSPORT_FSP
config IRQ_SLOT_COUNT int @@ -63,7 +64,8 @@ config CACHE_ROM_SIZE_OVERRIDE
config FSP_FILE string - default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" + default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" if BOARD_INTEL_BAYLEYBAY_FSP + default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP
config MRC_CACHE_LOC_OVERRIDE hex diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index 34199bd..1e91332 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -173,4 +173,11 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
/* Initialize the Azalia Verb Tables to mainboard specific version */ UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; + + /* Disable 2nd DIMM on Bakersport*/ +#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP) + UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */ +#endif + + return; }