Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47165 )
Change subject: sb/intel/*: Use common code to configure the POST code ......................................................................
sb/intel/*: Use common code to configure the POST code
Change-Id: I4989414bdd45929265bc47e953e646bf5f59667c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/early_init.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/pch/bootblock.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/bootblock.c 16 files changed, 20 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47165/1
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index dea4f9b..1cbaec0 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -789,9 +789,6 @@ /* Setup all BARs required for early PCIe and raminit */ i945_setup_bars();
- /* Change port80 to LPC */ - RCBA32(GCS) &= (~0x04); - /* Just do it that way */ RCBA32(0x2010) |= (1 << 10); } diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..92f9242 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -164,7 +164,5 @@ /* Miscellaneous setup */ early_misc_setup();
- /* Route port80 to LPC */ - RCBA32(GCS) &= (~0x04); RCBA32(0x2010) |= (1 << 10); } diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2430be6..cb12608 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -22,6 +22,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + select SOUTHBRIDGE_INTEL_COMMON_POST select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c index 7f6d0d5..9008c6f 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/soc/intel/broadwell/pch/bootblock.c @@ -10,21 +10,13 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h>
static void map_rcba(void) { pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); }
-static void enable_port80_on_lpc(void) -{ - /* Enable port 80 POST on LPC. The chipset does this by default, - * but it doesn't appear to hurt anything. */ - u32 gcs = RCBA32(GCS); - gcs = gcs & ~0x4; - RCBA32(GCS) = gcs; -} - static void set_spi_speed(void) { u32 fdod; diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 7852ace..d8018cc 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -34,6 +34,7 @@ select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_POST
config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index a3228e7..4f561ea 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -3,14 +3,9 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "pch.h"
-static void enable_port80_on_lpc(void) -{ - /* Enable port 80 POST on LPC */ - RCBA32(GCS) &= (~0x04); -} - static void set_spi_speed(void) { u32 fdod; @@ -36,8 +31,8 @@ enable_spi_prefetching_and_caching();
early_pch_init(); + configure_port80();
- enable_port80_on_lpc(); set_spi_speed();
/* Enable upper 128bytes of CMOS */ diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 50f7c60..579590d 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -20,6 +20,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_POST
if SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 51fb24f..462cea8 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -3,6 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "i82801gx.h"
void bootblock_early_southbridge_init(void) @@ -10,6 +11,7 @@ enable_spi_prefetching_and_caching();
i82801gx_setup_bars(); + configure_port80();
/* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index e1405cf..984f3fa 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -20,6 +20,7 @@ select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select USE_WATCHDOG_ON_BOOT + select SOUTHBRIDGE_INTEL_COMMON_POST
if SOUTHBRIDGE_INTEL_I82801IX
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 7a66b47..8a27de8 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -3,6 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "i82801ix.h"
void bootblock_early_southbridge_init(void) @@ -10,5 +11,6 @@ enable_spi_prefetching_and_caching();
i82801ix_early_init(); + configure_port80(); i82801ix_lpc_setup(); } diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 6abeac1..f6b8aa9 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -22,6 +22,7 @@ select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select USE_WATCHDOG_ON_BOOT + select SOUTHBRIDGE_INTEL_COMMON_POST
if SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 7caebdc..370d839 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -3,6 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "i82801jx.h"
void bootblock_early_southbridge_init(void) @@ -10,6 +11,7 @@ enable_spi_prefetching_and_caching();
i82801jx_setup_bars(); + configure_port80();
/* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 07f9b6b..31b799a 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -31,6 +31,7 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_POST
config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c index 944378e..1070b5f9 100644 --- a/src/southbridge/intel/ibexpeak/bootblock.c +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -3,14 +3,10 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "pch.h" #include "chip.h"
-static void enable_port80_on_lpc(void) -{ - RCBA32(GCS) &= ~4; -} - static void set_spi_speed(void) { u32 fdod; @@ -82,7 +78,6 @@ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0); pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
- enable_port80_on_lpc(); set_spi_speed();
/* Enable upper 128bytes of CMOS */ diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 7ba86b8..323a925 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -33,6 +33,7 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select SOUTHBRIDGE_INTEL_COMMON_POST
config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 802c58e..01283d7 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -3,6 +3,7 @@ #include <arch/bootblock.h> #include <device/pci_ops.h> #include <southbridge/intel/common/early_spi.h> +#include <southbridge/intel/common/post.h> #include "pch.h"
static void map_rcba(void) @@ -10,15 +11,6 @@ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); }
-static void enable_port80_on_lpc(void) -{ - /* Enable port 80 POST on LPC. The chipset does this by default, - * but it doesn't appear to hurt anything. */ - u32 gcs = RCBA32(GCS); - gcs = gcs & ~0x4; - RCBA32(GCS) = gcs; -} - static void set_spi_speed(void) { u32 fdod; @@ -43,7 +35,8 @@ { map_rcba(); enable_spi_prefetching_and_caching(); - enable_port80_on_lpc(); + configure_port80(); + set_spi_speed();
/* Enable upper 128bytes of CMOS */
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47165 )
Change subject: sb/intel/*: Use common code to configure the POST code ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47165/1/src/soc/intel/broadwell/pch... File src/soc/intel/broadwell/pch/bootblock.c:
https://review.coreboot.org/c/coreboot/+/47165/1/src/soc/intel/broadwell/pch... PS1, Line 104: enable_port80_on_lpc needs an update?
Hello Damien Zammit, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47165
to look at the new patch set (#2).
Change subject: sb/intel/*: Use common code to configure the POST code ......................................................................
sb/intel/*: Use common code to configure the POST code
Change-Id: I4989414bdd45929265bc47e953e646bf5f59667c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/early_init.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/pch/bootblock.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/bootblock.c 16 files changed, 21 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47165/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47165 )
Change subject: sb/intel/*: Use common code to configure the POST code ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47165/1/src/soc/intel/broadwell/pch... File src/soc/intel/broadwell/pch/bootblock.c:
https://review.coreboot.org/c/coreboot/+/47165/1/src/soc/intel/broadwell/pch... PS1, Line 104: enable_port80_on_lpc
needs an update?
Done. Thanks
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47165 )
Change subject: sb/intel/*: Use common code to configure the POST code ......................................................................
Patch Set 2: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/47165/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801ix/Kconfig:
https://review.coreboot.org/c/coreboot/+/47165/2/src/southbridge/intel/i8280... PS2, Line 23: select SOUTHBRIDGE_INTEL_COMMON_POST ouch. I guess it's been added here because the other options aren't sorted
https://review.coreboot.org/c/coreboot/+/47165/2/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/bootblock.c:
https://review.coreboot.org/c/coreboot/+/47165/2/src/southbridge/intel/ibexp... PS2, Line 80: the call is now missing from ibexpeak?
Hello Damien Zammit, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47165
to look at the new patch set (#3).
Change subject: sb/intel/*: Use common code to configure the POST code ......................................................................
sb/intel/*: Use common code to configure the POST code
Change-Id: I4989414bdd45929265bc47e953e646bf5f59667c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/early_init.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/pch/bootblock.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/bootblock.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/bootblock.c 16 files changed, 22 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47165/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47165 )
Change subject: sb/intel/*: Use common code to configure the POST code ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/47165/2/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/bootblock.c:
https://review.coreboot.org/c/coreboot/+/47165/2/src/southbridge/intel/ibexp... PS2, Line 80:
the call is now missing from ibexpeak?
Done
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47165?usp=email )
Change subject: sb/intel/*: Use common code to configure the POST code ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Stefan Reinauer (Code Review)