[L] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add ramstage code

[Johnny Lin (Code Review)]

Attention is currently required from: TimLiu-SMCI, Johnny Lin, Christian Walter, Angel Pons, Jian-Ming Wang, Arthur Heymans, Srinidhi N Kaushik, Shelly Chang.

Johnny Lin has uploaded a new patch set (#8) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/72443 )

Change subject: soc/intel/xeon_sp/spr: Add ramstage code
......................................................................

soc/intel/xeon_sp/spr: Add ramstage code

Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2
Signed-off-by: Jonathan Zhang 
Signed-off-by: Johnny Lin 
---
A src/soc/intel/xeon_sp/spr/Makefile.inc
A src/soc/intel/xeon_sp/spr/chip.c
A src/soc/intel/xeon_sp/spr/chip.h
M src/soc/intel/xeon_sp/spr/chipset.cb
A src/soc/intel/xeon_sp/spr/cpu.c
A src/soc/intel/xeon_sp/spr/crashlog.c
A src/soc/intel/xeon_sp/spr/numa.c
A src/soc/intel/xeon_sp/spr/ramstage.c
A src/soc/intel/xeon_sp/spr/reset.c
A src/soc/intel/xeon_sp/spr/xhci.c
10 files changed, 872 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/72443/8