Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36639 )
Change subject: sb,soc/intel: Reduce prepocessor use with ME debugging ......................................................................
sb,soc/intel: Reduce prepocessor use with ME debugging
Change-Id: Iedd54730f140b6a7a40834f00d558ed99a345077 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/broadwell/include/soc/me.h M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/me_status.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/me_status.c 9 files changed, 70 insertions(+), 93 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36639/1
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h index a213e37..69b75b4 100644 --- a/src/soc/intel/broadwell/include/soc/me.h +++ b/src/soc/intel/broadwell/include/soc/me.h @@ -493,11 +493,7 @@
void intel_me_hsio_version(uint16_t *version, uint16_t *checksum);
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(void); -#else -static inline void intel_me_status(void) { } -#endif
#endif diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 6be1748..0461428 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,13 @@ /* MMIO base address for MEI interface */ static u8 *mei_base_address;
-#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -88,9 +90,6 @@ break; } } -#else -# define mei_dump(ptr, dword, offset, type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -483,7 +482,6 @@ vers_name->hotfix_version, vers_name->build_version); }
-#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -536,7 +534,6 @@ print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif
/* Send END OF POST message to the ME */ static int mkhi_end_of_post(void) @@ -804,9 +801,8 @@ { me_print_fw_version(mbp_data->fw_version_name);
-#if CONFIG(DEBUG_INTEL_ME) - me_print_fwcaps(mbp_data->fw_capabilities); -#endif + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data->fw_capabilities);
if (mbp_data->plat_time) { printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", @@ -912,12 +908,12 @@ }
/* Dump out the MBP contents. */ -#if CONFIG(DEBUG_INTEL_ME) - printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); - for (i = 0; i < mbp->header.mbp_size - 1; i++) - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); -#endif + if (CONFIG(DEBUG_INTEL_ME)) { + printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", + mbp->header.num_entries, mbp->header.mbp_size); + for (i = 0; i < mbp->header.mbp_size - 1; i++) + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + }
#define ASSIGN_FIELD_PTR(field_, val_) \ { \ diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 08fd48f..1880da1 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -34,8 +34,6 @@ memcpy(ptr, &dword, sizeof(dword)); }
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -210,6 +208,9 @@
void intel_me_status(void) { + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + struct me_hfs _hfs, *hfs = &_hfs; struct me_hfs2 _hfs2, *hfs2 = &_hfs2;
@@ -302,7 +303,6 @@ } printk(BIOS_DEBUG, "\n"); } -#endif
void intel_me_hsio_version(uint16_t *version, uint16_t *checksum) { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index ea60085..5e355a1 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -60,11 +60,13 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address;
-#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -90,9 +92,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -373,9 +372,8 @@ } #endif
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) /* Get ME firmware version */ -static int mkhi_get_fw_version(void) +static int __unused mkhi_get_fw_version(void) { struct me_fw_version version; struct mkhi_header mkhi = { @@ -412,7 +410,7 @@ }
/* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(void) +static int __unused mkhi_get_fwcaps(void) { u32 rule_id = 0; struct me_fwcaps cap; @@ -454,7 +452,6 @@
return 0; } -#endif
#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -714,12 +711,12 @@ if (intel_mei_setup(dev) < 0) break;
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* Print ME firmware version */ - mkhi_get_fw_version(); - /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + /* Print ME firmware version */ + mkhi_get_fw_version(); + /* Print ME firmware capabilities */ + mkhi_get_fwcaps(); + }
/* * Leave the ME unlocked in this path. diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 54c3fff..c224cb4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -62,11 +62,14 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address;
-#if CONFIG(DEBUG_INTEL_ME) + static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -92,9 +95,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -350,14 +350,13 @@ return 0; }
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", name, state ? " en" : "dis"); }
-static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name->major_version) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -395,7 +394,7 @@ }
/* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_fw_caps *caps_section) +static void __unused me_print_fwcaps(mbp_fw_caps *caps_section) { mefwcaps_sku *cap = &caps_section->fw_capabilities; if (!caps_section->available) { @@ -421,7 +420,6 @@ print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif
#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -719,10 +717,10 @@ } #endif
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(&mbp_data.fw_version_name); - me_print_fwcaps(&mbp_data.fw_caps_sku); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + me_print_fw_version(&mbp_data.fw_version_name); + me_print_fwcaps(&mbp_data.fw_caps_sku); + }
/* * Leave the ME unlocked in this path. diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index b202376..4d9540a 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -18,7 +18,6 @@ #include <console/console.h> #include "me.h"
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -137,11 +136,12 @@ [0x0f] = "ME cannot access the chipset descriptor region", [0x10] = "Required VSCC values for flash parts do not match", }; -#endif
void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) { -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); @@ -204,5 +204,4 @@ printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state); } printk(BIOS_DEBUG, "\n"); -#endif } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index f804126..c944f63 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -59,11 +59,13 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address;
-#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -89,9 +91,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 59a8666..1c45e2d 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -66,11 +66,13 @@ void intel_me_mbp_clear(struct device *dev); #endif
-#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -96,9 +98,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -380,7 +379,6 @@ return mei_wait_for_me_ready(); }
-#if CONFIG(DEBUG_INTEL_ME) || defined(__SMM__) static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, void *req_data, int req_bytes, void *rsp_data, int rsp_bytes) @@ -418,7 +416,6 @@
return 0; } -#endif /* CONFIG_DEBUG_INTEL_ME || __SMM__ */
/* * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read @@ -469,8 +466,7 @@ } }
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) -static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -482,7 +478,6 @@ vers_name->hotfix_version, vers_name->build_version); }
-#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -510,7 +505,7 @@ }
/* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_mefwcaps *cap) +static void __unused me_print_fwcaps(mbp_mefwcaps *cap) { mbp_mefwcaps local_caps; if (!cap) { @@ -535,8 +530,6 @@ print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif /* CONFIG_DEBUG_INTEL_ME */ -#endif
#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -851,21 +844,21 @@ if (intel_me_read_mbp(&mbp_data, dev)) return;
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(mbp_data.fw_version_name); -#if CONFIG(DEBUG_INTEL_ME) - me_print_fwcaps(mbp_data.fw_capabilities); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + me_print_fw_version(mbp_data.fw_version_name);
- if (mbp_data.plat_time) { - printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", - mbp_data.plat_time->wake_event_mrst_time_ms); - printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", - mbp_data.plat_time->mrst_pltrst_time_ms); - printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", - mbp_data.plat_time->pltrst_cpurst_time_ms); + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data.fw_capabilities); + + if (mbp_data.plat_time) { + printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", + mbp_data.plat_time->wake_event_mrst_time_ms); + printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", + mbp_data.plat_time->mrst_pltrst_time_ms); + printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", + mbp_data.plat_time->pltrst_cpurst_time_ms); + } } -#endif
/* Set clock enables according to devicetree */ if (config && config->icc_clock_disable) @@ -1004,15 +997,15 @@ #endif
/* Dump out the MBP contents. */ -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); -#if CONFIG(DEBUG_INTEL_ME) - for (i = 0; i < mbp->header.mbp_size - 1; i++) { - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", + mbp->header.num_entries, mbp->header.mbp_size); + if (CONFIG(DEBUG_INTEL_ME)) { + for (i = 0; i < mbp->header.mbp_size - 1; i++) { + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + } + } } -#endif -#endif
#define ASSIGN_FIELD_PTR(field_,val_) \ { \ diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 9ca5552..ad8362d 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -18,7 +18,6 @@ #include <console/console.h> #include "me.h"
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -138,11 +137,12 @@ [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region", [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; -#endif
void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) { -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); @@ -206,5 +206,4 @@ hfs2->progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); -#endif }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36639 )
Change subject: sb,soc/intel: Reduce prepocessor use with ME debugging ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36639/1/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/me_9.x.c:
https://review.coreboot.org/c/coreboot/+/36639/1/src/southbridge/intel/lynxp... PS1, Line 1004: for (i = 0; i < mbp->header.mbp_size - 1; i++) { braces {} are not necessary for single statement blocks
Hello Aaron Durbin, Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36639
to look at the new patch set (#2).
Change subject: sb,soc/intel: Reduce preprocessor use with ME debugging ......................................................................
sb,soc/intel: Reduce preprocessor use with ME debugging
Change-Id: Iedd54730f140b6a7a40834f00d558ed99a345077 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/broadwell/include/soc/me.h M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/me_status.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/me_status.c 9 files changed, 70 insertions(+), 93 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36639/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36639 )
Change subject: sb,soc/intel: Reduce preprocessor use with ME debugging ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36639/2/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/me_9.x.c:
https://review.coreboot.org/c/coreboot/+/36639/2/src/southbridge/intel/lynxp... PS2, Line 1004: for (i = 0; i < mbp->header.mbp_size - 1; i++) { braces {} are not necessary for single statement blocks
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36639 )
Change subject: sb,soc/intel: Reduce preprocessor use with ME debugging ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36639 )
Change subject: sb,soc/intel: Reduce preprocessor use with ME debugging ......................................................................
sb,soc/intel: Reduce preprocessor use with ME debugging
Change-Id: Iedd54730f140b6a7a40834f00d558ed99a345077 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36639 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/soc/intel/broadwell/include/soc/me.h M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/me_status.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/me_status.c 9 files changed, 70 insertions(+), 93 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h index a213e37..69b75b4 100644 --- a/src/soc/intel/broadwell/include/soc/me.h +++ b/src/soc/intel/broadwell/include/soc/me.h @@ -493,11 +493,7 @@
void intel_me_hsio_version(uint16_t *version, uint16_t *checksum);
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(void); -#else -static inline void intel_me_status(void) { } -#endif
#endif diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 6be1748..0461428 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,13 @@ /* MMIO base address for MEI interface */ static u8 *mei_base_address;
-#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -88,9 +90,6 @@ break; } } -#else -# define mei_dump(ptr, dword, offset, type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -483,7 +482,6 @@ vers_name->hotfix_version, vers_name->build_version); }
-#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -536,7 +534,6 @@ print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif
/* Send END OF POST message to the ME */ static int mkhi_end_of_post(void) @@ -804,9 +801,8 @@ { me_print_fw_version(mbp_data->fw_version_name);
-#if CONFIG(DEBUG_INTEL_ME) - me_print_fwcaps(mbp_data->fw_capabilities); -#endif + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data->fw_capabilities);
if (mbp_data->plat_time) { printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", @@ -912,12 +908,12 @@ }
/* Dump out the MBP contents. */ -#if CONFIG(DEBUG_INTEL_ME) - printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); - for (i = 0; i < mbp->header.mbp_size - 1; i++) - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); -#endif + if (CONFIG(DEBUG_INTEL_ME)) { + printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", + mbp->header.num_entries, mbp->header.mbp_size); + for (i = 0; i < mbp->header.mbp_size - 1; i++) + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + }
#define ASSIGN_FIELD_PTR(field_, val_) \ { \ diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 08fd48f..1880da1 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -34,8 +34,6 @@ memcpy(ptr, &dword, sizeof(dword)); }
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -210,6 +208,9 @@
void intel_me_status(void) { + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + struct me_hfs _hfs, *hfs = &_hfs; struct me_hfs2 _hfs2, *hfs2 = &_hfs2;
@@ -302,7 +303,6 @@ } printk(BIOS_DEBUG, "\n"); } -#endif
void intel_me_hsio_version(uint16_t *version, uint16_t *checksum) { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index ea60085..5e355a1 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -60,11 +60,13 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address;
-#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -90,9 +92,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -373,9 +372,8 @@ } #endif
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) /* Get ME firmware version */ -static int mkhi_get_fw_version(void) +static int __unused mkhi_get_fw_version(void) { struct me_fw_version version; struct mkhi_header mkhi = { @@ -412,7 +410,7 @@ }
/* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(void) +static int __unused mkhi_get_fwcaps(void) { u32 rule_id = 0; struct me_fwcaps cap; @@ -454,7 +452,6 @@
return 0; } -#endif
#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -714,12 +711,12 @@ if (intel_mei_setup(dev) < 0) break;
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* Print ME firmware version */ - mkhi_get_fw_version(); - /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + /* Print ME firmware version */ + mkhi_get_fw_version(); + /* Print ME firmware capabilities */ + mkhi_get_fwcaps(); + }
/* * Leave the ME unlocked in this path. diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 54c3fff..c224cb4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -62,11 +62,14 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address;
-#if CONFIG(DEBUG_INTEL_ME) + static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -92,9 +95,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -350,14 +350,13 @@ return 0; }
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", name, state ? " en" : "dis"); }
-static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name->major_version) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -395,7 +394,7 @@ }
/* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_fw_caps *caps_section) +static void __unused me_print_fwcaps(mbp_fw_caps *caps_section) { mefwcaps_sku *cap = &caps_section->fw_capabilities; if (!caps_section->available) { @@ -421,7 +420,6 @@ print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif
#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -719,10 +717,10 @@ } #endif
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(&mbp_data.fw_version_name); - me_print_fwcaps(&mbp_data.fw_caps_sku); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + me_print_fw_version(&mbp_data.fw_version_name); + me_print_fwcaps(&mbp_data.fw_caps_sku); + }
/* * Leave the ME unlocked in this path. diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index b202376..4d9540a 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -18,7 +18,6 @@ #include <console/console.h> #include "me.h"
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -137,11 +136,12 @@ [0x0f] = "ME cannot access the chipset descriptor region", [0x10] = "Required VSCC values for flash parts do not match", }; -#endif
void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) { -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); @@ -204,5 +204,4 @@ printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state); } printk(BIOS_DEBUG, "\n"); -#endif } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index f804126..c944f63 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -59,11 +59,13 @@ /* MMIO base address for MEI interface */ static u32 *mei_base_address;
-#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -89,9 +91,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 59a8666..1c45e2d 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -66,11 +66,13 @@ void intel_me_mbp_clear(struct device *dev); #endif
-#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr;
+ if (!CONFIG(DEBUG_INTEL_ME)) + return; + printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
switch (offset) { @@ -96,9 +98,6 @@ break; } } -#else -# define mei_dump(ptr,dword,offset,type) do {} while (0) -#endif
/* * ME/MEI access helpers using memcpy to avoid aliasing. @@ -380,7 +379,6 @@ return mei_wait_for_me_ready(); }
-#if CONFIG(DEBUG_INTEL_ME) || defined(__SMM__) static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, void *req_data, int req_bytes, void *rsp_data, int rsp_bytes) @@ -418,7 +416,6 @@
return 0; } -#endif /* CONFIG_DEBUG_INTEL_ME || __SMM__ */
/* * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read @@ -469,8 +466,7 @@ } }
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) -static void me_print_fw_version(mbp_fw_version_name *vers_name) +static void __unused me_print_fw_version(mbp_fw_version_name *vers_name) { if (!vers_name) { printk(BIOS_ERR, "ME: mbp missing version report\n"); @@ -482,7 +478,6 @@ vers_name->hotfix_version, vers_name->build_version); }
-#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -510,7 +505,7 @@ }
/* Get ME Firmware Capabilities */ -static void me_print_fwcaps(mbp_mefwcaps *cap) +static void __unused me_print_fwcaps(mbp_mefwcaps *cap) { mbp_mefwcaps local_caps; if (!cap) { @@ -535,8 +530,6 @@ print_cap("TLS", cap->tls); print_cap("Wireless LAN (WLAN)", cap->wlan); } -#endif /* CONFIG_DEBUG_INTEL_ME */ -#endif
#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ @@ -851,21 +844,21 @@ if (intel_me_read_mbp(&mbp_data, dev)) return;
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - me_print_fw_version(mbp_data.fw_version_name); -#if CONFIG(DEBUG_INTEL_ME) - me_print_fwcaps(mbp_data.fw_capabilities); -#endif + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + me_print_fw_version(mbp_data.fw_version_name);
- if (mbp_data.plat_time) { - printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", - mbp_data.plat_time->wake_event_mrst_time_ms); - printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", - mbp_data.plat_time->mrst_pltrst_time_ms); - printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", - mbp_data.plat_time->pltrst_cpurst_time_ms); + if (CONFIG(DEBUG_INTEL_ME)) + me_print_fwcaps(mbp_data.fw_capabilities); + + if (mbp_data.plat_time) { + printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", + mbp_data.plat_time->wake_event_mrst_time_ms); + printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", + mbp_data.plat_time->mrst_pltrst_time_ms); + printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", + mbp_data.plat_time->pltrst_cpurst_time_ms); + } } -#endif
/* Set clock enables according to devicetree */ if (config && config->icc_clock_disable) @@ -1004,15 +997,15 @@ #endif
/* Dump out the MBP contents. */ -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); -#if CONFIG(DEBUG_INTEL_ME) - for (i = 0; i < mbp->header.mbp_size - 1; i++) { - printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { + printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", + mbp->header.num_entries, mbp->header.mbp_size); + if (CONFIG(DEBUG_INTEL_ME)) { + for (i = 0; i < mbp->header.mbp_size - 1; i++) { + printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); + } + } } -#endif -#endif
#define ASSIGN_FIELD_PTR(field_,val_) \ { \ diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 9ca5552..ad8362d 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -18,7 +18,6 @@ #include <console/console.h> #include "me.h"
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -138,11 +137,12 @@ [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region", [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", }; -#endif
void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) { -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG) + return; + /* Check Current States */ printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfs->fpt_bad ? "BAD" : "OK"); @@ -206,5 +206,4 @@ hfs2->progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); -#endif }
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