Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81803?usp=email )
Change subject: soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP ......................................................................
soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP
IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and `PchPcieClockGating` UPDs, so, remove the preprocessor check that only enabled it for AlderLake FSPs.
Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177 Signed-off-by: Benjamin Doron benjamin.doron@9elements.com --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/81803/1
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 33ebee3..ff5c83c 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -932,7 +932,7 @@ } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
-#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_RAPTORLAKE) +#if CONFIG(FSP_TYPE_IOT) /* * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1